fix(mpu): perform RMW and inst barrier on mpu enable

danielRep · miguelafsilva5 · commit a7a49c5056ba · 2025-09-16T16:19:47.000+01:00
Signed-off-by: Daniel Oliveira &lt;drawnpoetry@gmail.com&gt;
diff --git a/src/arch/armv8/armv8-r/aarch32/boot.S b/src/arch/armv8/armv8-r/aarch32/boot.S
@@ -50,7 +50,7 @@ boot_arch_profile_init:
     /* r4 contains the id of the MPU entry being used */
     mov r4, #(-1)
 
-    /* Enable caches and MPU */
+    /* Enable caches */
     ldr r4, =(SCTLR_RES1_AARCH32 | SCTLR_C | SCTLR_I)
     mcr p15, 4, r4, c1, c0, 0 // HSCTLR
 
diff --git a/src/arch/armv8/armv8-r/mpu.c b/src/arch/armv8/armv8-r/mpu.c
@@ -199,7 +199,13 @@ bool mpu_perms_compatible(unsigned long perms1, unsigned long perms2)
 
 void mpu_enable(void)
 {
-    sysreg_sctlr_el2_write(SCTLR_M);
+    unsigned long reg_val;
+
+    reg_val = sysreg_sctlr_el2_read();
+    reg_val |= SCTLR_M;
+    sysreg_sctlr_el2_write(reg_val);
+
+    ISB();
 }
 
 void mpu_init()

Original file line number	Diff line number	Diff line change
`@@ -199,7 +199,13 @@ bool mpu_perms_compatible(unsigned long perms1, unsigned long perms2)`
`199`	`199`
`200`	`200`	`void mpu_enable(void)`
`201`	`201`	`{`
`202`		`- sysreg_sctlr_el2_write(SCTLR_M);`
	`202`	`+ unsigned long reg_val;`
	`203`	`+`
	`204`	`+ reg_val = sysreg_sctlr_el2_read();`
	`205`	`+ reg_val \|= SCTLR_M;`
	`206`	`+ sysreg_sctlr_el2_write(reg_val);`
	`207`	`+`
	`208`	`+ ISB();`
`203`	`209`	`}`
`204`	`210`
`205`	`211`	`void mpu_init()`