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This commit introduces a separation of input and output conventions for
hypercalls, addressing architecture-specific differences between ARM
and RISC-V. On ARM, the x0 register is used to pass both the extid,
fid, and the return value, while additional parameters (hypercalls arguments)
are passed via registers x1 to xn. On RISC-V, while the return value is
passed in a0, the extid and fid are handled by the a7 and a6 registers,
respectively. This means that the hypercall input arguments on RISC-V
should be passed through registers a0 to a5, while output hypercall
arguments are passed via a2 and onward (because all registers except
a0 and a1 must be preserved across an SBI call by the callee).
To accommodate these differences and provide a uniform interface,
two macros were introduced to abstract the handling of input and output
hypercall arguments across architectures.
Signed-off-by: João Peixoto <[email protected]>
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