fix: Remove implicit type and sign casts

With the additional compiler flags, most implicit casts are not allowed.
This commit achieves this by forcing explicit casts, refactoring some variable
types and fixing literal values.

Signed-off-by: Miguel Silva <[email protected]>

Author: miguelafsilva5

src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h

@@ -55,8 +55,8 @@
     }                                                                                       \
     static inline void sysreg_##reg##_write(unsigned long long val)                         \
     {                                                                                       \
-        sysreg_##reg1##_write(val);                                                         \
-        sysreg_##reg2##_write(val >> 32);                                                   \
+        sysreg_##reg1##_write((unsigned long)val);                                          \
+        sysreg_##reg2##_write((unsigned long)(val >> 32));                                  \
     }
 
 /**
@@ -83,8 +83,9 @@ SYSREG_GEN_ACCESSORS(cptr_el2, 4, c1, c1, 2)   // hcptr
 SYSREG_GEN_ACCESSORS(vtcr_el2, 4, c2, c1, 2)
 SYSREG_GEN_ACCESSORS_64(vttbr_el2, 6, c2)
 SYSREG_GEN_ACCESSORS(tpidr_el2, 4, c13, c0, 2) // htpidr
-SYSREG_GEN_ACCESSORS(ccsidr_el1, 1, c0, c0, 0)
+SYSREG_GEN_ACCESSORS(ccsidr, 1, c0, c0, 0)
 SYSREG_GEN_ACCESSORS(ccsidr2, 1, c0, c0, 2)
+SYSREG_GEN_ACCESSORS_MERGE(ccsidr_el1, ccsidr, ccsidr2)
 SYSREG_GEN_ACCESSORS(hmair0, 4, c10, c2, 0)
 SYSREG_GEN_ACCESSORS(hmair1, 4, c10, c2, 1)
 SYSREG_GEN_ACCESSORS_MERGE(mair_el2, hmair0, hmair1)

src/arch/armv8/aborts.c

@@ -22,7 +22,7 @@ void aborts_data_lower(unsigned long iss, unsigned long far, unsigned long il, u
         ERROR("no information to handle data abort (0x%x)", far);
     }
 
-    unsigned long DSFC = bit64_extract(iss, ESR_ISS_DA_DSFC_OFF, ESR_ISS_DA_DSFC_LEN) & (0xf << 2);
+    unsigned long DSFC = bit_extract(iss, ESR_ISS_DA_DSFC_OFF, ESR_ISS_DA_DSFC_LEN) & (0xf << 2);
 
     if (DSFC != ESR_ISS_DA_DSFC_TRNSLT && DSFC != ESR_ISS_DA_DSFC_PERMIS) {
         ERROR("data abort is not translation fault - cant deal with it");
@@ -33,11 +33,11 @@ void aborts_data_lower(unsigned long iss, unsigned long far, unsigned long il, u
     if (handler != NULL) {
         struct emul_access emul;
         emul.addr = addr;
-        emul.width = (1 << bit64_extract(iss, ESR_ISS_DA_SAS_OFF, ESR_ISS_DA_SAS_LEN));
+        emul.width = (1U << bit_extract(iss, ESR_ISS_DA_SAS_OFF, ESR_ISS_DA_SAS_LEN));
         emul.write = iss & ESR_ISS_DA_WnR_BIT ? true : false;
-        emul.reg = bit64_extract(iss, ESR_ISS_DA_SRT_OFF, ESR_ISS_DA_SRT_LEN);
-        emul.reg_width = 4 + (4 * bit64_extract(iss, ESR_ISS_DA_SF_OFF, ESR_ISS_DA_SF_LEN));
-        emul.sign_ext = bit64_extract(iss, ESR_ISS_DA_SSE_OFF, ESR_ISS_DA_SSE_LEN);
+        emul.reg = bit_extract(iss, ESR_ISS_DA_SRT_OFF, ESR_ISS_DA_SRT_LEN);
+        emul.reg_width = 4 + (4 * bit_extract(iss, ESR_ISS_DA_SF_OFF, ESR_ISS_DA_SF_LEN));
+        emul.sign_ext = bit_extract(iss, ESR_ISS_DA_SSE_OFF, ESR_ISS_DA_SSE_LEN);
 
         // TODO: check if the access is aligned. If not, inject an exception in the vm
 
@@ -56,15 +56,15 @@ long int standard_service_call(unsigned long _fn_num)
 {
     UNUSED_ARG(_fn_num);
 
-    int64_t ret = -1;
+    long int ret = -1;
 
     unsigned long smc_fid = vcpu_readreg(cpu()->vcpu, 0);
     unsigned long x1 = vcpu_readreg(cpu()->vcpu, 1);
     unsigned long x2 = vcpu_readreg(cpu()->vcpu, 2);
     unsigned long x3 = vcpu_readreg(cpu()->vcpu, 3);
 
     if (is_psci_fid(smc_fid)) {
-        ret = psci_smc_handler(smc_fid, x1, x2, x3);
+        ret = psci_smc_handler((uint32_t)smc_fid, x1, x2, x3);
     } else {
         INFO("unknown smc_fid 0x%lx", smc_fid);
     }
@@ -96,7 +96,7 @@ static inline void syscall_handler(unsigned long iss, unsigned long far, unsigne
             WARNING("Unknown system call fid 0x%x", fid);
     }
 
-    vcpu_writereg(cpu()->vcpu, 0, ret);
+    vcpu_writereg(cpu()->vcpu, 0, (unsigned long)ret);
 }
 
 void hvc_handler(unsigned long iss, unsigned long far, unsigned long il, unsigned long ec)
@@ -145,8 +145,8 @@ void sysreg_handler(unsigned long iss, unsigned long far, unsigned long il, unsi
         emul.addr = reg_addr;
         emul.width = 8;
         emul.write = iss & ESR_ISS_SYSREG_DIR ? false : true;
-        emul.reg = bit64_extract(iss, ESR_ISS_SYSREG_REG_OFF, ESR_ISS_SYSREG_REG_LEN);
-        emul.reg_high = bit64_extract(iss, ESR_ISS_SYSREG_REG2_OFF, ESR_ISS_SYSREG_REG2_LEN);
+        emul.reg = bit_extract(iss, ESR_ISS_SYSREG_REG_OFF, ESR_ISS_SYSREG_REG_LEN);
+        emul.reg_high = bit_extract(iss, ESR_ISS_SYSREG_REG2_OFF, ESR_ISS_SYSREG_REG2_LEN);
         emul.reg_width = 8;
         emul.multi_reg = (ec == ESR_EC_RG_64) ? true : false;
         emul.sign_ext = false;
@@ -187,9 +187,9 @@ void aborts_sync_handler()
         ipa_fault_addr = far;
     }
 
-    unsigned long ec = bit64_extract(esr, ESR_EC_OFF, ESR_EC_LEN);
-    unsigned long il = bit64_extract(esr, ESR_IL_OFF, ESR_IL_LEN);
-    unsigned long iss = bit64_extract(esr, ESR_ISS_OFF, ESR_ISS_LEN);
+    unsigned long ec = bit_extract(esr, ESR_EC_OFF, ESR_EC_LEN);
+    unsigned long il = bit_extract(esr, ESR_IL_OFF, ESR_IL_LEN);
+    unsigned long iss = bit_extract(esr, ESR_ISS_OFF, ESR_ISS_LEN);
 
     abort_handler_t handler = abort_handlers[ec];
     if (handler) {

src/arch/armv8/armv8-a/aarch32/vmm.c

@@ -16,7 +16,7 @@ void vmm_arch_init_tcr()
 
     cpu_sync_barrier(&cpu_glb_sync);
 
-    uint64_t vtcr = VTCR_RES1 | VTCR_ORGN0_WB_RA_WA | VTCR_IRGN0_WB_RA_WA | VTCR_T0SZ(0) |
+    unsigned long vtcr = VTCR_RES1 | VTCR_ORGN0_WB_RA_WA | VTCR_IRGN0_WB_RA_WA | VTCR_T0SZ(0) |
         VTCR_SH0_IS | VTCR_SL0_12;
 
     sysreg_vtcr_el2_write(vtcr);

src/arch/armv8/armv8-a/inc/arch/iommu.h

@@ -11,7 +11,7 @@
 
 struct iommu_vm_arch {
     streamid_t global_mask;
-    size_t ctx_id;
+    ssize_t ctx_id;
 };
 
 #endif

src/arch/armv8/armv8-a/inc/arch/smmuv2.h

@@ -8,23 +8,23 @@
 
 #include <bao.h>
 
-#define SMMUV2_CR0_GFRE                 (0x1 << 1)
-#define SMMUV2_CR0_GFIE                 (0x1 << 2)
-#define SMMUV2_CR0_GCFGFRE              (0x1 << 4)
-#define SMMUV2_CR0_GCFGFIE              (0x1 << 5)
-#define SMMUV2_CR0_USFCFG               (0x1 << 10)
-#define SMMUV2_CR0_SMCFCFG              (0x1 << 21)
-#define SMMUV2_CR0_CLIENTPD             (0x1 << 0)
+#define SMMUV2_CR0_GFRE                 (0x1U << 1)
+#define SMMUV2_CR0_GFIE                 (0x1U << 2)
+#define SMMUV2_CR0_GCFGFRE              (0x1U << 4)
+#define SMMUV2_CR0_GCFGFIE              (0x1U << 5)
+#define SMMUV2_CR0_USFCFG               (0x1U << 10)
+#define SMMUV2_CR0_SMCFCFG              (0x1U << 21)
+#define SMMUV2_CR0_CLIENTPD             (0x1U << 0)
 
-#define SMMUV2_CR0_CLEAR(cr0)           (cr0 & (0x3 << 30 | 0x1 << 11))
+#define SMMUV2_CR0_CLEAR(cr0)           (cr0 & (0x3U << 30 | 0x1U << 11))
 
 #define SMMUV2_IDR0_MASK                (0xFF)
 #define SMMUV2_IDR0_S2TS_BIT            (0x1 << 30)
 #define SMMUV2_IDR0_SMS_BIT             (0x1 << 27)
 #define SMMUV2_IDR0_CTTW_BIT            (0x1 << 14)
 #define SMMUV2_IDR0_BTM_BIT             (0x1 << 13)
 
-#define SMMUV2_IDR1_PAGESIZE_BIT        (0x1 << 31)
+#define SMMUV2_IDR1_PAGESIZE_BIT        (0x1U << 31)
 #define SMMUV2_IDR1_NUMCB_OFF           (0)
 #define SMMUV2_IDR1_NUMCB_LEN           (8)
 #define SMMUV2_IDR1_NUMPAGEDXB_OFF      (28)
@@ -49,7 +49,7 @@
 #define SMMU_SMR_MASK_LEN               15
 #define SMMU_SMR_MASK(smr)              bit32_extract(smr, SMMU_SMR_MASK_OFF, SMMU_SMR_MASK_LEN)
 
-#define SMMUV2_SMR_VALID                (0x1 << 31)
+#define SMMUV2_SMR_VALID                (0x1U << 31)
 
 #define S2CR_IMPL_OFF                   (30)
 #define S2CR_IMPL_LEN                   (2)
@@ -282,7 +282,7 @@ struct smmu_glbl_rs1_hw {
 #define SMMUV2_SCTLR_BSU_OSH       (0x2 << 14)
 #define SMMUV2_SCTLR_BSU_SYS       (0x3 << 14)
 
-#define SMMUV2_SCTLR_CLEAR(sctlr)  (sctlr & (0xF << 28 | 0x1 << 20 | 0xF << 9 | 0x1 << 11))
+#define SMMUV2_SCTLR_CLEAR(sctlr)  (sctlr & (0xFU << 28 | 0x1U << 20 | 0xFU << 9 | 0x1U << 11))
 
 #define SMMUV2_SCTLR_DEFAULT       (SMMUV2_SCTLR_CFCFG | SMMUV2_SCTLR_M)
 

src/arch/armv8/armv8-a/iommu.c

@@ -21,14 +21,14 @@ bool iommu_arch_init()
 
 static ssize_t iommu_vm_arch_init_ctx(struct vm* vm)
 {
-    ssize_t ctx_id = vm->io.prot.mmu.ctx_id;
+    ssize_t ctx_id = (ssize_t)vm->io.prot.mmu.ctx_id;
     if (ctx_id < 0) {
         /* Set up ctx bank to vm address space in an available ctx. */
         ctx_id = smmu_alloc_ctxbnk();
         if (ctx_id >= 0) {
             paddr_t rootpt;
             mem_translate(&cpu()->as, (vaddr_t)vm->as.pt.root, &rootpt);
-            smmu_write_ctxbnk(ctx_id, rootpt, vm->id);
+            smmu_write_ctxbnk((size_t)ctx_id, rootpt, vm->id);
             vm->io.prot.mmu.ctx_id = ctx_id;
         } else {
             INFO("iommu: smmuv2 could not allocate ctx for vm: %d", vm->id);
@@ -51,14 +51,14 @@ static bool iommu_vm_arch_add(struct vm* vm, streamid_t mask, streamid_t id)
         return false;
     }
 
-    if (!smmu_compatible_sme_exists(prep_mask, prep_id, vm_ctx, group)) {
+    if (!smmu_compatible_sme_exists(prep_mask, prep_id, (size_t)vm_ctx, group)) {
         ssize_t sme = smmu_alloc_sme();
         if (sme < 0) {
             INFO("iommu: smmuv2 no more free sme available.");
             return false;
         }
-        smmu_write_sme(sme, prep_mask, prep_id, group);
-        smmu_write_s2c(sme, vm_ctx);
+        smmu_write_sme((size_t)sme, prep_mask, prep_id, group);
+        smmu_write_s2c((size_t)sme, (size_t)vm_ctx);
     }
 
     return true;

src/arch/armv8/armv8-a/page_table.c

@@ -74,10 +74,10 @@ pte_t* pt_get_pte(struct page_table* pt, size_t lvl, vaddr_t va)
 
     size_t rec_ind_off = cpu_pt->dscr->lvl_off[cpu_pt->dscr->lvls - lvl - 1];
     size_t rec_ind_len = cpu_pt->dscr->lvl_wdt[cpu_pt->dscr->lvls - lvl - 1];
-    uintptr_t rec_ind_mask = PTE_MASK(rec_ind_off, rec_ind_len - rec_ind_off);
-    uintptr_t addr = cpu_pt->arch.rec_mask & ~PTE_MASK(0, rec_ind_len);
+    uintptr_t rec_ind_mask = (uintptr_t)PTE_MASK(rec_ind_off, rec_ind_len - rec_ind_off);
+    uintptr_t addr = (uintptr_t)(cpu_pt->arch.rec_mask & ~PTE_MASK(0, rec_ind_len));
     addr |= (pt->arch.rec_ind << rec_ind_off) & rec_ind_mask;
-    addr |= (va >> pt->dscr->lvl_off[lvl]) * sizeof(pte_t) & PTE_MASK(0, rec_ind_off);
+    addr |= (uintptr_t)((va >> pt->dscr->lvl_off[lvl]) * sizeof(pte_t) & PTE_MASK(0, rec_ind_off));
 
     return (pte_t*)addr;
 }

src/arch/armv8/armv8-a/psci.c

@@ -105,10 +105,10 @@ int32_t psci_power_down(enum wakeup_reason reason)
 
 int32_t psci_cpu_suspend(uint32_t power_state, unsigned long entrypoint, unsigned long context_id)
 {
-    return smc_call(PSCI_CPU_SUSPEND, power_state, entrypoint, context_id, NULL);
+    return (int32_t)smc_call(PSCI_CPU_SUSPEND, power_state, entrypoint, context_id, NULL);
 }
 
 int32_t psci_cpu_on(unsigned long target_cpu, unsigned long entrypoint, unsigned long context_id)
 {
-    return smc_call(PSCI_CPU_ON, target_cpu, entrypoint, context_id, NULL);
+    return (int32_t)smc_call(PSCI_CPU_ON, target_cpu, entrypoint, context_id, NULL);
 }

src/arch/armv8/armv8-a/smmuv2.c

@@ -129,8 +129,8 @@ void smmu_init()
     smmu.hw.glbl_rs0 = (struct smmu_glbl_rs0_hw*)smmu_glbl_rs0;
 
     size_t pg_size = smmu.hw.glbl_rs0->IDR1 & SMMUV2_IDR1_PAGESIZE_BIT ? 0x10000 : 0x1000;
-    size_t num_page = 1ULL << (bit32_extract(smmu.hw.glbl_rs0->IDR1, SMMUV2_IDR1_NUMPAGEDXB_OFF,
-                                   SMMUV2_IDR1_NUMPAGEDXB_LEN) +
+    size_t num_page = 1UL << (bit32_extract(smmu.hw.glbl_rs0->IDR1, SMMUV2_IDR1_NUMPAGEDXB_OFF,
+                                  SMMUV2_IDR1_NUMPAGEDXB_LEN) +
                           1);
     size_t ctx_bank_num =
         bit32_extract(smmu.hw.glbl_rs0->IDR1, SMMUV2_IDR1_NUMCB_OFF, SMMUV2_IDR1_NUMCB_LEN);
@@ -167,7 +167,7 @@ void smmu_init()
 
     for (size_t i = 0; i < smmu.ctx_num; i++) {
         smmu.hw.cntxt[i].SCTLR = 0;
-        smmu.hw.cntxt[i].FSR = -1;
+        smmu.hw.cntxt[i].FSR = ~0U;
     }
 
     /* Enable IOMMU. */
@@ -184,7 +184,7 @@ ssize_t smmu_alloc_ctxbnk()
     /* Find a free context bank. */
     ssize_t nth = bitmap_find_nth(smmu.ctxbank_bitmap, smmu.ctx_num, 1, 0, false);
     if (nth >= 0) {
-        bitmap_set(smmu.ctxbank_bitmap, nth);
+        bitmap_set(smmu.ctxbank_bitmap, (size_t)nth);
     }
     spin_unlock(&smmu.ctx_lock);
 
@@ -249,7 +249,7 @@ ssize_t smmu_alloc_sme()
     /* Find a free sme. */
     ssize_t nth = bitmap_find_nth(smmu.sme_bitmap, smmu.sme_num, 1, 0, false);
     if (nth >= 0) {
-        bitmap_set(smmu.sme_bitmap, nth);
+        bitmap_set(smmu.sme_bitmap, (size_t)nth);
     }
     spin_unlock(&smmu.sme_lock);
 

src/arch/armv8/armv8-r/mpu.c

@@ -116,7 +116,7 @@ static inline void mpu_entry_set_perms(struct mp_region* mpr, struct mpu_perms m
     bool el1_priv = mpu_perms.el1 != PERM_NONE;
     perms_t perms = mpu_perms.el1 | mpu_perms.el2;
 
-    mpr->mem_flags.prbar &= ~(PRBAR_PERMS_FLAGS_MSK);
+    mpr->mem_flags.prbar &= (uint16_t) ~(PRBAR_PERMS_FLAGS_MSK);
     if (perms & PERM_W) {
         mpr->mem_flags.prbar |= PRBAR_AP_RW_EL2;
     } else {