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bartoldemanbartoldeman
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simx86: Eliminate TR1 static variable
Just read/write to ECX instead
1 parent d9f4f3e commit 4d80a74

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+60
-36
lines changed

1 file changed

+60
-36
lines changed

‎src/base/emu-i386/simx86/codegen-sim.c‎

Lines changed: 60 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,6 @@ static unsigned char *currentIG = NULL;
8484
/* working registers of the host CPU */
8585
static wkreg DR1; // "eax"
8686
static wkreg AR1; // "edi"
87-
static wkreg TR1; // "ecx"
8887
static flgtmp RFL;
8988

9089
/////////////////////////////////////////////////////////////////////////////
@@ -1515,13 +1514,14 @@ static unsigned int Gen_sim(const IGen *IG)
15151514
break;
15161515
case O_XLAT: {
15171516
unsigned int ofs = IG->p0;
1517+
unsigned int offset;
15181518
GTRACE1("XLAT",ofs);
15191519
AR1.d = CPULONG(ofs);
1520-
TR1.d = CPULONG(Ofs_EBX) + CPUBYTE(Ofs_AL);
1520+
offset = CPULONG(Ofs_EBX) + CPUBYTE(Ofs_AL);
15211521
if (mode & ADDR16) {
1522-
TR1.d &= 0xFFFF;
1522+
offset &= 0xFFFF;
15231523
}
1524-
AR1.d += TR1.d;
1524+
AR1.d += offset;
15251525
}
15261526
break;
15271527

@@ -2108,34 +2108,34 @@ static unsigned int Gen_sim(const IGen *IG)
21082108
AR1.d += CPUWORD(Ofs_DI);
21092109

21102110
}
2111-
TR1.d = (mode&(MREP|MREPNE)? CPUWORD(Ofs_CX) : 1);
21122111
}
21132112
else {
21142113
if (mode&MOVSSRC) {
21152114
AR1.d = CPULONG(ofs) + CPULONG(Ofs_ESI);
21162115
} else {
21172116
AR1.d = CPULONG(Ofs_XES) + CPULONG(Ofs_EDI);
21182117
}
2119-
TR1.d = (mode&(MREP|MREPNE)? CPULONG(Ofs_ECX) : 1);
21202118
}
21212119
}
21222120
break;
21232121

21242122
case O_MOVS_MovD: {
21252123
wkreg SR1, DR2, AR2;
2124+
unsigned int i;
21262125
DR2.d = CPUWORD(Ofs_SI); /* for overflow calc */
21272126
SR1.d = CPUWORD(Ofs_DI); /* for overflow calc */
21282127
AR2.d = CPULONG(Ofs_XES);
2129-
if (mode&ADDR16)
2128+
if (mode&ADDR16) {
21302129
AR2.d += CPUWORD(Ofs_DI);
2131-
else
2130+
i = (mode&(MREP|MREPNE)? CPUWORD(Ofs_CX) : 1);
2131+
} else {
21322132
AR2.d += CPULONG(Ofs_EDI);
2133+
i = (mode&(MREP|MREPNE)? CPULONG(Ofs_ECX) : 1);
2134+
}
21332135
do {
21342136
unsigned int minofs, bytesbefore, rest = 0;
21352137
int df = (CPUWORD(Ofs_FLAGS) & EFLAGS_DF? -1:1);
21362138
dosaddr_t src, dest;
2137-
unsigned int i;
2138-
i = TR1.d;
21392139
GTRACE4("O_MOVS_MovD",0xff,0xff,df,i);
21402140
if(i == 0)
21412141
break;
@@ -2195,7 +2195,7 @@ static unsigned int Gen_sim(const IGen *IG)
21952195
dest += 4; src += 4; }
21962196
}
21972197
}
2198-
TR1.d = rest;
2198+
i = rest;
21992199
AR2.d = dest;
22002200
AR1.d = src;
22012201
if(rest == 0) break;
@@ -2235,17 +2235,25 @@ static unsigned int Gen_sim(const IGen *IG)
22352235
}
22362236
} while (1);
22372237
AR2.d -= CPULONG(Ofs_XES);
2238-
if (mode&ADDR16)
2238+
if (mode&ADDR16) {
22392239
CPUWORD(Ofs_DI) = AR2.w.l;
2240-
else
2240+
if (mode&(MREP|MREPNE))
2241+
CPUWORD(Ofs_CX) = 0;
2242+
} else {
22412243
CPULONG(Ofs_EDI) = AR2.d;
2244+
if (mode&(MREP|MREPNE))
2245+
CPULONG(Ofs_ECX) = 0;
2246+
}
22422247
}
22432248
break;
22442249
case O_MOVS_LodD: {
22452250
int df = (CPUWORD(Ofs_FLAGS) & EFLAGS_DF? -1:1);
22462251
dosaddr_t addr;
22472252
unsigned int i;
2248-
i = TR1.d;
2253+
if (mode&ADDR16)
2254+
i = (mode&(MREP|MREPNE)? CPUWORD(Ofs_CX) : 1);
2255+
else
2256+
i = (mode&(MREP|MREPNE)? CPULONG(Ofs_ECX) : 1);
22492257
GTRACE4("O_MOVS_LodD",0xff,0xff,df,i);
22502258
if (mode&(MREP|MREPNE)) {
22512259
dbug_printf("odd: REP LODS %d\n",i);
@@ -2260,20 +2268,29 @@ static unsigned int Gen_sim(const IGen *IG)
22602268
else {
22612269
while (i--) { DR1.d = sim_read_dword(addr); addr += 4*df; }
22622270
}
2263-
if (mode&(MREP|MREPNE)) TR1.d = 0;
2271+
if (mode&(MREP|MREPNE)) {
2272+
if (mode&ADDR16)
2273+
CPUWORD(Ofs_CX) = 0;
2274+
else
2275+
CPULONG(Ofs_ECX) = 0;
2276+
}
22642277
AR1.d = addr;
22652278
// ! Warning DI,SI wrap in 16-bit mode
22662279
}
22672280
break;
22682281
case O_MOVS_StoD: {
22692282
wkreg SR1;
2283+
unsigned int i;
22702284
SR1.d = CPUWORD(Ofs_DI); /* for overflow calc */
2285+
if (mode&ADDR16)
2286+
i = (mode&(MREP|MREPNE)? CPUWORD(Ofs_CX) : 1);
2287+
else
2288+
i = (mode&(MREP|MREPNE)? CPULONG(Ofs_ECX) : 1);
22712289

22722290
do {
22732291
int df = (CPUWORD(Ofs_FLAGS) & EFLAGS_DF? -1:1);
22742292
dosaddr_t addr;
2275-
unsigned int i, rest = 0;
2276-
i = TR1.d;
2293+
unsigned int rest = 0;
22772294
GTRACE4("O_MOVS_StoD",0xff,0xff,df,i);
22782295
if((mode & ADDR16) && i) {
22792296
unsigned int minofs, bytesbefore;
@@ -2313,19 +2330,28 @@ static unsigned int Gen_sim(const IGen *IG)
23132330
while (i--) { sim_write_dword(addr, DR1.d); addr += 4*df; }
23142331
}
23152332
AR1.d = addr;
2316-
TR1.d = rest;
2333+
i = rest;
23172334
if (rest == 0) break;
23182335
SR1.d = (df == -1 ? 0xffff : 0);
23192336
AR1.d -= 0x10000*df;
23202337
} while (1);
2338+
if (mode&(MREP|MREPNE)) {
2339+
if (mode&ADDR16)
2340+
CPUWORD(Ofs_CX) = 0;
2341+
else
2342+
CPULONG(Ofs_ECX) = 0;
2343+
}
23212344
}
23222345
break;
23232346
case O_MOVS_ScaD: { // OSZAPC
23242347
int df = (CPUWORD(Ofs_FLAGS) & EFLAGS_DF? -1:1);
23252348
dosaddr_t addr;
23262349
unsigned int i;
23272350
char k, z;
2328-
i = TR1.d;
2351+
if (mode&ADDR16)
2352+
i = (mode&(MREP|MREPNE)? CPUWORD(Ofs_CX) : 1);
2353+
else
2354+
i = (mode&(MREP|MREPNE)? CPULONG(Ofs_ECX) : 1);
23292355
GTRACE4("O_MOVS_ScaD",0xff,0xff,df,i);
23302356
if (i == 0) break; /* eCX = 0, no-op, no flags updated */
23312357
z = k = (mode&MREP? 1:0);
@@ -2353,7 +2379,12 @@ static unsigned int Gen_sim(const IGen *IG)
23532379
i--;
23542380
}
23552381
AR1.d = addr;
2356-
TR1.d = i;
2382+
if (mode&(MREP|MREPNE)) {
2383+
if (mode&ADDR16)
2384+
CPUWORD(Ofs_CX) = i;
2385+
else
2386+
CPULONG(Ofs_ECX) = i;
2387+
}
23572388
// ! Warning DI,SI wrap in 16-bit mode
23582389
}
23592390
break;
@@ -2368,12 +2399,10 @@ static unsigned int Gen_sim(const IGen *IG)
23682399
AR2.d += CPUWORD(Ofs_DI);
23692400
else
23702401
AR2.d += CPULONG(Ofs_EDI);
2371-
i = TR1.d;
23722402
df = (CPUWORD(Ofs_FLAGS) & EFLAGS_DF? -1:1);
2373-
GTRACE4("O_MOVS_CmpD",0xff,0xff,df,i);
2374-
if (i == 0) break; /* eCX = 0, no-op, no flags updated */
23752403
addr1 = AR2.d;
23762404
if(!(mode & (MREP|MREPNE))) {
2405+
GTRACE4("O_MOVS_CmpD",0xff,0xff,df,1);
23772406
// assumes DR1=*AR1
23782407
if (mode&MBYTE) {
23792408
S1 = DR1.b.bl;
@@ -2390,6 +2419,9 @@ static unsigned int Gen_sim(const IGen *IG)
23902419
}
23912420
break;
23922421
}
2422+
i = (mode&ADDR16) ? CPUWORD(Ofs_CX) : CPULONG(Ofs_ECX);
2423+
GTRACE4("O_MOVS_CmpD",0xff,0xff,df,i);
2424+
if (i == 0) break; /* eCX = 0, no-op, no flags updated */
23932425
z = k = (mode&MREP? 1:0);
23942426
addr2 = AR1.d;
23952427
while (i && (z==k)) {
@@ -2414,15 +2446,17 @@ static unsigned int Gen_sim(const IGen *IG)
24142446
z = (RFL.res==0);
24152447
i--;
24162448
}
2417-
TR1.d = i;
24182449
AR2.d = addr1;
24192450
AR1.d = addr2;
24202451
// ! Warning DI,SI wrap in 16-bit mode
24212452
AR2.d -= CPULONG(Ofs_XES);
2422-
if (mode&ADDR16)
2453+
if (mode&ADDR16) {
24232454
CPUWORD(Ofs_DI) = AR2.w.l;
2424-
else
2455+
CPUWORD(Ofs_CX) = i;
2456+
} else {
24252457
CPULONG(Ofs_EDI) = AR2.d;
2458+
CPULONG(Ofs_ECX) = i;
2459+
}
24262460
}
24272461
break;
24282462

@@ -2447,9 +2481,6 @@ static unsigned int Gen_sim(const IGen *IG)
24472481
}
24482482
}
24492483
else if (mode&ADDR16) {
2450-
if (mode&(MREP|MREPNE)) {
2451-
CPUWORD(Ofs_CX) = TR1.w.l;
2452-
}
24532484
if (mode&MOVSSRC) {
24542485
AR1.d -= CPULONG(ofs);
24552486
CPUWORD(Ofs_SI) = AR1.w.l;
@@ -2459,9 +2490,6 @@ static unsigned int Gen_sim(const IGen *IG)
24592490
}
24602491
}
24612492
else {
2462-
if (mode&(MREP|MREPNE)) {
2463-
CPULONG(Ofs_ECX) = TR1.d;
2464-
}
24652493
if (mode&MOVSSRC) {
24662494
AR1.d -= CPULONG(ofs);
24672495
CPULONG(Ofs_ESI) = AR1.d;
@@ -2803,8 +2831,6 @@ static unsigned int Gen_sim(const IGen *IG)
28032831
#endif
28042832
dbug_printf("(R) DR1=%08x AR1=%08x\n",
28052833
DR1.d,AR1.d);
2806-
dbug_printf("(R) TR1=%08x\n",
2807-
TR1.d);
28082834
dbug_printf("(R) RFL cout=%08x RES=%08x\n",
28092835
RFL.cout,RFL.res);
28102836
// if (debug_level('e')==9) dbug_printf("\n%s",e_print_regs());
@@ -2859,8 +2885,6 @@ static unsigned Exec_sim(unsigned *mem_ref, unsigned long *flg,
28592885
{
28602886
dbug_printf("(R) DR1=%08x AR1=%08x\n",
28612887
DR1.d,AR1.d);
2862-
dbug_printf("(R) TR1=%08x\n",
2863-
TR1.d);
28642888
dbug_printf("(R) RFL cout=%08x RES=%08x\n\n",
28652889
RFL.cout,RFL.res);
28662890
}

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