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bartoldemanbartoldeman
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simx86, Gen_sim: remove now unused RFL.valid
1 parent b7ffbcd commit 4fb8144

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2 files changed

+4
-43
lines changed

2 files changed

+4
-43
lines changed

‎src/base/emu-i386/simx86/codegen-sim.c‎

Lines changed: 4 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -191,7 +191,6 @@ static inline void FlagHandleIncDec(unsigned low, unsigned high, int wordsize)
191191
if (wordsize == 32) RFL.cout = cout & ~(LF_MASK_SD|LF_MASK_PD);
192192
if (wordsize == 16) RFL.cout = (cout << 16) | (cout & LF_MASK_AF);
193193
if (wordsize == 8) RFL.cout = (cout << 24) | (cout & LF_MASK_AF);
194-
RFL.valid = V_ADD;
195194
SET_CF(oldcy);
196195
}
197196

@@ -616,7 +615,6 @@ unsigned int Gen_sim(const IGen *IG)
616615
case O_ADD_R: { // OSZAPC
617616
register wkreg v;
618617
v.d = IG->p0;
619-
RFL.valid = V_ADD;
620618
if (mode & IMMED) {GTRACE3("O_ADD_R",0xff,0xff,v.d);}
621619
else {GTRACE3("O_ADD_R",v.bs.bl,0xff,v.d);}
622620
if (mode & MBYTE) {
@@ -645,7 +643,6 @@ unsigned int Gen_sim(const IGen *IG)
645643
break;
646644
case O_OR_R: { // O=0 SZP C=0
647645
int v = IG->p0;
648-
RFL.valid = V_GEN;
649646
if (mode & IMMED) {GTRACE3("O_OR_R",0xff,0xff,v);}
650647
else {GTRACE3("O_OR_R",v,0xff,v);}
651648
if (mode & MBYTE) {
@@ -666,7 +663,6 @@ unsigned int Gen_sim(const IGen *IG)
666663
break;
667664
case O_AND_R: { // O=0 SZP C=0
668665
int v = IG->p0;
669-
RFL.valid = V_GEN;
670666
if (mode & IMMED) {GTRACE3("O_AND_R",0xff,0xff,v);}
671667
else {GTRACE3("O_AND_R",v,0xff,v);}
672668
if (mode & MBYTE) {
@@ -687,7 +683,6 @@ unsigned int Gen_sim(const IGen *IG)
687683
break;
688684
case O_XOR_R: { // O=0 SZP C=0
689685
int v = IG->p0;
690-
RFL.valid = V_GEN;
691686
if (mode & IMMED) {GTRACE3("O_XOR_R",0xff,0xff,v);}
692687
else {GTRACE3("O_XOR_R",v,0xff,v);}
693688
if (mode & MBYTE) {
@@ -709,7 +704,6 @@ unsigned int Gen_sim(const IGen *IG)
709704
case O_SUB_R: { // OSZAPC
710705
register wkreg v;
711706
v.d = IG->p0;
712-
RFL.valid = V_SUB;
713707
if (mode & IMMED) {GTRACE3("O_SUB_R",0xff,0xff,v.d);}
714708
else {GTRACE3("O_SUB_R",v.bs.bl,0xff,v.d);}
715709
if (mode & MBYTE) {
@@ -739,7 +733,6 @@ unsigned int Gen_sim(const IGen *IG)
739733
case O_CMP_R: { // OSZAPC
740734
register wkreg v;
741735
v.d = IG->p0;
742-
RFL.valid = V_SUB;
743736
if (mode & IMMED) {GTRACE3("O_CMP_R",0xff,0xff,v.d);}
744737
else {GTRACE3("O_CMP_R",v.bs.bl,0xff,v.d);}
745738
if (mode & MBYTE) {
@@ -767,7 +760,6 @@ unsigned int Gen_sim(const IGen *IG)
767760
int cy;
768761
v.d = IG->p0;
769762
cy = is_cf_set();
770-
RFL.valid = (cy? V_ADC:V_ADD);
771763
if (mode & IMMED) {GTRACE3("O_ADC_R",0xff,0xff,v.d);}
772764
else {GTRACE3("O_ADC_R",v.bs.bl,0xff,v.d);}
773765
if (mode & MBYTE) {
@@ -799,7 +791,6 @@ unsigned int Gen_sim(const IGen *IG)
799791
int cy;
800792
v.d = IG->p0;
801793
cy = is_cf_set();
802-
RFL.valid = V_SBB;
803794
if (mode & IMMED) {GTRACE3("O_SBB_R",0xff,0xff,v.d);}
804795
else {GTRACE3("O_SBB_R",v.bs.bl,0xff,v.d);}
805796
if (mode & MBYTE) {
@@ -841,13 +832,11 @@ unsigned int Gen_sim(const IGen *IG)
841832
}
842833
RFL.res = 0;
843834
RFL.cout &= LF_MASK_AF;
844-
RFL.valid = V_GEN;
845835
}
846836
break;
847837
case O_TEST: { // == OR r,r
848838
signed char o = (signed char)IG->p0;
849839
GTRACE1("O_TEST",o);
850-
RFL.valid = V_GEN;
851840
if (mode & MBYTE) {
852841
RFL.res = (int8_t)CPUBYTE(o);
853842
}
@@ -882,7 +871,6 @@ unsigned int Gen_sim(const IGen *IG)
882871
else {
883872
CPULONG(o) = RFL.res;
884873
}
885-
RFL.valid = V_SBB;
886874
}
887875
break;
888876
case O_INC_R: { // OSZAP
@@ -930,7 +918,6 @@ unsigned int Gen_sim(const IGen *IG)
930918
signed char o = (signed char)IG->p0;
931919
v.d = 0;
932920
if (mode & IMMED) v.d = IG->p1;
933-
RFL.valid = V_ADD;
934921
if (mode & IMMED) {GTRACE3("O_ADD_FR",0xff,0xff,v.d);}
935922
else {GTRACE3("O_ADD_FR",v.bs.bl,0xff,v.d);}
936923
if (mode & MBYTE) {
@@ -962,7 +949,6 @@ unsigned int Gen_sim(const IGen *IG)
962949
signed char o = (signed char)IG->p0;
963950
v.d = 0;
964951
if (mode & IMMED) v.d = IG->p1;
965-
RFL.valid = V_GEN;
966952
if (mode & IMMED) {GTRACE3("O_OR_FR",0xff,0xff,v.d);}
967953
else {GTRACE3("O_OR_FR",v.d,0xff,v.d);}
968954
if (mode & MBYTE) {
@@ -985,7 +971,6 @@ unsigned int Gen_sim(const IGen *IG)
985971
v.d = 0;
986972
if (mode & IMMED) v.d = IG->p1;
987973
cy = is_cf_set();
988-
RFL.valid = (cy? V_ADC:V_ADD);
989974
if (mode & IMMED) {GTRACE3("O_ADC_FR",0xff,0xff,v.d);}
990975
else {GTRACE3("O_ADC_FR",v.bs.bl,0xff,v.d);}
991976
if (mode & MBYTE) {
@@ -1019,7 +1004,6 @@ unsigned int Gen_sim(const IGen *IG)
10191004
v.d = 0;
10201005
if (mode & IMMED) v.d = IG->p1;
10211006
cy = is_cf_set();
1022-
RFL.valid = V_SBB;
10231007
if (mode & IMMED) {GTRACE3("O_SBB_FR",0xff,0xff,v.d);}
10241008
else {GTRACE3("O_SBB_FR",v.bs.bl,0xff,v.d);}
10251009
if (mode & MBYTE) {
@@ -1052,7 +1036,6 @@ unsigned int Gen_sim(const IGen *IG)
10521036
signed char o = (signed char)IG->p0;
10531037
v.d = 0;
10541038
if (mode & IMMED) v.d = IG->p1;
1055-
RFL.valid = V_GEN;
10561039
if (mode & IMMED) {GTRACE3("O_AND_FR",0xff,0xff,v.d);}
10571040
else {GTRACE3("O_AND_FR",v.d,0xff,v.d);}
10581041
if (mode & MBYTE) {
@@ -1073,7 +1056,6 @@ unsigned int Gen_sim(const IGen *IG)
10731056
signed char o = (signed char)IG->p0;
10741057
v.d = 0;
10751058
if (mode & IMMED) v.d = IG->p1;
1076-
RFL.valid = V_SUB;
10771059
if (mode & IMMED) {GTRACE3("O_SUB_FR",0xff,0xff,v.d);}
10781060
else {GTRACE3("O_SUB_FR",v.bs.bl,0xff,v.d);}
10791061
if (mode & MBYTE) {
@@ -1105,7 +1087,6 @@ unsigned int Gen_sim(const IGen *IG)
11051087
signed char o = (signed char)IG->p0;
11061088
v.d = 0;
11071089
if (mode & IMMED) v.d = IG->p1;
1108-
RFL.valid = V_GEN;
11091090
if (mode & IMMED) {GTRACE3("O_XOR_FR",0xff,0xff,v.d);}
11101091
else {GTRACE3("O_XOR_FR",v.d,0xff,v.d);}
11111092
if (mode & MBYTE) {
@@ -1126,7 +1107,6 @@ unsigned int Gen_sim(const IGen *IG)
11261107
signed char o = (signed char)IG->p0;
11271108
v.d = 0;
11281109
if (mode & IMMED) v.d = IG->p1;
1129-
RFL.valid = V_SUB;
11301110
if (mode & IMMED) {GTRACE3("O_CMP_FR",0xff,0xff,v.d);}
11311111
else {GTRACE3("O_CMP_FR",v.bs.bl,0xff,v.d);}
11321112
if (mode & MBYTE) {
@@ -1163,7 +1143,6 @@ unsigned int Gen_sim(const IGen *IG)
11631143
break;
11641144
case O_NEG: // OSZAPC
11651145
GTRACE0("O_NEG");
1166-
RFL.valid = V_SUB;
11671146
if (mode & MBYTE) {
11681147
DR1.bs.bl = -(S2 = DR1.b.bl);
11691148
FlagHandleSub(0, S2, DR1.bs.bl, 8);
@@ -1215,7 +1194,6 @@ unsigned int Gen_sim(const IGen *IG)
12151194
break;
12161195
case O_CMPXCHG: { // OSZAPC
12171196
signed char o = (signed char)IG->p0;
1218-
RFL.valid = V_SUB;
12191197
GTRACE1("O_CMPXCHG",o);
12201198
if (mode & MBYTE) {
12211199
S1 = CPUBYTE(Ofs_AL);
@@ -1289,7 +1267,6 @@ unsigned int Gen_sim(const IGen *IG)
12891267
case O_MUL: { // OC
12901268
int of;
12911269
GTRACE0("O_MUL");
1292-
RFL.valid = V_GEN;
12931270
if (mode & MBYTE) {
12941271
DR1.w.l =
12951272
(unsigned int)CPUBYTE(Ofs_AL) * (unsigned int)DR1.b.bl;
@@ -1321,7 +1298,6 @@ unsigned int Gen_sim(const IGen *IG)
13211298
break;
13221299
case O_IMUL: { // OC
13231300
int of;
1324-
RFL.valid = V_GEN;
13251301
if (mode & MBYTE) {
13261302
if ((mode&(IMMED|DATA16))==(IMMED|DATA16)) {
13271303
int b = IG->p0;
@@ -1659,7 +1635,6 @@ unsigned int Gen_sim(const IGen *IG)
16591635
// All flags unchanged (at least on PIII)
16601636
break;
16611637

1662-
RFL.valid = V_GEN;
16631638
if (mode & MBYTE)
16641639
rbef = DR1.b.bl;
16651640
else if (mode & DATA16)
@@ -1793,7 +1768,6 @@ unsigned int Gen_sim(const IGen *IG)
17931768
break; // shift count 0, flags unchanged, except OVFL
17941769
}
17951770

1796-
RFL.valid = V_GEN;
17971771
if (mode & MBYTE)
17981772
rbef = DR1.b.bl;
17991773
else if (mode & DATA16)
@@ -1837,7 +1811,6 @@ unsigned int Gen_sim(const IGen *IG)
18371811
break; // shift count 0, flags unchanged, except OVFL
18381812
}
18391813

1840-
RFL.valid = V_GEN;
18411814
if (mode & MBYTE)
18421815
rbef = DR1.bs.bl;
18431816
else if (mode & DATA16)
@@ -1868,7 +1841,6 @@ unsigned int Gen_sim(const IGen *IG)
18681841
unsigned char subop = IG->p1;
18691842
GTRACE3("O_OPAX",0xff,0xff,n);
18701843
int cy = is_cf_set();
1871-
RFL.valid = V_ADD;
18721844
SET_OF(0);
18731845
DR1.d = CPULONG(Ofs_EAX);
18741846
switch (subop) {
@@ -2399,7 +2371,6 @@ unsigned int Gen_sim(const IGen *IG)
23992371
i = TR1.d;
24002372
GTRACE4("O_MOVS_ScaD",0xff,0xff,df,i);
24012373
if (i == 0) break; /* eCX = 0, no-op, no flags updated */
2402-
RFL.valid = V_SUB;
24032374
z = k = (mode&MREP? 1:0);
24042375
addr = AR1.d;
24052376
while (i && (z==k)) {
@@ -2438,7 +2409,6 @@ unsigned int Gen_sim(const IGen *IG)
24382409
df = (CPUWORD(Ofs_FLAGS) & EFLAGS_DF? -1:1);
24392410
GTRACE4("O_MOVS_CmpD",0xff,0xff,df,i);
24402411
if (i == 0) break; /* eCX = 0, no-op, no flags updated */
2441-
RFL.valid = V_SUB;
24422412
addr1 = AR1.d;
24432413
if(!(mode & (MREP|MREPNE))) {
24442414
// assumes DR1=*AR2
@@ -2688,7 +2658,6 @@ unsigned int Gen_sim(const IGen *IG)
26882658
}
26892659
shc &= 31;
26902660
if (shc==0) break;
2691-
RFL.valid = V_GEN;
26922661
RFL.cout &= LF_MASK_AF;
26932662
if (mode & DATA16) {
26942663
if (l_r==0) { // left: <<reg|mem<<
@@ -2876,8 +2845,8 @@ unsigned int Gen_sim(const IGen *IG)
28762845
DR1.d,DR2.d,AR1.d,AR2.d);
28772846
dbug_printf("(R) SR1=%08x TR1=%08x\n",
28782847
SR1.d,TR1.d);
2879-
dbug_printf("(R) RFL v=%d cout=%08x RES=%08x\n",
2880-
RFL.valid,RFL.cout,RFL.res);
2848+
dbug_printf("(R) RFL cout=%08x RES=%08x\n",
2849+
RFL.cout,RFL.res);
28812850
// if (debug_level('e')==9) dbug_printf("\n%s",e_print_regs());
28822851
}
28832852

@@ -2925,8 +2894,8 @@ static unsigned Exec_sim(unsigned *mem_ref, unsigned long *flg,
29252894
DR1.d,DR2.d,AR1.d,AR2.d);
29262895
dbug_printf("(R) SR1=%08x TR1=%08x\n",
29272896
SR1.d,TR1.d);
2928-
dbug_printf("(R) RFL v=%d cout=%08x RES=%08x\n\n",
2929-
RFL.valid,RFL.cout,RFL.res);
2897+
dbug_printf("(R) RFL cout=%08x RES=%08x\n\n",
2898+
RFL.cout,RFL.res);
29302899
}
29312900

29322901
return P0;

‎src/base/emu-i386/simx86/codegen-sim.h‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -49,17 +49,9 @@ typedef union {
4949
} wkreg;
5050

5151
typedef struct {
52-
int valid;
5352
uint32_t cout, res;
5453
} flgtmp;
5554

56-
#define V_OSZAC 0
57-
#define V_GEN 1 // general case
58-
#define V_SUB 2
59-
#define V_SBB 3
60-
#define V_ADC 4
61-
#define V_ADD 5
62-
6355
/* same constants as used in Bochs and QEMU */
6456
#define LF_BIT_PD 2 /* lazy Parity Delta, same bit as PF */
6557
#define LF_BIT_AF 3 /* lazy Adjust flag */

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