simx86: handle popss/movss/sti inhibition at compile time

We force the generation of one more instruction within the same
block using a recursive call to InterpOne, so no interruption
is possible there. Then, for STI only, a signal check is generated
for the instuction past STI.

This cleans up the DoExec checks considerably.

Author: bartoldeman

src/base/emu-i386/simx86/codegen-sim.c

@@ -3310,7 +3310,6 @@ static unsigned int _Sim_helper(unsigned int mem_ref, unsigned int data, int mod
 					    EFLAGS);
 				/* force exit after next compiled block execution */
 				exit_pending_or(CeS_RPIC);
-				TheCPU.err = EXCP_STISHADOW;
 			    }
 			}
 			break;

src/base/emu-i386/simx86/codegen.c

@@ -458,16 +458,7 @@ static CodeBuf *ProduceCode(unsigned int PC, IMeta *I0)
 		cp1 = CodePtr;
 	    }
 	    I->len = CodePtr - cp;
-	    if (i > 0) {
-		/* F_INHI (pop ss/mov ss) only applies to the last
-		   instruction in the sequence and not twice in
-		   a row */
-		if ((I->flags & F_INHI) && !(I0->flags & F_INHI))
-		    I0->flags |= F_INHI;
-		else
-		    I0->flags &= ~F_INHI;
-		I0->flags |= I->flags & ~F_INHI;
-	    }
+	    I0->flags |= I->flags;
 	    if (debug_level('e')>3) {
 		if (debug_level('e')>4) {
 		    e_printf("Metadata %03d PC=%08x flags=%x(%x) ng=%d\n",
@@ -593,12 +584,7 @@ static void Exec_post(unsigned long flg, unsigned int mem_ref,
 {
 	EFLAGS = (EFLAGS & ~EFLAGS_CC) | (flg &	EFLAGS_CC);
 	TheCPU.mem_ref = mem_ref;
-	CEmuStat &= ~CeS_STI;
 	TheCPU.err = abs(TheCPU.err);
-	if (TheCPU.err == EXCP_STISHADOW) {
-		CEmuStat |= CeS_STI;
-		TheCPU.err = 0;
-	}
 	if (TheCPU.err == EXCP_TFSET)
 		TheCPU.err = 0;
 	/* checking for infinite loops, flagged in JumpGen() */
@@ -648,7 +634,6 @@ unsigned int DoExec(TNode *G, unsigned *pLastXKey)
 	unsigned int mem_ref;
 	unsigned int ePC;
 	unsigned short seqflg = G->flags;
-	int block_inhibit;
 #if defined(SINGLESTEP)
         unsigned int key = G->key;
 #endif
@@ -670,19 +655,14 @@ unsigned int DoExec(TNode *G, unsigned *pLastXKey)
 #endif
 	/* these flags need to be checked only once for the node */
 	G->flags &= ~(F_SPEC|F_LEAV);
-	/* if there is just one compiled instruction inhibition
-	   should be ignored unconditionally if signals and traps
-	   were already ignored, e.g. two "sti"s in a row */
-	block_inhibit = (seqflg & F_INHI) && G->seqnum == 1 &&
-	  (CEmuStat & CeS_INHI);
 	flg = Exec_pre(ecpu);
 #if !defined(ASM_DUMP) && !defined(SINGLESTEP)
 	/* try fast inner loop if nothing special is going on */
-	if (!(EFLAGS & TF) && !block_inhibit && !debug_level('e')) {
+	if (!(EFLAGS & TF) && !debug_level('e')) {
 		while (1) {
 			ePC = ExecOne(G, &mem_ref, &flg, ecpu, pLastXKey);
 			if (TheCPU.err || exit_pending() ||
-			    (seqflg & (F_INHI|F_SLFJ|F_SPEC|F_LEAV)))
+			    (seqflg & (F_SLFJ|F_SPEC|F_LEAV)))
 				break;
 			G = FindTree(ePC);
 			if (!G || !GoodNode(G))
@@ -717,14 +697,7 @@ unsigned int DoExec(TNode *G, unsigned *pLastXKey)
 	/* exit_pending at this point is non-zero if there was ANY signal,
 	 * not just a SIGALRM
 	 */
-	if (((seqflg & F_INHI) || (CEmuStat & CeS_STI)) && !block_inhibit) {
-		/* ignore signals and traps for movss/popss */
-		CEmuStat |= CeS_INHI;
-		CEmuStat &= ~CeS_TRAP;
-	} else {
-		CEmuStat &= ~(CeS_INHI|CeS_STI);
-		CEmuStat |= exit_pending_xchg(0);
-	}
+	CEmuStat |= exit_pending_xchg(0);
 
 #if defined(SINGLESTEP)
 	InvalidateNodeRange(key, 1, NULL);

src/base/emu-i386/simx86/codegen.h

@@ -188,12 +188,12 @@
 #define MREPCOND 0x01000000	// this is SCASx or CMPSx, REP can be terminated
 				// by flags
 #define MSSTP	0x02000000	// generate only one instruction
+#define MINHI	0x04000000	// inhibits IRQs (MOVss/POPss/STI)
 
 // values for TNode.flags and IMeta.flags
 #define F_FPOP	0x0001	// has at least one FP instruction
 #define F_SPEC	0x0002	// start speculative prejit when executing this node
 #define F_SLFL	0x0004	// links to itself
-#define F_INHI	0x0008	// inhibits IRQs (MOVss/POPss/STI)
 #define F_PREJ	0x0010	// generated by any prejit thread
 #define F_SPRJ	0x0020	// generated by speculative prejit thread
 #define F_LEAV	0x0040	// leave instremu after executing this node
@@ -216,7 +216,7 @@ static __inline__ int FastLog2(int v)
 /////////////////////////////////////////////////////////////////////////////
 
 void InitGen(void);
-int NewIMeta(int npc);
+int NewIMeta(int npc, int override);
 extern int CurrIMeta;
 extern void Gen(int op, int mode, ...);
 extern void AddrGen(int op, int mode, ...);

src/base/emu-i386/simx86/emu86.h

@@ -681,7 +681,6 @@ extern int SpecPrejits;
 #define EXCP_MODESWITCH	68
 #define EXCP_EMULEAVE	69
 #define EXCP_TFSET	71
-#define EXCP_STISHADOW	72
 
 /////////////////////////////////////////////////////////////////////////////
 

src/base/emu-i386/simx86/interp.c

@@ -383,7 +383,7 @@ static unsigned int FindExecCode(unsigned int PC)
 	while (1) {
 		if (EFLAGS & TF)
 			CEmuStat |= CeS_TRAP;
-		if (CEmuStat & (CeS_TRAP|CeS_STI))
+		if (CEmuStat & CeS_TRAP)
 			TheCPU.mode |= MSSTP;
 		else
 			TheCPU.mode &= ~MSSTP;
@@ -512,7 +512,7 @@ void Interp86(void)
       return;
     }
 
-    CEmuStat &= ~(CeS_TRAP|CeS_STI);
+    CEmuStat &= ~CeS_TRAP;
 
     PC = LONG_CS + TheCPU.eip;
     assert(CurrIMeta < 0);
@@ -607,7 +607,14 @@ static unsigned int InterpOne(unsigned int PC, unsigned int Interp_LONG_CS,
 	signed char OVERR_DS = Ofs_XDS;
 	signed char OVERR_SS = Ofs_XSS;
 
-	if (!NewIMeta(P0)) {
+	/* sti, pop ss, or mov ss recursively call InterpOne to make
+	   sure the next instruction is in the same block so it
+	   it cannot be interrupted. This only applies strictly to the
+	   next instruction, the inhibition doesn't last past two "sti"s
+	   for example. We must signal to NewIMeta that we want one more
+	   item.
+	*/
+	if (!NewIMeta(P0, (basemode & MINHI) ? 1 : 0)) {
 		if (debug_level('e')>2)
 			e_printf("============ Tab full:cannot close sequence\n");
 
@@ -878,8 +885,10 @@ intop3b:		{ int op = ArOpsFR[D_MO(opc)];
 			    AddrGen(A_SR_PROT, _mode, Ofs_SS, P0);
 			    Gen(O_POP3, _mode);
 			}
-			InstrMeta[CurrIMeta].flags |= F_INHI;
 			PC++;
+			if (!(_mode & MINHI))
+			    PC = InterpOne(PC, Interp_LONG_CS, ocs,
+					   basemode|MINHI);
 			break;
 /*1f*/	case POPds:	_mode |= SEGREG;
 			if (REALADDR()) {
@@ -1324,8 +1333,9 @@ intop3b:		{ int op = ArOpsFR[D_MO(opc)];
 			else {
 			    AddrGen(A_SR_PROT, _mode, REG1, P0);
 			}
-			if (REG1 == Ofs_SS)
-			    InstrMeta[CurrIMeta].flags |= F_INHI;
+			if (REG1 == Ofs_SS && !(_mode & MINHI))
+			    PC = InterpOne(PC, Interp_LONG_CS, ocs,
+					   basemode|MINHI);
 			break;
 
 /*9b*/	case oWAIT:
@@ -2088,8 +2098,16 @@ intop3b:		{ int op = ArOpsFR[D_MO(opc)];
 			Gen(O_SIM, _mode, opc, 0, PC);
 			/* real mode inhibits after STI as well but
 			   we've always relied on trapping behaviour with vm86 */
-			if (!V86MODE())
-				InstrMeta[CurrIMeta].flags |= F_INHI;
+			if (!V86MODE() && !(_mode & MINHI)) {
+				PC = InterpOne(PC, Interp_LONG_CS, ocs,
+					       basemode|MINHI|MSSTP);
+				/* check signals immediately after the
+				   instruction following STI, if it's not
+				   already a jump */
+				IMeta *GL = &InstrMeta[CurrIMeta];
+				if (GL->gen[GL->ngen-1].op < JMP_TAILCODE)
+					Gen(JMP_LINK, _mode|CKSIGN, PC, InstrMeta[0].npc);
+			}
 			break;
 /*fc*/	case CLD:	PC++;
 			Gen(O_SETFL, _mode, CLD);

src/base/emu-i386/simx86/trees.c

@@ -1622,15 +1622,17 @@ int e_invalidate_page_full(unsigned data)
 
 /////////////////////////////////////////////////////////////////////////////
 
-int NewIMeta(int npc)
+int NewIMeta(int npc, int override)
 {
 	int ret = 0;
 #if PROFILE >= 2
 	hitimer_t t0 = 0;
 
 	if (debug_level('e')) t0 = GETTSC();
 #endif
-	if (CurrIMeta < MAXINODES-1) {
+	/* normally we have max MAXINODES-1 instructions in the buffer, but
+	   we allow one more for the instruction following STI/POPss/MOVss */
+	if (CurrIMeta < MAXINODES-2+override) {
 		// add new opcode metadata
 		IMeta *I,*I0;
 

src/include/cpu-emu.h

@@ -50,8 +50,6 @@ extern void e_priv_iopl(int);
 #define CeS_SIGPEND	0x01	/* signal pending mask */
 #define CeS_SIGACT	0x02	/* signal active mask */
 #define CeS_RPIC	0x04	/* pic asks for interruption */
-#define CeS_STI		0x08	/* STI shadow active */
-#define CeS_INHI	0x800	/* inhibit interrupts(pop ss; pop sp et sim.) */
 #define CeS_TRAP	0x1000	/* INT01 Sstep active */
 #define CeS_DRTRAP	0x2000	/* Debug Registers active */
 #define CeS_INSTREMU_RM	0x4000