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[SPIRV] Support for the extension SPV_ALTERA_blocking_pipes (llvm#138675)
--Added support for the extension SPV_ALTERA_blocking_pipes --Added test files for the extension SPV_ALTERA_blocking_pipes
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‎llvm/docs/SPIRVUsage.rst‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -241,6 +241,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
241241
- Adds predicated load and store instructions that conditionally read from or write to memory based on a boolean predicate.
242242
* - ``SPV_KHR_maximal_reconvergence``
243243
- Adds execution mode and capability to enable maximal reconvergence.
244+
* - ``SPV_ALTERA_blocking_pipes``
245+
- Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
244246

245247
SPIR-V representation in LLVM IR
246248
================================

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2390,6 +2390,15 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
23902390
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
23912391
}
23922392

2393+
static bool generateBlockingPipesInst(const SPIRV::IncomingCall *Call,
2394+
MachineIRBuilder &MIRBuilder,
2395+
SPIRVGlobalRegistry *GR) {
2396+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2397+
unsigned Opcode =
2398+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2399+
return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
2400+
}
2401+
23932402
static bool
23942403
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
23952404
MachineIRBuilder &MIRBuilder,
@@ -3050,6 +3059,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
30503059
return generatePipeInst(Call.get(), MIRBuilder, GR);
30513060
case SPIRV::PredicatedLoadStore:
30523061
return generatePredicatedLoadStoreInst(Call.get(), MIRBuilder, GR);
3062+
case SPIRV::BlockingPipes:
3063+
return generateBlockingPipesInst(Call.get(), MIRBuilder, GR);
30533064
}
30543065
return false;
30553066
}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ def TernaryBitwiseINTEL : BuiltinGroup;
7171
def Block2DLoadStore : BuiltinGroup;
7272
def Pipe : BuiltinGroup;
7373
def PredicatedLoadStore : BuiltinGroup;
74+
def BlockingPipes : BuiltinGroup;
7475

7576
//===----------------------------------------------------------------------===//
7677
// Class defining a demangled builtin record. The information in the record
@@ -1174,6 +1175,10 @@ defm : DemangledNativeBuiltin<"clock_read_sub_group", OpenCL_std, KernelClock, 0
11741175
defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11751176
defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11761177
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
1178+
1179+
//SPV_ALTERA_blocking_pipes
1180+
defm : DemangledNativeBuiltin<"__spirv_WritePipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpWritePipeBlockingALTERA>;
1181+
defm : DemangledNativeBuiltin<"__spirv_ReadPipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpReadPipeBlockingALTERA>;
11771182
defm : DemangledNativeBuiltin<"__spirv_ReadClockKHR", OpenCL_std, KernelClock, 1, 1, OpReadClockKHR>;
11781183

11791184
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,7 +159,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
159159
{"SPV_KHR_maximal_reconvergence",
160160
SPIRV::Extension::Extension::SPV_KHR_maximal_reconvergence},
161161
{"SPV_INTEL_kernel_attributes",
162-
SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes}};
162+
SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes},
163+
{"SPV_ALTERA_blocking_pipes",
164+
SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes}};
163165

164166
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
165167
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -993,3 +993,9 @@ def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr,
993993
"$res = OpPredicatedLoadINTEL $resType $ptr $predicate $default_value">;
994994
def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
995995
"OpPredicatedStoreINTEL $ptr $object $predicate">;
996+
997+
//SPV_ALTERA_blocking_pipes
998+
def OpReadPipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
999+
"OpReadPipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
1000+
def OpWritePipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
1001+
"OpWritePipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1885,6 +1885,13 @@ void addInstrRequirements(const MachineInstr &MI,
18851885
Reqs.addCapability(
18861886
SPIRV::Capability::CooperativeMatrixCheckedInstructionsINTEL);
18871887
break;
1888+
case SPIRV::OpReadPipeBlockingALTERA:
1889+
case SPIRV::OpWritePipeBlockingALTERA:
1890+
if (ST.canUseExtension(SPIRV::Extension::SPV_ALTERA_blocking_pipes)) {
1891+
Reqs.addExtension(SPIRV::Extension::SPV_ALTERA_blocking_pipes);
1892+
Reqs.addCapability(SPIRV::Capability::BlockingPipesALTERA);
1893+
}
1894+
break;
18881895
case SPIRV::OpCooperativeMatrixGetElementCoordINTEL:
18891896
if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_joint_matrix))
18901897
report_fatal_error("OpCooperativeMatrixGetElementCoordINTEL requires the "

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -309,7 +309,7 @@ defm SPV_KHR_shader_clock : ExtensionOperand<54, [EnvVulkan, EnvOpenCL]>;
309309
defm SPV_INTEL_unstructured_loop_controls : ExtensionOperand<55, [EnvOpenCL]>;
310310
defm SPV_EXT_demote_to_helper_invocation : ExtensionOperand<56, [EnvVulkan]>;
311311
defm SPV_INTEL_fpga_reg : ExtensionOperand<57, [EnvOpenCL]>;
312-
defm SPV_INTEL_blocking_pipes : ExtensionOperand<58, [EnvOpenCL]>;
312+
defm SPV_ALTERA_blocking_pipes : ExtensionOperand<58, [EnvOpenCL]>;
313313
defm SPV_GOOGLE_user_type : ExtensionOperand<59, [EnvVulkan]>;
314314
defm SPV_KHR_physical_storage_buffer : ExtensionOperand<60, [EnvVulkan]>;
315315
defm SPV_INTEL_kernel_attributes : ExtensionOperand<61, [EnvOpenCL]>;
@@ -611,6 +611,7 @@ defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tenso
611611
defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
612612
defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
613613
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
614+
defm BlockingPipesALTERA : CapabilityOperand<5945, 0, 0, [SPV_ALTERA_blocking_pipes], []>;
614615

615616
//===----------------------------------------------------------------------===//
616617
// Multiclass used to define SourceLanguage enum values and at the same time

‎llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_blocking_pipes/PipeBlocking.ll‎

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_ALTERA_blocking_pipes %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
2+
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_blocking_pipes %s -o - -filetype=obj | spirv-val %}
3+
4+
%opencl.pipe_ro_t = type opaque
5+
%opencl.pipe_wo_t = type opaque
6+
7+
; CHECK-SPIRV: OpCapability BlockingPipesALTERA
8+
; CHECK-SPIRV: OpExtension "SPV_ALTERA_blocking_pipes"
9+
; CHECK-SPIRV: %[[PipeRTy:[0-9]+]] = OpTypePipe ReadOnly
10+
; CHECK-SPIRV: %[[PipeWTy:[0-9]+]] = OpTypePipe WriteOnly
11+
; CHECK-SPIRV: %[[PipeR1:[0-9]+]] = OpLoad %[[PipeRTy]] %[[#]] Aligned 8
12+
; CHECK-SPIRV: OpReadPipeBlockingALTERA %[[PipeR1]] %[[#]] %[[#]] %[[#]]
13+
; CHECK-SPIRV: %[[PipeR2:[0-9]+]] = OpLoad %[[PipeRTy]] %[[#]] Aligned 8
14+
; CHECK-SPIRV: OpReadPipeBlockingALTERA %[[PipeR2]] %[[#]] %[[#]] %[[#]]
15+
; CHECK-SPIRV: %[[PipeW1:[0-9]+]] = OpLoad %[[PipeWTy]] %[[#]] Aligned 8
16+
; CHECK-SPIRV: OpWritePipeBlockingALTERA %[[PipeW1]] %[[#]] %[[#]] %[[#]]
17+
; CHECK-SPIRV: %[[PipeW2:[0-9]+]] = OpLoad %[[PipeWTy]] %[[#]] Aligned 8
18+
; CHECK-SPIRV: OpWritePipeBlockingALTERA %[[PipeW2]] %[[#]] %[[#]] %[[#]]
19+
20+
define spir_func void @foo(target("spirv.Pipe", 0) %p, ptr addrspace(1) %ptr) {
21+
entry:
22+
%p.addr = alloca target("spirv.Pipe", 0), align 8
23+
%ptr.addr = alloca ptr addrspace(1), align 8
24+
store target("spirv.Pipe", 0) %p, target("spirv.Pipe", 0)* %p.addr, align 8
25+
store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
26+
%0 = load target("spirv.Pipe", 0), target("spirv.Pipe", 0)* %p.addr, align 8
27+
%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
28+
%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
29+
call spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePiii(target("spirv.Pipe", 0) %0, ptr addrspace(4) %2, i32 4, i32 4)
30+
ret void
31+
}
32+
33+
declare dso_local spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePiii(target("spirv.Pipe", 0), ptr addrspace(4), i32, i32)
34+
35+
define spir_func void @bar(target("spirv.Pipe", 0) %p, ptr addrspace(1) %ptr) {
36+
entry:
37+
%p.addr = alloca target("spirv.Pipe", 0), align 8
38+
%ptr.addr = alloca ptr addrspace(1), align 8
39+
store target("spirv.Pipe", 0) %p, target("spirv.Pipe", 0)* %p.addr, align 8
40+
store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
41+
%0 = load target("spirv.Pipe", 0), target("spirv.Pipe", 0)* %p.addr, align 8
42+
%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
43+
%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
44+
call spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePvii(target("spirv.Pipe", 0) %0, ptr addrspace(4) %2, i32 4, i32 4)
45+
ret void
46+
}
47+
48+
declare dso_local spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePvii(target("spirv.Pipe", 0), ptr addrspace(4), i32, i32)
49+
50+
define spir_func void @boo(target("spirv.Pipe", 1) %p, ptr addrspace(1) %ptr) {
51+
entry:
52+
%p.addr = alloca target("spirv.Pipe", 1), align 8
53+
%ptr.addr = alloca ptr addrspace(1), align 8
54+
store target("spirv.Pipe", 1) %p, target("spirv.Pipe", 1)* %p.addr, align 8
55+
store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
56+
%0 = load target("spirv.Pipe", 1), target("spirv.Pipe", 1)* %p.addr, align 8
57+
%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
58+
%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
59+
call spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePiii(target("spirv.Pipe", 1) %0, ptr addrspace(4) %2, i32 4, i32 4)
60+
ret void
61+
}
62+
63+
declare dso_local spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePiii(target("spirv.Pipe", 1), ptr addrspace(4), i32, i32)
64+
65+
define spir_func void @baz(target("spirv.Pipe", 1) %p, ptr addrspace(1) %ptr) {
66+
entry:
67+
%p.addr = alloca target("spirv.Pipe", 1), align 8
68+
%ptr.addr = alloca ptr addrspace(1), align 8
69+
store target("spirv.Pipe", 1) %p, target("spirv.Pipe", 1)* %p.addr, align 8
70+
store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
71+
%0 = load target("spirv.Pipe", 1), target("spirv.Pipe", 1)* %p.addr, align 8
72+
%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
73+
%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
74+
call spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePvii(target("spirv.Pipe", 1) %0, ptr addrspace(4) %2, i32 4, i32 4)
75+
ret void
76+
}
77+
78+
declare dso_local spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePvii(target("spirv.Pipe", 1), ptr addrspace(4), i32, i32)
79+
80+
; CHECK-LLVM: declare spir_func void @__read_pipe_2_bl(ptr addrspace(1), ptr addrspace(4), i32, i32)
81+
; CHECK-LLVM: declare spir_func void @__write_pipe_2_bl(ptr addrspace(1), ptr addrspace(4), i32, i32)
82+
83+
define linkonce_odr dso_local spir_func void @WritePipeBLockingi9Pointer(ptr addrspace(4) align 2 dereferenceable(2) %_Data) {
84+
entry:
85+
%_Data.addr = alloca ptr addrspace(4), align 8
86+
%_WPipe = alloca target("spirv.Pipe", 1), align 8
87+
%_Data.addr.ascast = addrspacecast ptr %_Data.addr to ptr addrspace(4)
88+
%_WPipe.ascast = addrspacecast target("spirv.Pipe", 1)* %_WPipe to target("spirv.Pipe", 1) addrspace(4)*
89+
store ptr addrspace(4) %_Data, ptr addrspace(4) %_Data.addr.ascast, align 8
90+
%0 = bitcast target("spirv.Pipe", 1)* %_WPipe to ptr
91+
%1 = load target("spirv.Pipe", 1), target("spirv.Pipe", 1) addrspace(4)* %_WPipe.ascast, align 8
92+
%2 = load ptr addrspace(4), ptr addrspace(4) %_Data.addr.ascast, align 8
93+
call spir_func void @_Z30__spirv_WritePipeBlockingINTELIDU9_Ev8ocl_pipePKT_ii(target("spirv.Pipe", 1) %1, ptr addrspace(4) %2, i32 2, i32 2)
94+
ret void
95+
}
96+
97+
declare dso_local spir_func void @_Z30__spirv_WritePipeBlockingINTELIDU9_Ev8ocl_pipePKT_ii(target("spirv.Pipe", 1), ptr addrspace(4), i32, i32)
98+

‎mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,7 @@ def SPV_INTEL_fpga_buffer_location : I32EnumAttrCase<"SPV_INTEL_fp
395395
def SPV_INTEL_arbitrary_precision_fixed_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 4019>;
396396
def SPV_INTEL_usm_storage_classes : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 4020>;
397397
def SPV_INTEL_io_pipes : I32EnumAttrCase<"SPV_INTEL_io_pipes", 4021>;
398-
def SPV_INTEL_blocking_pipes : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 4022>;
398+
def SPV_ALTERA_blocking_pipes : I32EnumAttrCase<"SPV_ALTERA_blocking_pipes", 4022>;
399399
def SPV_INTEL_fpga_reg : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 4023>;
400400
def SPV_INTEL_long_constant_composite : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 4024>;
401401
def SPV_INTEL_optnone : I32EnumAttrCase<"SPV_INTEL_optnone", 4025>;
@@ -465,7 +465,7 @@ def SPIRV_ExtensionAttr :
465465
SPV_INTEL_kernel_attributes, SPV_INTEL_fpga_memory_accesses,
466466
SPV_INTEL_fpga_cluster_attributes, SPV_INTEL_loop_fuse,
467467
SPV_INTEL_fpga_buffer_location, SPV_INTEL_arbitrary_precision_fixed_point,
468-
SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_INTEL_blocking_pipes,
468+
SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_ALTERA_blocking_pipes,
469469
SPV_INTEL_fpga_reg, SPV_INTEL_long_constant_composite, SPV_INTEL_optnone,
470470
SPV_INTEL_debug_module, SPV_INTEL_fp_fast_math_mode,
471471
SPV_INTEL_memory_access_aliasing, SPV_INTEL_split_barrier,
@@ -807,9 +807,9 @@ def SPIRV_C_IOPipesINTEL : I32EnumAttrCase<"IOPip
807807
Extension<[SPV_INTEL_io_pipes]>
808808
];
809809
}
810-
def SPIRV_C_BlockingPipesINTEL : I32EnumAttrCase<"BlockingPipesINTEL", 5945> {
810+
def SPIRV_C_BlockingPipesALTERA : I32EnumAttrCase<"BlockingPipesALTERA", 5945> {
811811
list<Availability> availability = [
812-
Extension<[SPV_INTEL_blocking_pipes]>
812+
Extension<[SPV_ALTERA_blocking_pipes]>
813813
];
814814
}
815815
def SPIRV_C_FPGARegINTEL : I32EnumAttrCase<"FPGARegINTEL", 5948> {
@@ -1519,7 +1519,7 @@ def SPIRV_CapabilityAttr :
15191519
SPIRV_C_FPGAMemoryAccessesINTEL, SPIRV_C_FPGAClusterAttributesINTEL,
15201520
SPIRV_C_LoopFuseINTEL, SPIRV_C_MemoryAccessAliasingINTEL,
15211521
SPIRV_C_FPGABufferLocationINTEL, SPIRV_C_ArbitraryPrecisionFixedPointINTEL,
1522-
SPIRV_C_USMStorageClassesINTEL, SPIRV_C_IOPipesINTEL, SPIRV_C_BlockingPipesINTEL,
1522+
SPIRV_C_USMStorageClassesINTEL, SPIRV_C_IOPipesINTEL, SPIRV_C_BlockingPipesALTERA,
15231523
SPIRV_C_FPGARegINTEL, SPIRV_C_DotProductInputAll,
15241524
SPIRV_C_DotProductInput4x8BitPacked, SPIRV_C_DotProduct, SPIRV_C_RayCullMaskKHR,
15251525
SPIRV_C_CooperativeMatrixKHR, SPIRV_C_ReplicatedCompositesEXT,

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