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Implemented configuration of row and column cycles required for addresing read/write/erase operation
1 parent d7438d0 commit 05d54c5

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11 files changed

+182
-37
lines changed

11 files changed

+182
-37
lines changed

‎firmware/chip_info.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ typedef struct
1818
uint8_t hi_z_setup_time;
1919
uint8_t clr_setup_time;
2020
uint8_t ar_setup_time;
21+
uint8_t row_cycles;
22+
uint8_t col_cycles;
2123
} chip_info_t;
2224

2325
#endif /* _CHIP_INFO_H_ */

‎firmware/fsmc_nand.c

Lines changed: 113 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -93,43 +93,138 @@ void nand_read_id(nand_id_t *nand_id)
9393
nand_id->fourth_id = ADDR_4th_CYCLE (data);
9494
}
9595

96-
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size)
96+
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
97+
uint8_t row_cycles, uint8_t col_cycles)
9798
{
9899
uint32_t i;
99100

100101
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
101102

102-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
103-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
104-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
105-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
106-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
103+
switch (col_cycles)
104+
{
105+
case 1:
106+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
107+
break;
108+
case 2:
109+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
110+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
111+
break;
112+
case 3:
113+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
114+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
115+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
116+
break;
117+
case 4:
118+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
119+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
120+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
121+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
122+
break;
123+
default:
124+
break;
125+
}
126+
127+
switch (row_cycles)
128+
{
129+
case 1:
130+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
131+
break;
132+
case 2:
133+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
134+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
135+
break;
136+
case 3:
137+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
138+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
139+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
140+
break;
141+
case 4:
142+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
143+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
144+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
145+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(page);
146+
break;
147+
default:
148+
break;
149+
}
107150

108151
for(i = 0; i < page_size; i++)
109152
*(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = buf[i];
110153

111154
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
112155
}
113156

114-
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size)
157+
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size,
158+
uint8_t row_cycles, uint8_t col_cycles)
115159
{
116-
nand_write_page_async(buf, page, page_size);
160+
nand_write_page_async(buf, page, page_size, row_cycles, col_cycles);
117161

118162
return nand_get_status();
119163
}
120164

121165
uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
122-
uint32_t data_size)
166+
uint32_t data_size, uint8_t row_cycles, uint8_t col_cycles)
123167
{
124168
uint32_t i;
125169

126170
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ0;
127-
128-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page_offset);
129-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page_offset);
130-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
131-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
132-
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
171+
172+
switch (col_cycles)
173+
{
174+
case 1:
175+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
176+
ADDR_1st_CYCLE(page_offset);
177+
break;
178+
case 2:
179+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
180+
ADDR_1st_CYCLE(page_offset);
181+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
182+
ADDR_2nd_CYCLE(page_offset);
183+
break;
184+
case 3:
185+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
186+
ADDR_1st_CYCLE(page_offset);
187+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
188+
ADDR_2nd_CYCLE(page_offset);
189+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
190+
ADDR_3rd_CYCLE(page_offset);
191+
break;
192+
case 4:
193+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
194+
ADDR_1st_CYCLE(page_offset);
195+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
196+
ADDR_2nd_CYCLE(page_offset);
197+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
198+
ADDR_3rd_CYCLE(page_offset);
199+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
200+
ADDR_4th_CYCLE(page_offset);
201+
default:
202+
break;
203+
}
204+
205+
switch (row_cycles)
206+
{
207+
case 1:
208+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
209+
break;
210+
case 2:
211+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
212+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
213+
break;
214+
case 3:
215+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
216+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
217+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
218+
break;
219+
case 4:
220+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
221+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
222+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
223+
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(page);
224+
break;
225+
default:
226+
break;
227+
}
133228

134229
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ1;
135230

@@ -139,9 +234,10 @@ uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
139234
return nand_get_status();
140235
}
141236

142-
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size)
237+
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size,
238+
uint8_t row_cycles, uint8_t col_cycles)
143239
{
144-
return nand_read_data(buf, page, 0, page_size);
240+
return nand_read_data(buf, page, 0, page_size, row_cycles, col_cycles);
145241
}
146242

147243
/**

‎firmware/fsmc_nand.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -70,11 +70,14 @@ typedef struct
7070

7171
void nand_init(chip_info_t *chip_info);
7272
void nand_read_id(nand_id_t *nand_id);
73-
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size);
74-
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size);
73+
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size,
74+
uint8_t row_cycles, uint8_t col_cycles);
75+
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
76+
uint8_t row_cycles, uint8_t col_cycles);
7577
uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
76-
uint32_t data_size);
77-
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size);
78+
uint32_t data_size, uint8_t row_cycles, uint8_t col_cycles);
79+
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size,
80+
uint8_t row_cycles, uint8_t col_cycles);
7881
uint32_t nand_write_spare_area(uint8_t *buf, nand_addr_t addr,
7982
uint32_t num_spare_area_to_write);
8083
uint32_t nand_read_spare_area(uint8_t *buf, nand_addr_t addr,

‎firmware/nand_programmer.c

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,8 @@ typedef struct __attribute__((__packed__))
115115
uint8_t hi_z_setup_time;
116116
uint8_t clr_setup_time;
117117
uint8_t ar_setup_time;
118+
uint8_t row_cycles;
119+
uint8_t col_cycles;
118120
} np_conf_cmd_t;
119121

120122
enum
@@ -312,7 +314,7 @@ static int np_read_bad_block_info_from_page(np_prog_t *prog, uint32_t block,
312314
uint32_t status, addr = block * prog->chip_info.block_size;
313315

314316
status = nand_read_data(prog->page.buf, page, 0, prog->chip_info.page_size
315-
+ 1);
317+
+ 1, prog->chip_info.row_cycles, prog->chip_info.col_cycles);
316318
switch (status)
317319
{
318320
case NAND_READY:
@@ -650,7 +652,8 @@ static int np_nand_write(np_prog_t *prog)
650652
DEBUG_PRINT("NAND write at 0x%lx %lu bytes\r\n", prog->addr,
651653
prog->page_size);
652654

653-
nand_write_page_async(prog->page.buf, prog->page.page, prog->page_size);
655+
nand_write_page_async(prog->page.buf, prog->page.page, prog->page_size,
656+
prog->chip_info.row_cycles, prog->chip_info.col_cycles);
654657

655658
prog->nand_wr_in_progress = 1;
656659

@@ -794,11 +797,12 @@ static int np_cmd_nand_write(np_prog_t *prog)
794797
}
795798

796799
static int np_nand_read(uint32_t addr, np_page_t *page, uint32_t page_size,
797-
uint32_t block_size)
800+
uint32_t block_size, np_prog_t *prog)
798801
{
799802
uint32_t status;
800803

801-
status = nand_read_page(page->buf, page->page, page_size);
804+
status = nand_read_page(page->buf, page->page, page_size,
805+
prog->chip_info.row_cycles, prog->chip_info.col_cycles);
802806
switch (status)
803807
{
804808
case NAND_READY:
@@ -919,7 +923,7 @@ static int _np_cmd_nand_read(np_prog_t *prog)
919923
continue;
920924
}
921925

922-
if (np_nand_read(addr, &page, page_size, block_size))
926+
if (np_nand_read(addr, &page, page_size, block_size, prog))
923927
return NP_ERR_NAND_RD;
924928

925929
while (page.offset < page_size && len)
@@ -991,6 +995,8 @@ static int np_cmd_nand_conf(np_prog_t *prog)
991995
prog->chip_info.hi_z_setup_time = conf_cmd->hi_z_setup_time;
992996
prog->chip_info.clr_setup_time = conf_cmd->clr_setup_time;
993997
prog->chip_info.ar_setup_time = conf_cmd->ar_setup_time;
998+
prog->chip_info.row_cycles = conf_cmd->row_cycles;
999+
prog->chip_info.col_cycles = conf_cmd->col_cycles;
9941000
prog->chip_is_conf = 1;
9951001

9961002
DEBUG_PRINT("Page size: %lu\r\n", prog->chip_info.page_size);
@@ -1003,6 +1009,8 @@ static int np_cmd_nand_conf(np_prog_t *prog)
10031009
DEBUG_PRINT("HiZ setup time: %d\r\n", prog->chip_info.hi_z_setup_time);
10041010
DEBUG_PRINT("CLR setip time: %d\r\n", prog->chip_info.clr_setup_time);
10051011
DEBUG_PRINT("AR setip time: %d\r\n", prog->chip_info.ar_setup_time);
1012+
DEBUG_PRINT("Row cycles: %d\r\n", prog->chip_info.row_cycles);
1013+
DEBUG_PRINT("Col. cycles: %d\r\n", prog->chip_info.col_cycles);
10061014

10071015
nand_init(&prog->chip_info);
10081016

‎qt/chip_db.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@ enum
4040
CHIP_PARAM_T_WC,
4141
CHIP_PARAM_T_RC,
4242
CHIP_PARAM_T_REA,
43+
CHIP_PARAM_ROW_CYCLES,
44+
CHIP_PARAM_COL_CYCLES,
4345
CHIP_PARAM_NUM,
4446
};
4547

‎qt/chip_db_dialog.cpp

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
#include "chip_db_dialog.h"
22
#include "ui_chip_db_dialog.h"
33

4-
#define HEADER_LONG_WIDTH 100
4+
#define HEADER_LONG_WIDTH 120
5+
#define HEADER_MED_WIDTH 100
56
#define HEADER_SHORT_WIDTH 50
67

78
ChipDbDialog::ChipDbDialog(ChipDb *chipDb, QWidget *parent) : QDialog(parent),
@@ -12,15 +13,19 @@ ChipDbDialog::ChipDbDialog(ChipDb *chipDb, QWidget *parent) : QDialog(parent),
1213
ui->chipDbTableView->setModel(&chipDbProxyModel);
1314
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_NAME, HEADER_LONG_WIDTH);
1415
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_PAGE_SIZE,
15-
HEADER_LONG_WIDTH);
16+
HEADER_MED_WIDTH);
1617
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_BLOCK_SIZE,
17-
HEADER_LONG_WIDTH);
18+
HEADER_MED_WIDTH);
1819
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_TOTAL_SIZE,
19-
HEADER_LONG_WIDTH);
20+
HEADER_MED_WIDTH);
2021
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_SPARE_SIZE,
21-
HEADER_LONG_WIDTH);
22-
for (int i = CHIP_PARAM_SPARE_SIZE + 1; i < CHIP_PARAM_NUM; i++)
22+
HEADER_MED_WIDTH);
23+
for (int i = CHIP_PARAM_SPARE_SIZE + 1; i < CHIP_PARAM_T_REA; i++)
2324
ui->chipDbTableView->setColumnWidth(i, HEADER_SHORT_WIDTH);
25+
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_ROW_CYCLES,
26+
HEADER_MED_WIDTH);
27+
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_COL_CYCLES,
28+
HEADER_MED_WIDTH);
2429

2530
connect(ui->addChipDbButton, SIGNAL(clicked()), this,
2631
SLOT(slotAddChipDbButtonClicked()));

‎qt/chip_db_dialog.ui

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
<rect>
1010
<x>0</x>
1111
<y>0</y>
12-
<width>1226</width>
12+
<width>1470</width>
1313
<height>600</height>
1414
</rect>
1515
</property>
@@ -21,7 +21,7 @@
2121
</property>
2222
<property name="maximumSize">
2323
<size>
24-
<width>1226</width>
24+
<width>1470</width>
2525
<height>16777215</height>
2626
</size>
2727
</property>

‎qt/chip_db_table_model.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
#include "chip_db_table_model.h"
22

3+
#define CHIP_DB_TABLE_MODEL_MAX_CYCLES 4
4+
35
ChipDbTableModel::ChipDbTableModel(ChipDb *chipDb, QObject *parent) :
46
QAbstractTableModel(parent)
57
{
@@ -61,6 +63,10 @@ QVariant ChipDbTableModel::data(const QModelIndex &index, int role) const
6163
return (*chipDb)[index.row()]->params[CHIP_PARAM_T_RC];
6264
case CHIP_PARAM_T_REA:
6365
return (*chipDb)[index.row()]->params[CHIP_PARAM_T_REA];
66+
case CHIP_PARAM_ROW_CYCLES:
67+
return (*chipDb)[index.row()]->params[CHIP_PARAM_ROW_CYCLES];
68+
case CHIP_PARAM_COL_CYCLES:
69+
return (*chipDb)[index.row()]->params[CHIP_PARAM_COL_CYCLES];
6470
}
6571

6672
return QVariant();
@@ -92,6 +98,8 @@ QVariant ChipDbTableModel::headerData(int section, Qt::Orientation orientation,
9298
case CHIP_PARAM_T_WC: return tr("tWC");
9399
case CHIP_PARAM_T_RC: return tr("tRC");
94100
case CHIP_PARAM_T_REA: return tr("tREA");
101+
case CHIP_PARAM_ROW_CYCLES: return tr("Row cycles");
102+
case CHIP_PARAM_COL_CYCLES: return tr("Col. cycles");
95103
}
96104
}
97105

@@ -137,6 +145,12 @@ QVariant ChipDbTableModel::headerData(int section, Qt::Orientation orientation,
137145
return tr("Read cylce time");
138146
case CHIP_PARAM_T_REA:
139147
return tr("Read enable access time");
148+
case CHIP_PARAM_ROW_CYCLES:
149+
return tr("Number of cycles required for addresing row (page) "
150+
"during read/write/erase operation");
151+
case CHIP_PARAM_COL_CYCLES:
152+
return tr("Number of cycles required for addresing column "
153+
"(page offset) during read/write operation");
140154
}
141155
}
142156

@@ -185,6 +199,15 @@ bool ChipDbTableModel::setData(const QModelIndex &index, const QVariant &value,
185199
return false;
186200
(*chipDb)[index.row()]->params[index.column()] = paramVal;
187201
return true;
202+
case CHIP_PARAM_ROW_CYCLES:
203+
case CHIP_PARAM_COL_CYCLES:
204+
paramVal = value.toUInt(&convOk);
205+
if (!convOk)
206+
return false;
207+
if (paramVal > CHIP_DB_TABLE_MODEL_MAX_CYCLES)
208+
return false;
209+
(*chipDb)[index.row()]->params[index.column()] = paramVal;
210+
return true;
188211
}
189212

190213
return false;

‎qt/cmd.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,8 @@ typedef struct __attribute__((__packed__))
7676
uint8_t hiZSetupTime;
7777
uint8_t clrSetupTime;
7878
uint8_t arSetupTime;
79+
uint8_t rowCycles;
80+
uint8_t colCycles;
7981
} ConfCmd;
8082

8183
enum

‎qt/nando_chip_db.csv

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
# name, pageSize, blockSize, totalSize, spareSize, tCS, tCLS, tALS, tCLR, tAR, tWP, tRP, tDS, tCH, tCLH, tALH, tWC, tRC, tREA
2-
K9F2G08U0C, 2048, 131072, 268435456, 64, 20, 12, 12, 10, 10, 12, 12, 12, 5, 5, 5, 25, 25, 20
3-
K9F1G08U0E, 2048, 131072, 134217728, 64, 20, 12, 12, 10, 10, 12, 12, 12, 5, 5, 5, 25, 25, 20
1+
# name, pageSize, blockSize, totalSize, spareSize, tCS, tCLS, tALS, tCLR, tAR, tWP, tRP, tDS, tCH, tCLH, tALH, tWC, tRC, tREA, Row cycles, Col. cycles
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K9F2G08U0C, 2048, 131072, 268435456, 64, 20, 12, 12, 10, 10, 12, 12, 12, 5, 5, 5, 25, 25, 20, 3, 2
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K9F1G08U0E, 2048, 131072, 134217728, 64, 20, 12, 12, 10, 10, 12, 12, 12, 5, 5, 5, 25, 25, 20, 3, 2

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