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Implemented configuration of NAND commands
1 parent d21878f commit 2234d9c

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10 files changed

+222
-79
lines changed

10 files changed

+222
-79
lines changed

firmware/chip_info.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,15 @@ typedef struct
2020
uint8_t ar_setup_time;
2121
uint8_t row_cycles;
2222
uint8_t col_cycles;
23+
uint8_t read1_cmd;
24+
uint8_t read2_cmd;
25+
uint8_t read_id_cmd;
26+
uint8_t reset_cmd;
27+
uint8_t write1_cmd;
28+
uint8_t write2_cmd;
29+
uint8_t erase1_cmd;
30+
uint8_t erase2_cmd;
31+
uint8_t status_cmd;
2332
} chip_info_t;
2433

2534
#endif /* _CHIP_INFO_H_ */

firmware/fsmc_nand.c

Lines changed: 55 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,23 @@
1212
#define ROW_ADDRESS (addr.page + (addr.block + (addr.zone * NAND_ZONE_SIZE)) * \
1313
NAND_BLOCK_SIZE)
1414

15+
typedef struct
16+
{
17+
uint8_t row_cycles;
18+
uint8_t col_cycles;
19+
uint8_t read1_cmd;
20+
uint8_t read2_cmd;
21+
uint8_t read_id_cmd;
22+
uint8_t reset_cmd;
23+
uint8_t write1_cmd;
24+
uint8_t write2_cmd;
25+
uint8_t erase1_cmd;
26+
uint8_t erase2_cmd;
27+
uint8_t status_cmd;
28+
} fsmc_cmd_t;
29+
30+
static fsmc_cmd_t fsmc_cmd;
31+
1532
static void nand_gpio_init(void)
1633
{
1734
GPIO_InitTypeDef gpio_init;
@@ -70,18 +87,34 @@ static void nand_fsmc_init(chip_info_t *chip_info)
7087
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
7188
}
7289

90+
static void nand_cmd_init(chip_info_t *chip_info)
91+
{
92+
fsmc_cmd.row_cycles = chip_info->row_cycles;
93+
fsmc_cmd.col_cycles = chip_info->col_cycles;
94+
fsmc_cmd.read1_cmd = chip_info->read1_cmd;
95+
fsmc_cmd.read2_cmd = chip_info->read2_cmd;
96+
fsmc_cmd.read_id_cmd = chip_info->read_id_cmd;
97+
fsmc_cmd.reset_cmd = chip_info->reset_cmd;
98+
fsmc_cmd.write1_cmd = chip_info->write1_cmd;
99+
fsmc_cmd.write2_cmd = chip_info->write2_cmd;
100+
fsmc_cmd.erase1_cmd = chip_info->erase1_cmd;
101+
fsmc_cmd.erase2_cmd = chip_info->erase2_cmd;
102+
fsmc_cmd.status_cmd = chip_info->status_cmd;
103+
}
104+
73105
void nand_init(chip_info_t *chip_info)
74106
{
75107
nand_gpio_init();
76108
nand_fsmc_init(chip_info);
109+
nand_cmd_init(chip_info);
77110
}
78111

79112
void nand_read_id(nand_id_t *nand_id)
80113
{
81114
uint32_t data = 0;
82115

83116
/* Send Command to the command area */
84-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
117+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read_id_cmd;
85118
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
86119

87120
/* Sequence to read ID from NAND flash */
@@ -93,14 +126,13 @@ void nand_read_id(nand_id_t *nand_id)
93126
nand_id->fourth_id = ADDR_4th_CYCLE (data);
94127
}
95128

96-
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
97-
uint8_t row_cycles, uint8_t col_cycles)
129+
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size)
98130
{
99131
uint32_t i;
100132

101-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
133+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.write1_cmd;
102134

103-
switch (col_cycles)
135+
switch (fsmc_cmd.col_cycles)
104136
{
105137
case 1:
106138
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
@@ -124,7 +156,7 @@ void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
124156
break;
125157
}
126158

127-
switch (row_cycles)
159+
switch (fsmc_cmd.row_cycles)
128160
{
129161
case 1:
130162
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
@@ -151,25 +183,25 @@ void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
151183
for(i = 0; i < page_size; i++)
152184
*(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = buf[i];
153185

154-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
186+
if (fsmc_cmd.write2_cmd != 0xFF)
187+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.write2_cmd;
155188
}
156189

157-
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size,
158-
uint8_t row_cycles, uint8_t col_cycles)
190+
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size)
159191
{
160-
nand_write_page_async(buf, page, page_size, row_cycles, col_cycles);
192+
nand_write_page_async(buf, page, page_size);
161193

162194
return nand_get_status();
163195
}
164196

165197
uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
166-
uint32_t data_size, uint8_t row_cycles, uint8_t col_cycles)
198+
uint32_t data_size)
167199
{
168200
uint32_t i;
169201

170-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ0;
202+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read1_cmd;
171203

172-
switch (col_cycles)
204+
switch (fsmc_cmd.col_cycles)
173205
{
174206
case 1:
175207
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
@@ -202,7 +234,7 @@ uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
202234
break;
203235
}
204236

205-
switch (row_cycles)
237+
switch (fsmc_cmd.row_cycles)
206238
{
207239
case 1:
208240
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
@@ -226,18 +258,18 @@ uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
226258
break;
227259
}
228260

229-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ1;
261+
if (fsmc_cmd.read2_cmd != 0xFF)
262+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read2_cmd;
230263

231264
for (i = 0; i < data_size; i++)
232265
buf[i]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
233266

234267
return nand_get_status();
235268
}
236269

237-
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size,
238-
uint8_t row_cycles, uint8_t col_cycles)
270+
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size)
239271
{
240-
return nand_read_data(buf, page, 0, page_size, row_cycles, col_cycles);
272+
return nand_read_data(buf, page, 0, page_size);
241273
}
242274

243275
/**
@@ -361,13 +393,13 @@ uint32_t nand_read_spare_area(uint8_t *buf, nand_addr_t addr,
361393

362394
uint32_t nand_erase_block(uint32_t page)
363395
{
364-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
396+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.erase1_cmd;
365397

366398
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
367399
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(page);
368400
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(page);
369401

370-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
402+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.erase2_cmd;
371403

372404
return nand_get_status();
373405
}
@@ -377,9 +409,9 @@ uint32_t nand_erase_block(uint32_t page)
377409
* @param None
378410
* @retval NAND_READY
379411
*/
380-
uint32_t nand_reset(void)
412+
uint32_t nand_reset()
381413
{
382-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
414+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.reset_cmd;
383415

384416
return (NAND_READY);
385417
}
@@ -425,7 +457,7 @@ uint32_t nand_read_status(void)
425457
uint32_t data = 0x00, status = NAND_BUSY;
426458

427459
/* Read status operation */
428-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
460+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.status_cmd;
429461
data = *(__IO uint8_t *)(Bank_NAND_ADDR);
430462

431463
if ((data & NAND_ERROR) == NAND_ERROR)

firmware/fsmc_nand.h

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -70,14 +70,11 @@ typedef struct
7070

7171
void nand_init(chip_info_t *chip_info);
7272
void nand_read_id(nand_id_t *nand_id);
73-
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size,
74-
uint8_t row_cycles, uint8_t col_cycles);
75-
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
76-
uint8_t row_cycles, uint8_t col_cycles);
73+
uint32_t nand_write_page(uint8_t *buf, uint32_t page, uint32_t page_size);
74+
void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size);
7775
uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
78-
uint32_t data_size, uint8_t row_cycles, uint8_t col_cycles);
79-
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size,
80-
uint8_t row_cycles, uint8_t col_cycles);
76+
uint32_t data_size);
77+
uint32_t nand_read_page(uint8_t *buf, uint32_t page, uint32_t page_size);
8178
uint32_t nand_write_spare_area(uint8_t *buf, nand_addr_t addr,
8279
uint32_t num_spare_area_to_write);
8380
uint32_t nand_read_spare_area(uint8_t *buf, nand_addr_t addr,

firmware/nand_programmer.c

Lines changed: 54 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,15 @@ typedef struct __attribute__((__packed__))
117117
uint8_t ar_setup_time;
118118
uint8_t row_cycles;
119119
uint8_t col_cycles;
120+
uint8_t read1_cmd;
121+
uint8_t read2_cmd;
122+
uint8_t read_id_cmd;
123+
uint8_t reset_cmd;
124+
uint8_t write1_cmd;
125+
uint8_t write2_cmd;
126+
uint8_t erase1_cmd;
127+
uint8_t erase2_cmd;
128+
uint8_t status_cmd;
120129
} np_conf_cmd_t;
121130

122131
enum
@@ -314,7 +323,7 @@ static int np_read_bad_block_info_from_page(np_prog_t *prog, uint32_t block,
314323
uint32_t status, addr = block * prog->chip_info.block_size;
315324

316325
status = nand_read_data(prog->page.buf, page, 0, prog->chip_info.page_size
317-
+ 1, prog->chip_info.row_cycles, prog->chip_info.col_cycles);
326+
+ 1);
318327
switch (status)
319328
{
320329
case NAND_READY:
@@ -652,8 +661,7 @@ static int np_nand_write(np_prog_t *prog)
652661
DEBUG_PRINT("NAND write at 0x%lx %lu bytes\r\n", prog->addr,
653662
prog->page_size);
654663

655-
nand_write_page_async(prog->page.buf, prog->page.page, prog->page_size,
656-
prog->chip_info.row_cycles, prog->chip_info.col_cycles);
664+
nand_write_page_async(prog->page.buf, prog->page.page, prog->page_size);
657665

658666
prog->nand_wr_in_progress = 1;
659667

@@ -801,8 +809,7 @@ static int np_nand_read(uint32_t addr, np_page_t *page, uint32_t page_size,
801809
{
802810
uint32_t status;
803811

804-
status = nand_read_page(page->buf, page->page, page_size,
805-
prog->chip_info.row_cycles, prog->chip_info.col_cycles);
812+
status = nand_read_page(page->buf, page->page, page_size);
806813
switch (status)
807814
{
808815
case NAND_READY:
@@ -970,21 +977,8 @@ static int np_cmd_nand_read(np_prog_t *prog)
970977
return ret;
971978
}
972979

973-
static int np_cmd_nand_conf(np_prog_t *prog)
980+
static void np_fill_chip_info(np_conf_cmd_t *conf_cmd, np_prog_t *prog)
974981
{
975-
np_conf_cmd_t *conf_cmd;
976-
977-
DEBUG_PRINT("Chip configure command\r\n");
978-
979-
if (prog->rx_buf_len < sizeof(np_conf_cmd_t))
980-
{
981-
ERROR_PRINT("Wrong buffer length for configuration command %lu\r\n",
982-
prog->rx_buf_len);
983-
return NP_ERR_LEN_INVALID;
984-
}
985-
986-
conf_cmd = (np_conf_cmd_t *)prog->rx_buf;
987-
988982
prog->chip_info.page_size = conf_cmd->page_size;
989983
prog->chip_info.block_size = conf_cmd->block_size;
990984
prog->chip_info.total_size = conf_cmd->total_size;
@@ -997,8 +991,20 @@ static int np_cmd_nand_conf(np_prog_t *prog)
997991
prog->chip_info.ar_setup_time = conf_cmd->ar_setup_time;
998992
prog->chip_info.row_cycles = conf_cmd->row_cycles;
999993
prog->chip_info.col_cycles = conf_cmd->col_cycles;
1000-
prog->chip_is_conf = 1;
994+
prog->chip_info.read1_cmd = conf_cmd->read1_cmd;
995+
prog->chip_info.read2_cmd = conf_cmd->read2_cmd;
996+
prog->chip_info.read_id_cmd = conf_cmd->read_id_cmd;
997+
prog->chip_info.reset_cmd = conf_cmd->reset_cmd;
998+
prog->chip_info.write1_cmd = conf_cmd->write1_cmd;
999+
prog->chip_info.write2_cmd = conf_cmd->write2_cmd;
1000+
prog->chip_info.erase1_cmd = conf_cmd->erase1_cmd;
1001+
prog->chip_info.erase2_cmd = conf_cmd->erase2_cmd;
1002+
prog->chip_info.status_cmd = conf_cmd->status_cmd;
1003+
prog->chip_is_conf = 1;
1004+
}
10011005

1006+
static void np_print_chip_info(np_prog_t *prog)
1007+
{
10021008
DEBUG_PRINT("Page size: %lu\r\n", prog->chip_info.page_size);
10031009
DEBUG_PRINT("Block size: %lu\r\n", prog->chip_info.block_size);
10041010
DEBUG_PRINT("Total size: %lu\r\n", prog->chip_info.total_size);
@@ -1011,6 +1017,34 @@ static int np_cmd_nand_conf(np_prog_t *prog)
10111017
DEBUG_PRINT("AR setip time: %d\r\n", prog->chip_info.ar_setup_time);
10121018
DEBUG_PRINT("Row cycles: %d\r\n", prog->chip_info.row_cycles);
10131019
DEBUG_PRINT("Col. cycles: %d\r\n", prog->chip_info.col_cycles);
1020+
DEBUG_PRINT("Read command 1: %d\r\n", prog->chip_info.read1_cmd);
1021+
DEBUG_PRINT("Read command 2: %d\r\n", prog->chip_info.read2_cmd);
1022+
DEBUG_PRINT("Read ID command: %d\r\n", prog->chip_info.read_id_cmd);
1023+
DEBUG_PRINT("Reset command: %d\r\n", prog->chip_info.reset_cmd);
1024+
DEBUG_PRINT("Write 1 command: %d\r\n", prog->chip_info.write1_cmd);
1025+
DEBUG_PRINT("Write 2 command: %d\r\n", prog->chip_info.write2_cmd);
1026+
DEBUG_PRINT("Erase 1 command: %d\r\n", prog->chip_info.erase1_cmd);
1027+
DEBUG_PRINT("Erase 2 command: %d\r\n", prog->chip_info.erase2_cmd);
1028+
DEBUG_PRINT("Status command: %d\r\n", prog->chip_info.status_cmd);
1029+
}
1030+
1031+
static int np_cmd_nand_conf(np_prog_t *prog)
1032+
{
1033+
np_conf_cmd_t *conf_cmd;
1034+
1035+
DEBUG_PRINT("Chip configure command\r\n");
1036+
1037+
if (prog->rx_buf_len < sizeof(np_conf_cmd_t))
1038+
{
1039+
ERROR_PRINT("Wrong buffer length for configuration command %lu\r\n",
1040+
prog->rx_buf_len);
1041+
return NP_ERR_LEN_INVALID;
1042+
}
1043+
1044+
conf_cmd = (np_conf_cmd_t *)prog->rx_buf;
1045+
1046+
np_fill_chip_info(conf_cmd, prog);
1047+
np_print_chip_info(prog);
10141048

10151049
nand_init(&prog->chip_info);
10161050

qt/chip_db.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,15 @@ enum
4242
CHIP_PARAM_T_REA,
4343
CHIP_PARAM_ROW_CYCLES,
4444
CHIP_PARAM_COL_CYCLES,
45+
CHIP_PARAM_READ1_CMD,
46+
CHIP_PARAM_READ2_CMD,
47+
CHIP_PARAM_READ_ID_CMD,
48+
CHIP_PARAM_RESET_CMD,
49+
CHIP_PARAM_WRITE1_CMD,
50+
CHIP_PARAM_WRITE2_CMD,
51+
CHIP_PARAM_ERASE1_CMD,
52+
CHIP_PARAM_ERASE2_CMD,
53+
CHIP_PARAM_STATUS_CMD,
4554
CHIP_PARAM_NUM,
4655
};
4756

qt/chip_db_dialog.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -20,12 +20,10 @@ ChipDbDialog::ChipDbDialog(ChipDb *chipDb, QWidget *parent) : QDialog(parent),
2020
HEADER_MED_WIDTH);
2121
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_SPARE_SIZE,
2222
HEADER_MED_WIDTH);
23-
for (int i = CHIP_PARAM_SPARE_SIZE + 1; i < CHIP_PARAM_T_REA; i++)
23+
for (int i = CHIP_PARAM_T_CS; i <= CHIP_PARAM_T_REA; i++)
2424
ui->chipDbTableView->setColumnWidth(i, HEADER_SHORT_WIDTH);
25-
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_ROW_CYCLES,
26-
HEADER_MED_WIDTH);
27-
ui->chipDbTableView->setColumnWidth(CHIP_PARAM_COL_CYCLES,
28-
HEADER_MED_WIDTH);
25+
for (int i = CHIP_PARAM_ROW_CYCLES; i <= CHIP_PARAM_STATUS_CMD; i++)
26+
ui->chipDbTableView->setColumnWidth(i, HEADER_MED_WIDTH);
2927

3028
connect(ui->addChipDbButton, SIGNAL(clicked()), this,
3129
SLOT(slotAddChipDbButtonClicked()));

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