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#define ROW_ADDRESS (addr.page + (addr.block + (addr.zone * NAND_ZONE_SIZE)) * \
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NAND_BLOCK_SIZE)
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+ typedef struct
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+ {
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+ uint8_t row_cycles ;
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+ uint8_t col_cycles ;
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+ uint8_t read1_cmd ;
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+ uint8_t read2_cmd ;
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+ uint8_t read_id_cmd ;
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+ uint8_t reset_cmd ;
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+ uint8_t write1_cmd ;
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+ uint8_t write2_cmd ;
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+ uint8_t erase1_cmd ;
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+ uint8_t erase2_cmd ;
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+ uint8_t status_cmd ;
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+ } fsmc_cmd_t ;
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+
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+ static fsmc_cmd_t fsmc_cmd ;
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+
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static void nand_gpio_init (void )
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{
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GPIO_InitTypeDef gpio_init ;
@@ -70,18 +87,34 @@ static void nand_fsmc_init(chip_info_t *chip_info)
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FSMC_NANDCmd (FSMC_Bank2_NAND , ENABLE );
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}
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+ static void nand_cmd_init (chip_info_t * chip_info )
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+ {
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+ fsmc_cmd .row_cycles = chip_info -> row_cycles ;
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+ fsmc_cmd .col_cycles = chip_info -> col_cycles ;
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+ fsmc_cmd .read1_cmd = chip_info -> read1_cmd ;
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+ fsmc_cmd .read2_cmd = chip_info -> read2_cmd ;
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+ fsmc_cmd .read_id_cmd = chip_info -> read_id_cmd ;
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+ fsmc_cmd .reset_cmd = chip_info -> reset_cmd ;
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+ fsmc_cmd .write1_cmd = chip_info -> write1_cmd ;
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+ fsmc_cmd .write2_cmd = chip_info -> write2_cmd ;
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+ fsmc_cmd .erase1_cmd = chip_info -> erase1_cmd ;
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+ fsmc_cmd .erase2_cmd = chip_info -> erase2_cmd ;
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+ fsmc_cmd .status_cmd = chip_info -> status_cmd ;
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+ }
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+
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void nand_init (chip_info_t * chip_info )
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{
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nand_gpio_init ();
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nand_fsmc_init (chip_info );
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+ nand_cmd_init (chip_info );
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}
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void nand_read_id (nand_id_t * nand_id )
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{
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uint32_t data = 0 ;
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/* Send Command to the command area */
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = 0x90 ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . read_id_cmd ;
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = 0x00 ;
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/* Sequence to read ID from NAND flash */
@@ -93,14 +126,13 @@ void nand_read_id(nand_id_t *nand_id)
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nand_id -> fourth_id = ADDR_4th_CYCLE (data );
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}
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- void nand_write_page_async (uint8_t * buf , uint32_t page , uint32_t page_size ,
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- uint8_t row_cycles , uint8_t col_cycles )
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+ void nand_write_page_async (uint8_t * buf , uint32_t page , uint32_t page_size )
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{
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uint32_t i ;
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_WRITE0 ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . write1_cmd ;
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- switch (col_cycles )
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+ switch (fsmc_cmd . col_cycles )
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{
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case 1 :
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = 0x00 ;
@@ -124,7 +156,7 @@ void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
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break ;
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}
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- switch (row_cycles )
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+ switch (fsmc_cmd . row_cycles )
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{
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case 1 :
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = ADDR_1st_CYCLE (page );
@@ -151,25 +183,25 @@ void nand_write_page_async(uint8_t *buf, uint32_t page, uint32_t page_size,
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for (i = 0 ; i < page_size ; i ++ )
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* (__IO uint8_t * )(Bank_NAND_ADDR | DATA_AREA ) = buf [i ];
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_WRITE_TRUE1 ;
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+ if (fsmc_cmd .write2_cmd != 0xFF )
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd .write2_cmd ;
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}
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- uint32_t nand_write_page (uint8_t * buf , uint32_t page , uint32_t page_size ,
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- uint8_t row_cycles , uint8_t col_cycles )
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+ uint32_t nand_write_page (uint8_t * buf , uint32_t page , uint32_t page_size )
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{
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- nand_write_page_async (buf , page , page_size , row_cycles , col_cycles );
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+ nand_write_page_async (buf , page , page_size );
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return nand_get_status ();
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}
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uint32_t nand_read_data (uint8_t * buf , uint32_t page , uint32_t page_offset ,
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- uint32_t data_size , uint8_t row_cycles , uint8_t col_cycles )
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+ uint32_t data_size )
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{
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uint32_t i ;
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_READ0 ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . read1_cmd ;
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- switch (col_cycles )
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+ switch (fsmc_cmd . col_cycles )
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{
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case 1 :
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) =
@@ -202,7 +234,7 @@ uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
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break ;
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}
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- switch (row_cycles )
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+ switch (fsmc_cmd . row_cycles )
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{
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case 1 :
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = ADDR_1st_CYCLE (page );
@@ -226,18 +258,18 @@ uint32_t nand_read_data(uint8_t *buf, uint32_t page, uint32_t page_offset,
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break ;
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}
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_READ1 ;
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+ if (fsmc_cmd .read2_cmd != 0xFF )
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd .read2_cmd ;
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for (i = 0 ; i < data_size ; i ++ )
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buf [i ]= * (__IO uint8_t * )(Bank_NAND_ADDR | DATA_AREA );
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return nand_get_status ();
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}
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- uint32_t nand_read_page (uint8_t * buf , uint32_t page , uint32_t page_size ,
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- uint8_t row_cycles , uint8_t col_cycles )
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+ uint32_t nand_read_page (uint8_t * buf , uint32_t page , uint32_t page_size )
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{
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- return nand_read_data (buf , page , 0 , page_size , row_cycles , col_cycles );
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+ return nand_read_data (buf , page , 0 , page_size );
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}
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/**
@@ -361,13 +393,13 @@ uint32_t nand_read_spare_area(uint8_t *buf, nand_addr_t addr,
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uint32_t nand_erase_block (uint32_t page )
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{
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_ERASE0 ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . erase1_cmd ;
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = ADDR_1st_CYCLE (page );
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = ADDR_2nd_CYCLE (page );
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* (__IO uint8_t * )(Bank_NAND_ADDR | ADDR_AREA ) = ADDR_3rd_CYCLE (page );
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_ERASE1 ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . erase2_cmd ;
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return nand_get_status ();
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}
@@ -377,9 +409,9 @@ uint32_t nand_erase_block(uint32_t page)
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* @param None
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* @retval NAND_READY
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*/
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- uint32_t nand_reset (void )
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+ uint32_t nand_reset ()
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{
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_RESET ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . reset_cmd ;
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return (NAND_READY );
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}
@@ -425,7 +457,7 @@ uint32_t nand_read_status(void)
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uint32_t data = 0x00 , status = NAND_BUSY ;
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/* Read status operation */
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- * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = NAND_CMD_STATUS ;
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+ * (__IO uint8_t * )(Bank_NAND_ADDR | CMD_AREA ) = fsmc_cmd . status_cmd ;
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data = * (__IO uint8_t * )(Bank_NAND_ADDR );
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if ((data & NAND_ERROR ) == NAND_ERROR )
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