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Deleted calculation comment since it is done on host
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firmware/fsmc_nand.c

Lines changed: 1 addition & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -49,63 +49,7 @@ static void nand_fsmc_init(chip_info_t *chip_info)
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FSMC_NANDInitTypeDef fsmc_init;
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FSMC_NAND_PCCARDTimingInitTypeDef timing_init;
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52-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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/*-- FSMC Configuration --------------------------------------------------*/
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/* Calculations of timing paramaters
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* _ _ _ _ _ _ _ _ _ _ _ _
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* HCLK _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
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* _____ _________________________________ ________
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* A[25:0] _____|_________________________________|________
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* _____ ________
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* NCE |_________________________________|
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*
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* |SET+1| WAIT+1 |HOLD+1 |
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* ___________ ________________
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* NOE/NWE |___________________|
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*
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* | HIZ+1 |
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* Write _________________________
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* data -------------|_________________________|--------
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*
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* Read __________________________
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* data -----------|__________________________|---------
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*
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* (SET + 1) * tHCLK >= max(tCS, tCLS, tALS) - tWP
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* (SET + 1) * tHCLK >= max(tCLR, tAR)
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* (WAIT + 1) * tHCLK >= max(tWP, tRP)
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* (WAIT + 1) * tHCLK >= (tREA + tsu(D-NOE))
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* (HIZ + 1) * tHCLK >= max(tCS , tALS, tCLS) - tDS
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* (HOLD + 1) x tHCLK >= max(tCH, tCLH, tALH)
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* ((WAIT + 1) + (HOLD + 1) + (SET + 1)) x tHCLK >= max(tWC, tRC)
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* tsu(D-NOE) = 25ns
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* tHCLK = 1/72MHz = 13.89ns
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*/
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/* K9F2G08U0C parameters:
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* tCS = 20ns
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* tCLS = 12ns
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* tALS = 12ns
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* tCLR = 10ns
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* tAR = 10ns
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* tWP = 12ns
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* tRP = 12ns
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* tDS = 12ns
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* tCH = 5ns
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* tCLH = 5ns
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* tALH = 5ns
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* tWC = 25ns
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* tRC = 25ns
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* tREA = 20ns
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* =>
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* SET = 1
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* WAIT = 3
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* HOLD = 1
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* HIZ = 1
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* TCLR = 1
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* TAR = 1
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*/
52+
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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11054
timing_init.FSMC_SetupTime = chip_info->setup_time;
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timing_init.FSMC_WaitSetupTime = chip_info->wait_setup_time;

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