Fixed compilation of CM3

bbogush · bbogush · commit b6c4da5cb3b5 · 2020-03-28T16:46:51.000+02:00
diff --git a/firmware/libs/spl/CMSIS/CM3/CoreSupport/core_cm3.c b/firmware/libs/spl/CMSIS/CM3/CoreSupport/core_cm3.c
@@ -733,7 +733,7 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr)
 {
    uint32_t result=0;
   
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 
@@ -750,7 +750,7 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr)
 {
    uint32_t result=0;
   
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
    return(result);
 }
 

Original file line number	Diff line number	Diff line change
`@@ -733,7 +733,7 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr)`
`733`	`733`	`{`
`734`	`734`	`uint32_t result=0;`
`735`	`735`
`736`		`- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );`
	`736`	`+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );`
`737`	`737`	`return(result);`
`738`	`738`	`}`
`739`	`739`
`@@ -750,7 +750,7 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr)`
`750`	`750`	`{`
`751`	`751`	`uint32_t result=0;`
`752`	`752`
`753`		`- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );`
	`753`	`+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );`
`754`	`754`	`return(result);`
`755`	`755`	`}`
`756`	`756`