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Separated generic chip configuration and HAL configuration
1 parent d1adb72 commit d2be0bf

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6 files changed

+82
-125
lines changed

6 files changed

+82
-125
lines changed

‎firmware/programmer/chip_info.h

Lines changed: 1 addition & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -11,25 +11,7 @@ typedef struct
1111
uint32_t page_size; /* without spare area */
1212
uint32_t block_size;
1313
uint32_t total_size;
14-
uint32_t spare_size;
15-
uint8_t setup_time;
16-
uint8_t wait_setup_time;
17-
uint8_t hold_setup_time;
18-
uint8_t hi_z_setup_time;
19-
uint8_t clr_setup_time;
20-
uint8_t ar_setup_time;
21-
uint8_t row_cycles;
22-
uint8_t col_cycles;
23-
uint8_t read1_cmd;
24-
uint8_t read2_cmd;
25-
uint8_t read_spare_cmd;
26-
uint8_t read_id_cmd;
27-
uint8_t reset_cmd;
28-
uint8_t write1_cmd;
29-
uint8_t write2_cmd;
30-
uint8_t erase1_cmd;
31-
uint8_t erase2_cmd;
32-
uint8_t status_cmd;
14+
uint32_t spare_size;
3315
uint8_t bb_mark_off;
3416
} chip_info_t;
3517

‎firmware/programmer/flash_hal.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ enum
2121

2222
typedef struct
2323
{
24-
void (*init)(chip_info_t *chip_info);
24+
int (*init)(void *conf, uint32_t conf_size);
2525
void (*uninit)();
2626
void (*read_id)(chip_id_t *chip_id);
2727
uint32_t (*erase_block)(uint32_t page);

‎firmware/programmer/fsmc_nand.c

Lines changed: 66 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
*/
55

66
#include "fsmc_nand.h"
7+
#include "log.h"
78
#include <stm32f10x.h>
89

910
#define CMD_AREA (uint32_t)(1<<16) /* A16 = CLE high */
@@ -33,8 +34,14 @@
3334

3435
#define UNDEFINED_CMD 0xFF
3536

36-
typedef struct
37+
typedef struct __attribute__((__packed__))
3738
{
39+
uint8_t setup_time;
40+
uint8_t wait_setup_time;
41+
uint8_t hold_setup_time;
42+
uint8_t hi_z_setup_time;
43+
uint8_t clr_setup_time;
44+
uint8_t ar_setup_time;
3845
uint8_t row_cycles;
3946
uint8_t col_cycles;
4047
uint8_t read1_cmd;
@@ -47,9 +54,9 @@ typedef struct
4754
uint8_t erase1_cmd;
4855
uint8_t erase2_cmd;
4956
uint8_t status_cmd;
50-
} fsmc_cmd_t;
57+
} fsmc_conf_t;
5158

52-
static fsmc_cmd_t fsmc_cmd;
59+
static fsmc_conf_t fsmc_conf;
5360

5461
static void nand_gpio_init(void)
5562
{
@@ -83,53 +90,66 @@ static void nand_gpio_init(void)
8390

8491
}
8592

86-
static void nand_fsmc_init(chip_info_t *chip_info)
93+
static void nand_fsmc_init()
8794
{
8895
FSMC_NANDInitTypeDef fsmc_init;
8996
FSMC_NAND_PCCARDTimingInitTypeDef timing_init;
9097

9198
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
9299

93-
timing_init.FSMC_SetupTime = chip_info->setup_time;
94-
timing_init.FSMC_WaitSetupTime = chip_info->wait_setup_time;
95-
timing_init.FSMC_HoldSetupTime = chip_info->hold_setup_time;
96-
timing_init.FSMC_HiZSetupTime = chip_info->hi_z_setup_time;
100+
timing_init.FSMC_SetupTime = fsmc_conf.setup_time;
101+
timing_init.FSMC_WaitSetupTime = fsmc_conf.wait_setup_time;
102+
timing_init.FSMC_HoldSetupTime = fsmc_conf.hold_setup_time;
103+
timing_init.FSMC_HiZSetupTime = fsmc_conf.hi_z_setup_time;
97104

98105
fsmc_init.FSMC_Bank = FSMC_Bank2_NAND;
99106
fsmc_init.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
100107
fsmc_init.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
101108
fsmc_init.FSMC_ECC = FSMC_ECC_Enable;
102109
fsmc_init.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes;
103-
fsmc_init.FSMC_TCLRSetupTime = chip_info->clr_setup_time;
104-
fsmc_init.FSMC_TARSetupTime = chip_info->ar_setup_time;
110+
fsmc_init.FSMC_TCLRSetupTime = fsmc_conf.clr_setup_time;
111+
fsmc_init.FSMC_TARSetupTime = fsmc_conf.ar_setup_time;
105112
fsmc_init.FSMC_CommonSpaceTimingStruct = &timing_init;
106113
fsmc_init.FSMC_AttributeSpaceTimingStruct = &timing_init;
107114
FSMC_NANDInit(&fsmc_init);
108115

109116
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
110117
}
111118

112-
static void nand_cmd_init(chip_info_t *chip_info)
119+
static void nand_print_fsmc_info()
113120
{
114-
fsmc_cmd.row_cycles = chip_info->row_cycles;
115-
fsmc_cmd.col_cycles = chip_info->col_cycles;
116-
fsmc_cmd.read1_cmd = chip_info->read1_cmd;
117-
fsmc_cmd.read2_cmd = chip_info->read2_cmd;
118-
fsmc_cmd.read_spare_cmd = chip_info->read_spare_cmd;
119-
fsmc_cmd.read_id_cmd = chip_info->read_id_cmd;
120-
fsmc_cmd.reset_cmd = chip_info->reset_cmd;
121-
fsmc_cmd.write1_cmd = chip_info->write1_cmd;
122-
fsmc_cmd.write2_cmd = chip_info->write2_cmd;
123-
fsmc_cmd.erase1_cmd = chip_info->erase1_cmd;
124-
fsmc_cmd.erase2_cmd = chip_info->erase2_cmd;
125-
fsmc_cmd.status_cmd = chip_info->status_cmd;
121+
DEBUG_PRINT("Setup time: %d\r\n", fsmc_conf.setup_time);
122+
DEBUG_PRINT("Wait setup time: %d\r\n", fsmc_conf.wait_setup_time);
123+
DEBUG_PRINT("Hold setup time: %d\r\n", fsmc_conf.hold_setup_time);
124+
DEBUG_PRINT("HiZ setup time: %d\r\n", fsmc_conf.hi_z_setup_time);
125+
DEBUG_PRINT("CLR setip time: %d\r\n", fsmc_conf.clr_setup_time);
126+
DEBUG_PRINT("AR setip time: %d\r\n", fsmc_conf.ar_setup_time);
127+
DEBUG_PRINT("Row cycles: %d\r\n", fsmc_conf.row_cycles);
128+
DEBUG_PRINT("Col. cycles: %d\r\n", fsmc_conf.col_cycles);
129+
DEBUG_PRINT("Read command 1: %d\r\n", fsmc_conf.read1_cmd);
130+
DEBUG_PRINT("Read command 2: %d\r\n", fsmc_conf.read2_cmd);
131+
DEBUG_PRINT("Read spare command: %d\r\n", fsmc_conf.read_spare_cmd);
132+
DEBUG_PRINT("Read ID command: %d\r\n", fsmc_conf.read_id_cmd);
133+
DEBUG_PRINT("Reset command: %d\r\n", fsmc_conf.reset_cmd);
134+
DEBUG_PRINT("Write 1 command: %d\r\n", fsmc_conf.write1_cmd);
135+
DEBUG_PRINT("Write 2 command: %d\r\n", fsmc_conf.write2_cmd);
136+
DEBUG_PRINT("Erase 1 command: %d\r\n", fsmc_conf.erase1_cmd);
137+
DEBUG_PRINT("Erase 2 command: %d\r\n", fsmc_conf.erase2_cmd);
138+
DEBUG_PRINT("Status command: %d\r\n", fsmc_conf.status_cmd);
126139
}
127140

128-
static void nand_init(chip_info_t *chip_info)
141+
static int nand_init(void *conf, uint32_t conf_size)
129142
{
143+
if (conf_size < sizeof(fsmc_conf_t))
144+
return -1;
145+
146+
fsmc_conf = *(fsmc_conf_t *)conf;
147+
130148
nand_gpio_init();
131-
nand_fsmc_init(chip_info);
132-
nand_cmd_init(chip_info);
149+
nand_fsmc_init(fsmc_conf);
150+
nand_print_fsmc_info();
151+
152+
return 0;
133153
}
134154

135155
static void nand_uninit()
@@ -141,7 +161,7 @@ static uint32_t nand_read_status()
141161
{
142162
uint32_t data, status;
143163

144-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.status_cmd;
164+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.status_cmd;
145165
data = *(__IO uint8_t *)(Bank_NAND_ADDR);
146166

147167
if ((data & NAND_ERROR) == NAND_ERROR)
@@ -177,7 +197,7 @@ static void nand_read_id(chip_id_t *nand_id)
177197
{
178198
uint32_t data = 0;
179199

180-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read_id_cmd;
200+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.read_id_cmd;
181201
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
182202

183203
/* Sequence to read ID from NAND flash */
@@ -196,9 +216,9 @@ static void nand_write_page_async(uint8_t *buf, uint32_t page,
196216
{
197217
uint32_t i;
198218

199-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.write1_cmd;
219+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.write1_cmd;
200220

201-
switch (fsmc_cmd.col_cycles)
221+
switch (fsmc_conf.col_cycles)
202222
{
203223
case 1:
204224
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
@@ -222,7 +242,7 @@ static void nand_write_page_async(uint8_t *buf, uint32_t page,
222242
break;
223243
}
224244

225-
switch (fsmc_cmd.row_cycles)
245+
switch (fsmc_conf.row_cycles)
226246
{
227247
case 1:
228248
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
@@ -249,18 +269,18 @@ static void nand_write_page_async(uint8_t *buf, uint32_t page,
249269
for(i = 0; i < page_size; i++)
250270
*(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = buf[i];
251271

252-
if (fsmc_cmd.write2_cmd != UNDEFINED_CMD)
253-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.write2_cmd;
272+
if (fsmc_conf.write2_cmd != UNDEFINED_CMD)
273+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.write2_cmd;
254274
}
255275

256276
static uint32_t nand_read_data(uint8_t *buf, uint32_t page,
257277
uint32_t page_offset, uint32_t data_size)
258278
{
259279
uint32_t i;
260280

261-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read1_cmd;
281+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.read1_cmd;
262282

263-
switch (fsmc_cmd.col_cycles)
283+
switch (fsmc_conf.col_cycles)
264284
{
265285
case 1:
266286
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
@@ -293,7 +313,7 @@ static uint32_t nand_read_data(uint8_t *buf, uint32_t page,
293313
break;
294314
}
295315

296-
switch (fsmc_cmd.row_cycles)
316+
switch (fsmc_conf.row_cycles)
297317
{
298318
case 1:
299319
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
@@ -317,8 +337,8 @@ static uint32_t nand_read_data(uint8_t *buf, uint32_t page,
317337
break;
318338
}
319339

320-
if (fsmc_cmd.read2_cmd != UNDEFINED_CMD)
321-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read2_cmd;
340+
if (fsmc_conf.read2_cmd != UNDEFINED_CMD)
341+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.read2_cmd;
322342

323343
for (i = 0; i < data_size; i++)
324344
buf[i] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
@@ -336,12 +356,12 @@ static uint32_t nand_read_spare_data(uint8_t *buf, uint32_t page,
336356
{
337357
uint32_t i;
338358

339-
if (fsmc_cmd.read_spare_cmd == UNDEFINED_CMD)
359+
if (fsmc_conf.read_spare_cmd == UNDEFINED_CMD)
340360
return FLASH_STATUS_INVALID_CMD;
341361

342-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.read_spare_cmd;
362+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.read_spare_cmd;
343363

344-
switch (fsmc_cmd.col_cycles)
364+
switch (fsmc_conf.col_cycles)
345365
{
346366
case 1:
347367
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) =
@@ -374,7 +394,7 @@ static uint32_t nand_read_spare_data(uint8_t *buf, uint32_t page,
374394
break;
375395
}
376396

377-
switch (fsmc_cmd.row_cycles)
397+
switch (fsmc_conf.row_cycles)
378398
{
379399
case 1:
380400
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
@@ -406,9 +426,9 @@ static uint32_t nand_read_spare_data(uint8_t *buf, uint32_t page,
406426

407427
static uint32_t nand_erase_block(uint32_t page)
408428
{
409-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.erase1_cmd;
429+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.erase1_cmd;
410430

411-
switch (fsmc_cmd.row_cycles)
431+
switch (fsmc_conf.row_cycles)
412432
{
413433
case 1:
414434
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(page);
@@ -432,8 +452,8 @@ static uint32_t nand_erase_block(uint32_t page)
432452
break;
433453
}
434454

435-
if (fsmc_cmd.erase2_cmd != UNDEFINED_CMD)
436-
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_cmd.erase2_cmd;
455+
if (fsmc_conf.erase2_cmd != UNDEFINED_CMD)
456+
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = fsmc_conf.erase2_cmd;
437457

438458
return nand_get_status();
439459
}

‎firmware/programmer/nand_programmer.c

Lines changed: 10 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -122,25 +122,8 @@ typedef struct __attribute__((__packed__))
122122
uint32_t block_size;
123123
uint32_t total_size;
124124
uint32_t spare_size;
125-
uint8_t setup_time;
126-
uint8_t wait_setup_time;
127-
uint8_t hold_setup_time;
128-
uint8_t hi_z_setup_time;
129-
uint8_t clr_setup_time;
130-
uint8_t ar_setup_time;
131-
uint8_t row_cycles;
132-
uint8_t col_cycles;
133-
uint8_t read1_cmd;
134-
uint8_t read2_cmd;
135-
uint8_t read_spare_cmd;
136-
uint8_t read_id_cmd;
137-
uint8_t reset_cmd;
138-
uint8_t write1_cmd;
139-
uint8_t write2_cmd;
140-
uint8_t erase1_cmd;
141-
uint8_t erase2_cmd;
142-
uint8_t status_cmd;
143125
uint8_t bb_mark_off;
126+
uint8_t hal_conf[];
144127
} np_conf_cmd_t;
145128

146129
enum
@@ -1028,27 +1011,9 @@ static void np_fill_chip_info(np_conf_cmd_t *conf_cmd, np_prog_t *prog)
10281011
prog->chip_info.page_size = conf_cmd->page_size;
10291012
prog->chip_info.block_size = conf_cmd->block_size;
10301013
prog->chip_info.total_size = conf_cmd->total_size;
1031-
prog->chip_info.spare_size = conf_cmd->spare_size;
1032-
prog->chip_info.setup_time = conf_cmd->setup_time;
1033-
prog->chip_info.wait_setup_time = conf_cmd->wait_setup_time;
1034-
prog->chip_info.hold_setup_time = conf_cmd->hold_setup_time;
1035-
prog->chip_info.hi_z_setup_time = conf_cmd->hi_z_setup_time;
1036-
prog->chip_info.clr_setup_time = conf_cmd->clr_setup_time;
1037-
prog->chip_info.ar_setup_time = conf_cmd->ar_setup_time;
1038-
prog->chip_info.row_cycles = conf_cmd->row_cycles;
1039-
prog->chip_info.col_cycles = conf_cmd->col_cycles;
1040-
prog->chip_info.read1_cmd = conf_cmd->read1_cmd;
1041-
prog->chip_info.read2_cmd = conf_cmd->read2_cmd;
1042-
prog->chip_info.read_spare_cmd = conf_cmd->read_spare_cmd;
1043-
prog->chip_info.read_id_cmd = conf_cmd->read_id_cmd;
1044-
prog->chip_info.reset_cmd = conf_cmd->reset_cmd;
1045-
prog->chip_info.write1_cmd = conf_cmd->write1_cmd;
1046-
prog->chip_info.write2_cmd = conf_cmd->write2_cmd;
1047-
prog->chip_info.erase1_cmd = conf_cmd->erase1_cmd;
1048-
prog->chip_info.erase2_cmd = conf_cmd->erase2_cmd;
1049-
prog->chip_info.status_cmd = conf_cmd->status_cmd;
1014+
prog->chip_info.spare_size = conf_cmd->spare_size;
10501015
prog->chip_info.bb_mark_off = conf_cmd->bb_mark_off;
1051-
prog->chip_is_conf = 1;
1016+
prog->chip_is_conf = 1;
10521017
}
10531018

10541019
static void np_print_chip_info(np_prog_t *prog)
@@ -1057,24 +1022,6 @@ static void np_print_chip_info(np_prog_t *prog)
10571022
DEBUG_PRINT("Block size: %lu\r\n", prog->chip_info.block_size);
10581023
DEBUG_PRINT("Total size: %lu\r\n", prog->chip_info.total_size);
10591024
DEBUG_PRINT("Spare size: %lu\r\n", prog->chip_info.spare_size);
1060-
DEBUG_PRINT("Setup time: %d\r\n", prog->chip_info.setup_time);
1061-
DEBUG_PRINT("Wait setup time: %d\r\n", prog->chip_info.wait_setup_time);
1062-
DEBUG_PRINT("Hold setup time: %d\r\n", prog->chip_info.hold_setup_time);
1063-
DEBUG_PRINT("HiZ setup time: %d\r\n", prog->chip_info.hi_z_setup_time);
1064-
DEBUG_PRINT("CLR setip time: %d\r\n", prog->chip_info.clr_setup_time);
1065-
DEBUG_PRINT("AR setip time: %d\r\n", prog->chip_info.ar_setup_time);
1066-
DEBUG_PRINT("Row cycles: %d\r\n", prog->chip_info.row_cycles);
1067-
DEBUG_PRINT("Col. cycles: %d\r\n", prog->chip_info.col_cycles);
1068-
DEBUG_PRINT("Read command 1: %d\r\n", prog->chip_info.read1_cmd);
1069-
DEBUG_PRINT("Read command 2: %d\r\n", prog->chip_info.read2_cmd);
1070-
DEBUG_PRINT("Read spare command: %d\r\n", prog->chip_info.read_spare_cmd);
1071-
DEBUG_PRINT("Read ID command: %d\r\n", prog->chip_info.read_id_cmd);
1072-
DEBUG_PRINT("Reset command: %d\r\n", prog->chip_info.reset_cmd);
1073-
DEBUG_PRINT("Write 1 command: %d\r\n", prog->chip_info.write1_cmd);
1074-
DEBUG_PRINT("Write 2 command: %d\r\n", prog->chip_info.write2_cmd);
1075-
DEBUG_PRINT("Erase 1 command: %d\r\n", prog->chip_info.erase1_cmd);
1076-
DEBUG_PRINT("Erase 2 command: %d\r\n", prog->chip_info.erase2_cmd);
1077-
DEBUG_PRINT("Status command: %d\r\n", prog->chip_info.status_cmd);
10781025
DEBUG_PRINT("Bad block mark offset: %d\r\n", prog->chip_info.bb_mark_off);
10791026
}
10801027

@@ -1097,7 +1044,13 @@ static int np_cmd_nand_conf(np_prog_t *prog)
10971044
np_print_chip_info(prog);
10981045

10991046
prog->hal = conf_cmd->hal;
1100-
hal[prog->hal]->init(&prog->chip_info);
1047+
if (hal[prog->hal]->init(conf_cmd->hal_conf,
1048+
prog->rx_buf_len - sizeof(np_conf_cmd_t)))
1049+
{
1050+
ERROR_PRINT("Wrong buffer length for hal configuration command %lu\r\n",
1051+
prog->rx_buf_len);
1052+
return NP_ERR_LEN_INVALID;
1053+
}
11011054

11021055
nand_bad_block_table_init();
11031056
prog->bb_is_read = 0;

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