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[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (llvm#146637)
This is alternative to llvm#145965 that allows RegisterSDNode to be handled without making a special case.
1 parent 191583c commit b62826c

14 files changed

+106
-78
lines changed

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -631,16 +631,17 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
631631
void
632632
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
633633
VRBaseMapType &VRBaseMap) {
634-
Register VReg = getVR(Node->getOperand(0), VRBaseMap);
635-
636634
// Create the new VReg in the destination class and emit a copy.
637635
unsigned DstRCIdx = Node->getConstantOperandVal(1);
638636
const TargetRegisterClass *DstRC =
639637
TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
640638
Register NewVReg = MRI->createVirtualRegister(DstRC);
641-
BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
642-
NewVReg).addReg(VReg);
639+
const MCInstrDesc &II = TII->get(TargetOpcode::COPY);
640+
MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
641+
AddOperand(MIB, Node->getOperand(0), 1, &II, VRBaseMap, /*IsDebug=*/false,
642+
/*IsClone=*/false, /*IsCloned*/ false);
643643

644+
MBB->insert(InsertPos, MIB);
644645
SDValue Op(Node, 0);
645646
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
646647
(void)isNew; // Silence compiler warning.

‎llvm/test/CodeGen/AArch64/bf16_fast_math.ll‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -19,13 +19,13 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) {
1919
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
2020
; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
2121
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr
22-
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
22+
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
2323
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY4]], 16, 16
2424
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY4]]
2525
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
2626
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], killed [[MOVi32imm]]
2727
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
28-
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
28+
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
2929
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr16 = COPY [[COPY5]].hsub
3030
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY6]]
3131
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -65,13 +65,13 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) {
6565
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
6666
; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
6767
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr
68-
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
68+
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
6969
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY4]], 16, 16
7070
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY4]]
7171
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
7272
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], killed [[MOVi32imm]]
7373
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
74-
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
74+
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
7575
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr16 = COPY [[COPY5]].hsub
7676
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY6]]
7777
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -111,13 +111,13 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) {
111111
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
112112
; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
113113
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr
114-
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
114+
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
115115
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY4]], 16, 16
116116
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY4]]
117117
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
118118
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], killed [[MOVi32imm]]
119119
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
120-
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
120+
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
121121
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr16 = COPY [[COPY5]].hsub
122122
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY6]]
123123
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -161,13 +161,13 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
161161
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
162162
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
163163
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr
164-
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
164+
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
165165
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY5]], 16, 16
166166
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY5]]
167167
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
168168
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], [[MOVi32imm]]
169169
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
170-
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
170+
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
171171
; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub
172172
; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub
173173
; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]]
@@ -176,12 +176,12 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
176176
; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]]
177177
; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub
178178
; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr
179-
; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY [[FADDSrr1]]
179+
; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr1]]
180180
; CHECK-NOBF16-NEXT: [[UBFMWri2:%[0-9]+]]:gpr32 = UBFMWri [[COPY10]], 16, 16
181181
; CHECK-NOBF16-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri2]], [[COPY10]]
182182
; CHECK-NOBF16-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr2]], [[MOVi32imm]]
183183
; CHECK-NOBF16-NEXT: [[UBFMWri3:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr3]], 16, 31
184-
; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY [[UBFMWri3]]
184+
; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri3]]
185185
; CHECK-NOBF16-NEXT: [[COPY12:%[0-9]+]]:fpr16 = COPY [[COPY11]].hsub
186186
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY12]]
187187
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -232,13 +232,13 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z)
232232
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
233233
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
234234
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr
235-
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
235+
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
236236
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY5]], 16, 16
237237
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY5]]
238238
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
239239
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], [[MOVi32imm]]
240240
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
241-
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
241+
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
242242
; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub
243243
; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub
244244
; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]]
@@ -247,12 +247,12 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z)
247247
; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]]
248248
; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub
249249
; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr
250-
; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY [[FADDSrr1]]
250+
; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr1]]
251251
; CHECK-NOBF16-NEXT: [[UBFMWri2:%[0-9]+]]:gpr32 = UBFMWri [[COPY10]], 16, 16
252252
; CHECK-NOBF16-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri2]], [[COPY10]]
253253
; CHECK-NOBF16-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr2]], [[MOVi32imm]]
254254
; CHECK-NOBF16-NEXT: [[UBFMWri3:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr3]], 16, 31
255-
; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY [[UBFMWri3]]
255+
; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri3]]
256256
; CHECK-NOBF16-NEXT: [[COPY12:%[0-9]+]]:fpr16 = COPY [[COPY11]].hsub
257257
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY12]]
258258
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -299,13 +299,13 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
299299
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
300300
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
301301
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr
302-
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
302+
; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
303303
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY5]], 16, 16
304304
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY5]]
305305
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
306306
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], [[MOVi32imm]]
307307
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
308-
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
308+
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
309309
; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub
310310
; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub
311311
; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]]
@@ -314,12 +314,12 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
314314
; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]]
315315
; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub
316316
; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr
317-
; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY [[FADDSrr1]]
317+
; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr1]]
318318
; CHECK-NOBF16-NEXT: [[UBFMWri2:%[0-9]+]]:gpr32 = UBFMWri [[COPY10]], 16, 16
319319
; CHECK-NOBF16-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri2]], [[COPY10]]
320320
; CHECK-NOBF16-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr2]], [[MOVi32imm]]
321321
; CHECK-NOBF16-NEXT: [[UBFMWri3:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr3]], 16, 31
322-
; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY [[UBFMWri3]]
322+
; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri3]]
323323
; CHECK-NOBF16-NEXT: [[COPY12:%[0-9]+]]:fpr16 = COPY [[COPY11]].hsub
324324
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY12]]
325325
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0

‎llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ define amdgpu_kernel void @s_ctpop_i32(ptr addrspace(1) noalias %out, i32 %val)
1111

1212
; GCN-LABEL: name: s_ctpop_i64
1313
; GCN: %[[BCNT:[0-9]+]]:sreg_32 = S_BCNT1_I32_B64
14-
; GCN: %[[SREG1:[0-9]+]]:sreg_32 = COPY %[[BCNT]]
14+
; GCN: %[[SREG1:[0-9]+]]:sreg_32 = COPY killed %[[BCNT]]
1515
; GCN: %[[SREG2:[0-9]+]]:sreg_32 = S_MOV_B32 0
1616
; GCN: REG_SEQUENCE killed %[[SREG1]], %subreg.sub0, killed %[[SREG2]], %subreg.sub1
1717
define amdgpu_kernel void @s_ctpop_i64(ptr addrspace(1) noalias %out, i64 %val) nounwind {

‎llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -398,7 +398,7 @@ define amdgpu_kernel void @uniform_fneg_f64(ptr addrspace(1) %out, ptr addrspace
398398
; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1
399399
; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
400400
; GCN: %[[XOR:[0-9]+]]:sreg_32 = S_XOR_B32 killed %[[HI32]], killed %[[SREG_MASK]]
401-
; GCN: %[[XOR_COPY:[0-9]+]]:sreg_32 = COPY %[[XOR]]
401+
; GCN: %[[XOR_COPY:[0-9]+]]:sreg_32 = COPY killed %[[XOR]]
402402
; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[XOR_COPY]], %subreg.sub1
403403

404404
%in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %idx
@@ -440,7 +440,7 @@ define amdgpu_kernel void @uniform_fabs_f64(ptr addrspace(1) %out, ptr addrspace
440440
; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1
441441
; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
442442
; GCN: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %[[HI32]], killed %[[SREG_MASK]]
443-
; GCN: %[[AND_COPY:[0-9]+]]:sreg_32 = COPY %[[AND]]
443+
; GCN: %[[AND_COPY:[0-9]+]]:sreg_32 = COPY killed %[[AND]]
444444
; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[AND_COPY]], %subreg.sub1
445445

446446

@@ -484,7 +484,7 @@ define amdgpu_kernel void @uniform_fneg_fabs_f64(ptr addrspace(1) %out, ptr addr
484484
; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1
485485
; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
486486
; GCN: %[[OR:[0-9]+]]:sreg_32 = S_OR_B32 killed %[[HI32]], killed %[[SREG_MASK]]
487-
; GCN: %[[OR_COPY:[0-9]+]]:sreg_32 = COPY %[[OR]]
487+
; GCN: %[[OR_COPY:[0-9]+]]:sreg_32 = COPY killed %[[OR]]
488488
; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[OR_COPY]], %subreg.sub1
489489

490490

‎llvm/test/CodeGen/ARM/fp16_fast_math.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define half @normal_fadd(half %x, half %y) {
2121
; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
2222
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
2323
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
24-
; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
24+
; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
2525
; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
2626
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
2727
;
@@ -55,7 +55,7 @@ define half @fast_fadd(half %x, half %y) {
5555
; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
5656
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
5757
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
58-
; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
58+
; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
5959
; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
6060
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
6161
;
@@ -89,7 +89,7 @@ define half @ninf_fadd(half %x, half %y) {
8989
; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
9090
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
9191
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
92-
; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
92+
; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
9393
; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
9494
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
9595
;
@@ -129,13 +129,13 @@ define half @normal_fadd_sequence(half %x, half %y, half %z) {
129129
; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
130130
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
131131
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
132-
; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
133-
; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY [[COPY6]]
132+
; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
133+
; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]]
134134
; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg
135135
; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
136136
; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
137137
; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg
138-
; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[VCVTBSH1]]
138+
; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]]
139139
; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]]
140140
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
141141
;
@@ -177,7 +177,7 @@ define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) {
177177
; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
178178
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
179179
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg
180-
; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
180+
; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
181181
; CHECK-CVT-NEXT: $r0 = COPY [[COPY6]]
182182
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
183183
;
@@ -218,13 +218,13 @@ define half @ninf_fadd_sequence(half %x, half %y, half %z) {
218218
; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
219219
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
220220
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
221-
; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
222-
; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY [[COPY6]]
221+
; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
222+
; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]]
223223
; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg
224224
; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
225225
; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
226226
; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg
227-
; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[VCVTBSH1]]
227+
; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]]
228228
; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]]
229229
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
230230
;

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