|
| 1 | +/* |
| 2 | + * STM32 Microcontroller Timer module |
| 3 | + * |
| 4 | + * Copyright (C) 2010 Andrew Hankins |
| 5 | + * |
| 6 | + * Source code based on pl011.c |
| 7 | + * |
| 8 | + * This program is free software; you can redistribute it and/or |
| 9 | + * modify it under the terms of the GNU General Public License as |
| 10 | + * published by the Free Software Foundation; either version 2 of |
| 11 | + * the License, or (at your option) any later version. |
| 12 | + * |
| 13 | + * This program is distributed in the hope that it will be useful, |
| 14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | + * GNU General Public License for more details. |
| 17 | + * |
| 18 | + * You should have received a copy of the GNU General Public License along |
| 19 | + * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 20 | + */ |
| 21 | + |
| 22 | +#include "hw/sysbus.h" |
| 23 | +#include "qemu/timer.h" |
| 24 | +#include "sysemu/sysemu.h" |
| 25 | + |
| 26 | + |
| 27 | +/* DEFINITIONS*/ |
| 28 | + |
| 29 | +/* See the README file for details on these settings. */ |
| 30 | +#define DEBUG_STM32_TIMER |
| 31 | +//#define STM32_TIMER_NO_BAUD_DELAY |
| 32 | +//#define STM32_TIMER_ENABLE_OVERRUN |
| 33 | + |
| 34 | +#ifdef DEBUG_STM32_TIMER |
| 35 | +#define DPRINTF(fmt, ...) \ |
| 36 | + do { printf("STM32_TIMER: " fmt , ## __VA_ARGS__); } while (0) |
| 37 | +#else |
| 38 | +#define DPRINTF(fmt, ...) |
| 39 | +#endif |
| 40 | + |
| 41 | +#define RTC_DR 0x00 /* Data read register */ |
| 42 | +#define RTC_MR 0x04 /* Match register */ |
| 43 | +#define RTC_LR 0x08 /* Data load register */ |
| 44 | +#define RTC_CR 0x0c /* Control register */ |
| 45 | +#define RTC_IMSC 0x10 /* Interrupt mask and set register */ |
| 46 | +#define RTC_RIS 0x14 /* Raw interrupt status register */ |
| 47 | +#define RTC_MIS 0x18 /* Masked interrupt status register */ |
| 48 | +#define RTC_ICR 0x1c /* Interrupt clear register */ |
| 49 | + |
| 50 | +typedef struct { |
| 51 | + SysBusDevice busdev; |
| 52 | + MemoryRegion iomem; |
| 53 | + QEMUTimer *timer; |
| 54 | + qemu_irq irq; |
| 55 | + |
| 56 | + /* Needed to preserve the tick_count across migration, even if the |
| 57 | + * absolute value of the rtc_clock is different on the source and |
| 58 | + * destination. |
| 59 | + */ |
| 60 | + uint32_t tick_offset_vmstate; |
| 61 | + uint32_t tick_offset; |
| 62 | + |
| 63 | + uint32_t mr; |
| 64 | + uint32_t lr; |
| 65 | + uint32_t cr; |
| 66 | + uint32_t im; |
| 67 | + uint32_t is; |
| 68 | +} pl031_state; |
| 69 | + |
| 70 | +static const unsigned char pl031_id[] = { |
| 71 | + 0x31, 0x10, 0x14, 0x00, /* Device ID */ |
| 72 | + 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ |
| 73 | +}; |
| 74 | + |
| 75 | +static void pl031_update(pl031_state *s) |
| 76 | +{ |
| 77 | + qemu_set_irq(s->irq, s->is & s->im); |
| 78 | +} |
| 79 | + |
| 80 | +static void pl031_interrupt(void * opaque) |
| 81 | +{ |
| 82 | + pl031_state *s = (pl031_state *)opaque; |
| 83 | + |
| 84 | + s->is = 1; |
| 85 | + DPRINTF("Alarm raised\n"); |
| 86 | + pl031_update(s); |
| 87 | +} |
| 88 | + |
| 89 | +static uint32_t pl031_get_count(pl031_state *s) |
| 90 | +{ |
| 91 | + int64_t now = qemu_get_clock_ns(rtc_clock); |
| 92 | + return s->tick_offset + now / get_ticks_per_sec(); |
| 93 | +} |
| 94 | + |
| 95 | +static void pl031_set_alarm(pl031_state *s) |
| 96 | +{ |
| 97 | + uint32_t ticks; |
| 98 | + |
| 99 | + /* The timer wraps around. This subtraction also wraps in the same way, |
| 100 | + and gives correct results when alarm < now_ticks. */ |
| 101 | + ticks = s->mr - pl031_get_count(s); |
| 102 | + DPRINTF("Alarm set in %ud ticks\n", ticks); |
| 103 | + if (ticks == 0) { |
| 104 | + qemu_del_timer(s->timer); |
| 105 | + pl031_interrupt(s); |
| 106 | + } else { |
| 107 | + int64_t now = qemu_get_clock_ns(rtc_clock); |
| 108 | + qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec()); |
| 109 | + } |
| 110 | +} |
| 111 | + |
| 112 | +static uint64_t pl031_read(void *opaque, hwaddr offset, |
| 113 | + unsigned size) |
| 114 | +{ |
| 115 | + pl031_state *s = (pl031_state *)opaque; |
| 116 | + |
| 117 | + if (offset >= 0xfe0 && offset < 0x1000) |
| 118 | + return pl031_id[(offset - 0xfe0) >> 2]; |
| 119 | + |
| 120 | + switch (offset) { |
| 121 | + case RTC_DR: |
| 122 | + return pl031_get_count(s); |
| 123 | + case RTC_MR: |
| 124 | + return s->mr; |
| 125 | + case RTC_IMSC: |
| 126 | + return s->im; |
| 127 | + case RTC_RIS: |
| 128 | + return s->is; |
| 129 | + case RTC_LR: |
| 130 | + return s->lr; |
| 131 | + case RTC_CR: |
| 132 | + /* RTC is permanently enabled. */ |
| 133 | + return 1; |
| 134 | + case RTC_MIS: |
| 135 | + return s->is & s->im; |
| 136 | + case RTC_ICR: |
| 137 | + qemu_log_mask(LOG_GUEST_ERROR, |
| 138 | + "pl031: read of write-only register at offset 0x%x\n", |
| 139 | + (int)offset); |
| 140 | + break; |
| 141 | + default: |
| 142 | + qemu_log_mask(LOG_GUEST_ERROR, |
| 143 | + "pl031_read: Bad offset 0x%x\n", (int)offset); |
| 144 | + break; |
| 145 | + } |
| 146 | + |
| 147 | + return 0; |
| 148 | +} |
| 149 | + |
| 150 | +static void pl031_write(void * opaque, hwaddr offset, |
| 151 | + uint64_t value, unsigned size) |
| 152 | +{ |
| 153 | + pl031_state *s = (pl031_state *)opaque; |
| 154 | + |
| 155 | + |
| 156 | + switch (offset) { |
| 157 | + case RTC_LR: |
| 158 | + s->tick_offset += value - pl031_get_count(s); |
| 159 | + pl031_set_alarm(s); |
| 160 | + break; |
| 161 | + case RTC_MR: |
| 162 | + s->mr = value; |
| 163 | + pl031_set_alarm(s); |
| 164 | + break; |
| 165 | + case RTC_IMSC: |
| 166 | + s->im = value & 1; |
| 167 | + DPRINTF("Interrupt mask %d\n", s->im); |
| 168 | + pl031_update(s); |
| 169 | + break; |
| 170 | + case RTC_ICR: |
| 171 | + /* The PL031 documentation (DDI0224B) states that the interrupt is |
| 172 | + cleared when bit 0 of the written value is set. However the |
| 173 | + arm926e documentation (DDI0287B) states that the interrupt is |
| 174 | + cleared when any value is written. */ |
| 175 | + DPRINTF("Interrupt cleared"); |
| 176 | + s->is = 0; |
| 177 | + pl031_update(s); |
| 178 | + break; |
| 179 | + case RTC_CR: |
| 180 | + /* Written value is ignored. */ |
| 181 | + break; |
| 182 | + |
| 183 | + case RTC_DR: |
| 184 | + case RTC_MIS: |
| 185 | + case RTC_RIS: |
| 186 | + qemu_log_mask(LOG_GUEST_ERROR, |
| 187 | + "pl031: write to read-only register at offset 0x%x\n", |
| 188 | + (int)offset); |
| 189 | + break; |
| 190 | + |
| 191 | + default: |
| 192 | + qemu_log_mask(LOG_GUEST_ERROR, |
| 193 | + "pl031_write: Bad offset 0x%x\n", (int)offset); |
| 194 | + break; |
| 195 | + } |
| 196 | +} |
| 197 | + |
| 198 | +static const MemoryRegionOps pl031_ops = { |
| 199 | + .read = pl031_read, |
| 200 | + .write = pl031_write, |
| 201 | + .endianness = DEVICE_NATIVE_ENDIAN, |
| 202 | +}; |
| 203 | + |
| 204 | +static int pl031_init(SysBusDevice *dev) |
| 205 | +{ |
| 206 | + pl031_state *s = FROM_SYSBUS(pl031_state, dev); |
| 207 | + struct tm tm; |
| 208 | + |
| 209 | + memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000); |
| 210 | + sysbus_init_mmio(dev, &s->iomem); |
| 211 | + |
| 212 | + sysbus_init_irq(dev, &s->irq); |
| 213 | + qemu_get_timedate(&tm, 0); |
| 214 | + s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec(); |
| 215 | + |
| 216 | + s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s); |
| 217 | + return 0; |
| 218 | +} |
| 219 | + |
| 220 | +static void pl031_pre_save(void *opaque) |
| 221 | +{ |
| 222 | + pl031_state *s = opaque; |
| 223 | + |
| 224 | + /* tick_offset is base_time - rtc_clock base time. Instead, we want to |
| 225 | + * store the base time relative to the vm_clock for backwards-compatibility. */ |
| 226 | + int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); |
| 227 | + s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec(); |
| 228 | +} |
| 229 | + |
| 230 | +static int pl031_post_load(void *opaque, int version_id) |
| 231 | +{ |
| 232 | + pl031_state *s = opaque; |
| 233 | + |
| 234 | + int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); |
| 235 | + s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec(); |
| 236 | + pl031_set_alarm(s); |
| 237 | + return 0; |
| 238 | +} |
| 239 | + |
| 240 | +static const VMStateDescription vmstate_pl031 = { |
| 241 | + .name = "pl031", |
| 242 | + .version_id = 1, |
| 243 | + .minimum_version_id = 1, |
| 244 | + .pre_save = pl031_pre_save, |
| 245 | + .post_load = pl031_post_load, |
| 246 | + .fields = (VMStateField[]) { |
| 247 | + VMSTATE_UINT32(tick_offset_vmstate, pl031_state), |
| 248 | + VMSTATE_UINT32(mr, pl031_state), |
| 249 | + VMSTATE_UINT32(lr, pl031_state), |
| 250 | + VMSTATE_UINT32(cr, pl031_state), |
| 251 | + VMSTATE_UINT32(im, pl031_state), |
| 252 | + VMSTATE_UINT32(is, pl031_state), |
| 253 | + VMSTATE_END_OF_LIST() |
| 254 | + } |
| 255 | +}; |
| 256 | + |
| 257 | +static void pl031_class_init(ObjectClass *klass, void *data) |
| 258 | +{ |
| 259 | + DeviceClass *dc = DEVICE_CLASS(klass); |
| 260 | + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 261 | + |
| 262 | + k->init = pl031_init; |
| 263 | + dc->no_user = 1; |
| 264 | + dc->vmsd = &vmstate_pl031; |
| 265 | +} |
| 266 | + |
| 267 | +static const TypeInfo pl031_info = { |
| 268 | + .name = "pl031", |
| 269 | + .parent = TYPE_SYS_BUS_DEVICE, |
| 270 | + .instance_size = sizeof(pl031_state), |
| 271 | + .class_init = pl031_class_init, |
| 272 | +}; |
| 273 | + |
| 274 | +static void pl031_register_types(void) |
| 275 | +{ |
| 276 | + type_register_static(&pl031_info); |
| 277 | +} |
| 278 | + |
| 279 | +type_init(pl031_register_types) |
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