Skip to content

Commit ccee91a

Browse files
committed
Add unit tests for timer (commented out)
I was not able to get the timer unit test to work. When the timer is enabled, it does not appear to actually count. I believe I am initializing it properly - is it possible that the QEMU timer routines behave differently during unit tests? The timer unit tests are not absolutely necessary, so I am adding them but leaving them commented out.
1 parent 8dc1c5a commit ccee91a

File tree

1 file changed

+25
-3
lines changed

1 file changed

+25
-3
lines changed

tests/test-stm32.c

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
#define RCC_BASE_ADDR 0x40021000
2626
#define AFIO_BASE_ADDR 0x40010000
2727
#define EXTI_BASE_ADDR 0x40010400
28+
#define TIM2_BASE_ADDR 0x40000000
2829
#define UART2_BASE_ADDR 0x40004400
2930

3031
const char *dummy_kernel_path = "tests/test-stm32-dummy-kernel.bin";
@@ -271,9 +272,30 @@ static void test_uart(void)
271272
// so that we did not need to add test logic into the UART itself.....
272273
}
273274

274-
static void test_timer(void)
275+
/*static void test_timer(void)
275276
{
276-
}
277+
uint32_t status;
278+
279+
writel(TIM2_BASE_ADDR + 0x00, 0x0); // Disable Timer
280+
writel(TIM2_BASE_ADDR + 0x0C, 0x1); // Enable Timer Interrupt
281+
writel(TIM2_BASE_ADDR + 0x28, 8000); // PSC - Set Prescale value
282+
writel(TIM2_BASE_ADDR + 0x2C, 0x2000); // ARR - Set Auto-Reload count
283+
//writel(TIM2_BASE_ADDR + 0x14, 0x1); // EGR - Reset count
284+
285+
g_assert_cmpint(get_irq_for_gpio(nvic_in_id, 28), ==, 0);
286+
g_assert_cmpint(readl(TIM2_BASE_ADDR + 0x10), ==, 0);
287+
writel(TIM2_BASE_ADDR + 0x00, 0x1); // Enable Timer
288+
289+
//TODO: Add a timeout to avoid infinite loop
290+
do {
291+
//readl(TIM2_BASE_ADDR + 0x24);
292+
status = readl(TIM2_BASE_ADDR + 0x10);
293+
} while(status == 0); // Loop until transmit complete
294+
g_assert_cmpint(status, ==, 1);
295+
g_assert_cmpint(get_irq_for_gpio(nvic_in_id, 28), ==, 1);
296+
297+
writel(TIM2_BASE_ADDR + 0x00, 0x0); // Disable Timer
298+
}*/
277299

278300
int main(int argc, char **argv)
279301
{
@@ -301,7 +323,7 @@ int main(int argc, char **argv)
301323
qtest_add_func("/stm32/gpio/write", test_gpio_write);
302324
qtest_add_func("/stm32/gpio/interrupt", test_gpio_interrupt);
303325
qtest_add_func("/stm32/uart", test_uart);
304-
qtest_add_func("/stm32/timer", test_timer);
326+
// qtest_add_func("/stm32/timer", test_timer);
305327

306328
ret = g_test_run();
307329

0 commit comments

Comments
 (0)