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alanminkoalanminko
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Reading the printout.
1 parent 1b7912a commit 169e288

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2 files changed

+126
-16
lines changed

2 files changed

+126
-16
lines changed

‎src/base/wlc/wlcCom.c‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -321,11 +321,12 @@ int Abc_CommandWriteWlc( Abc_Frame_t * pAbc, int argc, char ** argv )
321321
******************************************************************************/
322322
int Abc_CommandGenWlc( Abc_Frame_t * pAbc, int argc, char ** argv )
323323
{
324-
extern int miniver_translate(const char *input, char *out, size_t cap);
324+
extern int miniver_translate(const char *input, char *out, size_t cap, int fShort);
325325
char * pFileName = NULL;
326+
int fShort = 1;
326327
int c, fVerbose = 0;
327328
Extra_UtilGetoptReset();
328-
while ( ( c = Extra_UtilGetopt( argc, argv, "Fvh" ) ) != EOF )
329+
while ( ( c = Extra_UtilGetopt( argc, argv, "Fsvh" ) ) != EOF )
329330
{
330331
switch ( c )
331332
{
@@ -338,6 +339,9 @@ int Abc_CommandGenWlc( Abc_Frame_t * pAbc, int argc, char ** argv )
338339
pFileName = argv[globalUtilOptind];
339340
globalUtilOptind++;
340341
break;
342+
case 's':
343+
fShort ^= 1;
344+
break;
341345
case 'v':
342346
fVerbose ^= 1;
343347
break;
@@ -355,7 +359,7 @@ int Abc_CommandGenWlc( Abc_Frame_t * pAbc, int argc, char ** argv )
355359
int Size = 10000;
356360
char * pStr = argv[globalUtilOptind];
357361
char * pOutStr = ABC_CALLOC( char, Size+1 );
358-
int RetValue = miniver_translate( pStr, pOutStr, Size );
362+
int RetValue = miniver_translate( pStr, pOutStr, Size, fShort );
359363
if ( !RetValue ) {
360364
if ( fVerbose )
361365
printf( "Entered Verilog design:\n%s", pOutStr );
@@ -387,10 +391,11 @@ int Abc_CommandGenWlc( Abc_Frame_t * pAbc, int argc, char ** argv )
387391
}
388392
return 0;
389393
usage:
390-
Abc_Print( -2, "\nusage: %%gen [-F file] [-vh] \"<mini_verilog_string>\"\n" );
394+
Abc_Print( -2, "\nusage: %%gen [-F file] [-svh] \"<mini_verilog_string>\"\n" );
391395
Abc_Print( -2, "\t generates the design from a mini-Verilog string\n" );
392396
Abc_Print( -2, "\t-F file : optional file name to save the design in standard Verilog [default = unused]\n" );
393-
Abc_Print( -2, "\t-v (if a file name is provided, Verilog is dumped into a file and not read into ABC)\n" );
397+
Abc_Print( -2, "\t (if a file name is provided, Verilog is dumped into a file and not read into ABC)\n" );
398+
Abc_Print( -2, "\t-s : prints Verilog using a shorter format [default = %s]\n", fShort ? "yes": "no" );
394399
Abc_Print( -2, "\t-v : toggle printing verbose information [default = %s]\n", fVerbose? "yes": "no" );
395400
Abc_Print( -2, "\t-h : print the command usage\n");
396401
Abc_Print( -2, "\n" );
@@ -2129,4 +2134,3 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
21292134

21302135

21312136
ABC_NAMESPACE_IMPL_END
2132-

‎src/misc/util/utilMiniver.c‎

Lines changed: 116 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,67 @@ static int print_decl_to_buf(char **p, size_t *left, const char *kw, decl_t *arr
179179
return 0;
180180
}
181181

182+
static int print_decl_single(char **p, size_t *left, const char *kw, const decl_t *decl) {
183+
if (out_cat(p, left, " %s ", kw)) return 1;
184+
if (decl->is_signed) {
185+
if (out_cat(p, left, "signed ")) return 1;
186+
}
187+
if (decl->width > 1) {
188+
if (out_cat(p, left, "[%d:0] ", decl->width - 1)) return 1;
189+
}
190+
if (out_cat(p, left, "%s;\n", decl->name)) return 1;
191+
return 0;
192+
}
193+
194+
static int print_decl_with_assign(char **p, size_t *left, const char *kw, const decl_t *decl, const char *rhs) {
195+
if (out_cat(p, left, " %s ", kw)) return 1;
196+
if (decl->is_signed) {
197+
if (out_cat(p, left, "signed ")) return 1;
198+
}
199+
if (decl->width > 1) {
200+
if (out_cat(p, left, "[%d:0] ", decl->width - 1)) return 1;
201+
}
202+
if (out_cat(p, left, "%s = %s;\n", decl->name, rhs)) return 1;
203+
return 0;
204+
}
205+
206+
static int print_inputs_short(char **p, size_t *left, decl_t *arr, int n) {
207+
for (int i = 0; i < n; ) {
208+
int w = arr[i].width;
209+
int sg = arr[i].is_signed;
210+
if (out_cat(p, left, " input ")) return 1;
211+
if (sg) {
212+
if (out_cat(p, left, "signed ")) return 1;
213+
}
214+
if (w > 1) {
215+
if (out_cat(p, left, "[%d:0] ", w - 1)) return 1;
216+
}
217+
int j = i;
218+
while (j < n && arr[j].width == w && arr[j].is_signed == sg) {
219+
if (out_cat(p, left, "%s%s", j == i ? "" : ", ", arr[j].name)) return 1;
220+
++j;
221+
}
222+
if (out_cat(p, left, ";\n")) return 1;
223+
i = j;
224+
}
225+
return 0;
226+
}
227+
228+
static decl_t *find_decl_by_name(decl_t *arr, int n, const char *name) {
229+
for (int i = 0; i < n; ++i) {
230+
if (!strcmp(arr[i].name, name))
231+
return &arr[i];
232+
}
233+
return NULL;
234+
}
235+
236+
static int has_assignment(const mv_ctx *ctx, const char *name) {
237+
for (int i = 0; i < ctx->na; ++i)
238+
if (!strcmp(ctx->assigns[i].lhs, name))
239+
return 1;
240+
return 0;
241+
}
242+
182243
// Add spaces around every alphanumeric/underscore sequence for readability.
183244
// Example: "a*b+16'b0" -> " a * b + 16 ' b0 "
184245
static void format_rhs_readable(const char *in, char *out, size_t cap) {
@@ -206,6 +267,20 @@ static void format_rhs_readable(const char *in, char *out, size_t cap) {
206267
if (o < cap) out[o] = 0; else if (cap) out[cap-1] = 0;
207268
}
208269

270+
static void trim_spaces(char *s) {
271+
if (!s) return;
272+
char *start = s;
273+
while (*start && isspace((unsigned char)*start))
274+
++start;
275+
char *end = start + strlen(start);
276+
while (end > start && isspace((unsigned char)*(end - 1)))
277+
--end;
278+
size_t len = (size_t)(end - start);
279+
if (start != s)
280+
memmove(s, start, len);
281+
s[len] = 0;
282+
}
283+
209284
// -----------------------------------------------------------------------------
210285
// Parsing helpers that quote offending clauses
211286
// -----------------------------------------------------------------------------
@@ -380,7 +455,7 @@ lhs_done:;
380455
// Translate a raw mini-Verilog string 'input' into standard Verilog.
381456
// The function strips whitespace internally, parses, and writes into 'out' (cap bytes).
382457
// Returns 0 on success, 1 on error. Errors are printed (no exit()).
383-
int miniver_translate(const char *input, char *out, size_t cap) {
458+
int miniver_translate(const char *input, char *out, size_t cap, int fShort) {
384459
if (!input || !out || cap == 0) {
385460
printf("Invalid arguments.\n");
386461
return 1;
@@ -458,15 +533,47 @@ int miniver_translate(const char *input, char *out, size_t cap) {
458533
free(ctx); return 1;
459534
}
460535

461-
if (print_decl_to_buf(&p, &left, "input", ctx->inputs, ctx->ni)) { free(ctx); return 1; }
462-
if (print_decl_to_buf(&p, &left, "output", ctx->outputs, ctx->no)) { free(ctx); return 1; }
463-
if (print_decl_to_buf(&p, &left, "wire", ctx->wires, ctx->nw)) { free(ctx); return 1; }
536+
if (!fShort) {
537+
if (print_decl_to_buf(&p, &left, "input", ctx->inputs, ctx->ni)) { free(ctx); return 1; }
538+
if (print_decl_to_buf(&p, &left, "output", ctx->outputs, ctx->no)) { free(ctx); return 1; }
539+
if (print_decl_to_buf(&p, &left, "wire", ctx->wires, ctx->nw)) { free(ctx); return 1; }
464540

465541
for (int i = 0; i < ctx->na; ++i) {
466-
char rhs_sp[8192];
467-
format_rhs_readable(ctx->assigns[i].rhs, rhs_sp, sizeof(rhs_sp));
468-
if (out_cat(&p, &left, " assign %s = %s;\n", ctx->assigns[i].lhs, rhs_sp)) {
469-
free(ctx); return 1;
542+
char rhs_sp[8192];
543+
format_rhs_readable(ctx->assigns[i].rhs, rhs_sp, sizeof(rhs_sp));
544+
if (out_cat(&p, &left, " assign %s = %s;\n", ctx->assigns[i].lhs, rhs_sp)) {
545+
free(ctx); return 1;
546+
}
547+
}
548+
} else {
549+
if (print_inputs_short(&p, &left, ctx->inputs, ctx->ni)) { free(ctx); return 1; }
550+
for (int i = 0; i < ctx->nw; ++i) {
551+
if (has_assignment(ctx, ctx->wires[i].name))
552+
continue;
553+
if (print_decl_single(&p, &left, "wire", &ctx->wires[i])) {
554+
free(ctx); return 1;
555+
}
556+
}
557+
for (int i = 0; i < ctx->na; ++i) {
558+
char rhs_sp[8192];
559+
format_rhs_readable(ctx->assigns[i].rhs, rhs_sp, sizeof(rhs_sp));
560+
trim_spaces(rhs_sp);
561+
const char *kw = "wire";
562+
decl_t *decl = find_decl_by_name(ctx->outputs, ctx->no, ctx->assigns[i].lhs);
563+
if (decl) {
564+
kw = "output";
565+
} else {
566+
decl = find_decl_by_name(ctx->wires, ctx->nw, ctx->assigns[i].lhs);
567+
}
568+
if (decl) {
569+
if (print_decl_with_assign(&p, &left, kw, decl, rhs_sp)) {
570+
free(ctx); return 1;
571+
}
572+
} else {
573+
if (out_cat(&p, &left, " assign %s = %s;\n", ctx->assigns[i].lhs, rhs_sp)) {
574+
free(ctx); return 1;
575+
}
576+
}
470577
}
471578
}
472579
if (out_cat(&p, &left, "endmodule\n")) {
@@ -506,7 +613,7 @@ int main(int argc, char **argv) {
506613
}
507614

508615
char out[10240];
509-
int rc = miniver_translate(in, out, sizeof(out));
616+
int rc = miniver_translate(in, out, sizeof(out), 0);
510617
if (!rc) {
511618
printf("%s", out);
512619
}
@@ -520,4 +627,3 @@ int main(int argc, char **argv) {
520627

521628

522629
ABC_NAMESPACE_IMPL_END
523-

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