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Force c22/c45 mode per read/write transaction..
Signed-off-by: Bevan Weiss <[email protected]>
1 parent 4134dc4 commit 1978189

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1 file changed

+33
-11
lines changed
  • target/linux/realtek/files-6.12/drivers/net/ethernet

1 file changed

+33
-11
lines changed

target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c

Lines changed: 33 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1650,6 +1650,7 @@ struct rtmdio_bus_priv {
16501650
bool smi_bus_isc45[RTMDIO_MAX_SMI_BUS];
16511651
bool phy_is_internal[RTMDIO_MAX_PORT];
16521652
phy_interface_t interfaces[RTMDIO_MAX_PORT];
1653+
void (*set_mdio_bus_c45mode)(int smi_bus, bool c45mode);
16531654
int (*read_mmd_phy)(u32 port, u32 addr, u32 reg, u32 *val);
16541655
int (*write_mmd_phy)(u32 port, u32 addr, u32 reg, u32 val);
16551656
int (*read_phy)(u32 port, u32 page, u32 reg, u32 *val);
@@ -2377,6 +2378,14 @@ static int rtmdio_930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
23772378
return err;
23782379
}
23792380

2381+
static void rtmdio_930x_set_mdio_bus_c45mode(int smi_bus, bool c45)
2382+
{
2383+
if (c45)
2384+
sw_w32_mask(0, BIT(smi_bus + 16), RTL930X_SMI_GLB_CTRL);
2385+
else
2386+
sw_w32_mask(BIT(smi_bus + 16), 0, RTL930X_SMI_GLB_CTRL);
2387+
}
2388+
23802389
/* Read an mmd register of the PHY */
23812390
static int rtmdio_930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
23822391
{
@@ -2552,6 +2561,14 @@ static int rtmdio_931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
25522561
return 0;
25532562
}
25542563

2564+
static void rtmdio_931x_set_mdio_bus_c45mode(int smi_bus, bool c45)
2565+
{
2566+
if(c45)
2567+
sw_w32_mask(0, 0x2 << (smi_bus * 2), RTL931X_SMI_GLB_CTRL0);
2568+
else
2569+
sw_w32_mask(0x2 << (smi_bus * 2), 0, RTL931X_SMI_GLB_CTRL0);
2570+
}
2571+
25552572
/* Read an mmd register of the PHY */
25562573
static int rtmdio_931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
25572574
{
@@ -2642,6 +2659,8 @@ static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum
26422659
if (addr >= priv->cpu_port)
26432660
return -ENODEV;
26442661

2662+
if(priv->set_mdio_bus_c45mode)
2663+
(*priv->set_mdio_bus_c45mode)(priv->smi_bus[addr], true);
26452664
err = (*priv->read_mmd_phy)(addr, devnum, regnum, &val);
26462665
pr_debug("rd_MMD(adr=%d, dev=%d, reg=%d) = %d, err = %d\n",
26472666
addr, devnum, regnum, val, err);
@@ -2715,10 +2734,13 @@ static int rtmdio_read(struct mii_bus *bus, int addr, int regnum)
27152734
return priv->page[addr];
27162735

27172736
priv->raw[addr] = (priv->page[addr] == priv->rawpage);
2718-
if ((priv->phy_is_internal[addr]) && (priv->sds_id[addr] >= 0))
2737+
if ((priv->phy_is_internal[addr]) && (priv->sds_id[addr] >= 0)) {
27192738
return rtmdio_read_sds_phy(priv, priv->sds_id[addr],
27202739
priv->page[addr], regnum);
2740+
}
27212741

2742+
if(priv->set_mdio_bus_c45mode)
2743+
(*priv->set_mdio_bus_c45mode)(priv->smi_bus[addr], false);
27222744
err = (*priv->read_phy)(addr, priv->page[addr], regnum, &val);
27232745
pr_debug("rd_PHY(adr=%d, pag=%d, reg=%d) = %d, err = %d\n",
27242746
addr, priv->page[addr], regnum, val, err);
@@ -2745,6 +2767,8 @@ static int rtmdio_93xx_read(struct mii_bus *bus, int addr, int regnum)
27452767
priv->page[addr], regnum);
27462768
}
27472769

2770+
if(priv->set_mdio_bus_c45mode)
2771+
(*priv->set_mdio_bus_c45mode)(priv->smi_bus[addr], false);
27482772
err = (*priv->read_phy)(addr, priv->page[addr], regnum, &val);
27492773
pr_debug("rd_PHY(adr=%d, pag=%d, reg=%d) = %d, err = %d\n",
27502774
addr, priv->page[addr], regnum, val, err);
@@ -2762,6 +2786,8 @@ static int rtmdio_write_c45(struct mii_bus *bus, int addr, int devnum, int regnu
27622786
if (addr >= priv->cpu_port)
27632787
return -ENODEV;
27642788

2789+
if(priv->set_mdio_bus_c45mode)
2790+
(*priv->set_mdio_bus_c45mode)(priv->smi_bus[addr], true);
27652791
err = (*priv->write_mmd_phy)(addr, devnum, regnum, val);
27662792
pr_debug("wr_MMD(adr=%d, dev=%d, reg=%d, val=%d) err = %d\n",
27672793
addr, devnum, regnum, val, err);
@@ -2795,6 +2821,8 @@ static int rtmdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
27952821
return rtmdio_write_sds_phy(priv, priv->sds_id[addr],
27962822
priv->page[addr], regnum, val);
27972823

2824+
if(priv->set_mdio_bus_c45mode)
2825+
(*priv->set_mdio_bus_c45mode)(priv->smi_bus[addr], false);
27982826
err = (*priv->write_phy)(addr, page, regnum, val);
27992827
pr_debug("wr_PHY(adr=%d, pag=%d, reg=%d, val=%d) err = %d\n",
28002828
addr, page, regnum, val, err);
@@ -2833,6 +2861,8 @@ static int rtmdio_93xx_write(struct mii_bus *bus, int addr, int regnum, u16 val)
28332861
page, regnum, val);
28342862
}
28352863

2864+
if(priv->set_mdio_bus_c45mode)
2865+
(*priv->set_mdio_bus_c45mode)(priv->smi_bus[addr], false);
28362866
err = (*priv->write_phy)(addr, page, regnum, val);
28372867
pr_debug("wr_PHY(adr=%d, pag=%d, reg=%d, val=%d) err = %d\n",
28382868
addr, page, regnum, val, err);
@@ -2908,11 +2938,6 @@ static int rtmdio_930x_reset(struct mii_bus *bus)
29082938
/* Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+) */
29092939
sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
29102940

2911-
/* Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus */
2912-
for (int i = 0; i < RTMDIO_MAX_SMI_BUS; i++)
2913-
if (priv->smi_bus_isc45[i])
2914-
c45_mask |= BIT(i + 16);
2915-
29162941
pr_info("c45_mask: %08x\n", c45_mask);
29172942
sw_w32_mask(GENMASK(19, 16), c45_mask, RTL930X_SMI_GLB_CTRL);
29182943

@@ -3017,9 +3042,6 @@ static int rtmdio_931x_reset(struct mii_bus *bus)
30173042
pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
30183043
pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
30193044
for (int i = 0; i < RTMDIO_MAX_SMI_BUS; i++) {
3020-
/* bus is polled in c45 */
3021-
if (priv->smi_bus_isc45[i])
3022-
c45_mask |= 0x2 << (i * 2); /* Std. C45, non-standard is 0x3 */
30233045
/* Enable bus access via MDC */
30243046
if (mdc_on[i])
30253047
sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
@@ -3145,6 +3167,7 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
31453167
priv->mii_bus->reset = rtmdio_930x_reset;
31463168
bus_priv->read_sds_phy = rtmdio_930x_read_sds_phy;
31473169
bus_priv->write_sds_phy = rtmdio_930x_write_sds_phy;
3170+
bus_priv->set_mdio_bus_c45mode = rtmdio_930x_set_mdio_bus_c45mode;
31483171
bus_priv->read_mmd_phy = rtmdio_930x_read_mmd_phy;
31493172
bus_priv->write_mmd_phy = rtmdio_930x_write_mmd_phy;
31503173
bus_priv->read_phy = rtmdio_930x_read_phy;
@@ -3157,6 +3180,7 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
31573180
priv->mii_bus->read = rtmdio_93xx_read;
31583181
priv->mii_bus->write = rtmdio_93xx_write;
31593182
priv->mii_bus->reset = rtmdio_931x_reset;
3183+
bus_priv->set_mdio_bus_c45mode = rtmdio_931x_set_mdio_bus_c45mode;
31603184
bus_priv->read_mmd_phy = rtmdio_931x_read_mmd_phy;
31613185
bus_priv->write_mmd_phy = rtmdio_931x_write_mmd_phy;
31623186
bus_priv->read_phy = rtmdio_931x_read_phy;
@@ -3203,8 +3227,6 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
32033227

32043228
if (bus_priv->phy_is_internal[pn] && bus_priv->sds_id[pn] >= 0)
32053229
bus_priv->smi_bus[pn]= -1;
3206-
else if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
3207-
bus_priv->smi_bus_isc45[bus_priv->smi_bus[pn]] = true;
32083230
}
32093231

32103232
dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");

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