Add support for Hasivo s1100wp-8gt-se

Signed-off-by: Bevan Weiss <bevan.weiss@gmail.com>

Author: bevanweiss

target/linux/realtek/dts/rtl9303_hasivo_s1100wp-8gt-se.dts

@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "hasivo,s1100wp-8gt-se";
+	model = "Hasivo S1100WP-8GT-SE";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>; /* 256 MiB */
+	};
+
+	aliases {
+		led-boot = &led_sys;
+		led-failsafe = &led_sys;
+		led-running = &led_sys;
+		led-upgrade = &led_sys;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		button-reset {
+			label = "reset";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_disable_sys_led>;
+
+		led_sys: led-0 {
+			label = "green:system";
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	led_set: led_set {
+		compatible = "realtek,rtl9300-leds";
+		realtek,rtl93xx-led-sync;
+
+		led_set0 = <
+		(	// GREEN LEFT RJ45
+			RTL93XX_LED_SET_1G |
+			RTL93XX_LED_SET_2P5G |
+			RTL93XX_LED_SET_LINK
+		)
+		(	// ORANGE LEFT RJ45
+			RTL93XX_LED_SET_10M |
+			RTL93XX_LED_SET_100M |
+			RTL93XX_LED_SET_2P5G |
+			RTL93XX_LED_SET_LINK
+		)
+		(	// GREEN RIGHT RJ45
+			RTL93XX_LED_SET_10M |
+			RTL93XX_LED_SET_100M |
+			RTL93XX_LED_SET_1G |
+			RTL93XX_LED_SET_2P5G |
+			RTL93XX_LED_SET_ACT
+		)
+		>;
+	};
+
+	i2c_scl23_sda22 {
+		compatible = "i2c-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		status = "okay";
+
+		clock-frequency = <100000>;
+
+		pse-hs104_0@0x0d {
+			compatible = "hasivo,hs104";
+			reg = <0x0d>;
+
+		};
+
+		pse-hs104_1@0x15 {
+			compatible = "hasivo,hs104";
+			reg = <0x15>;
+		};
+
+		stc8@4d {
+			compatible = "hasivo,stc8-mfd";
+			reg = <0x4d>;
+
+			led_lan1_poe {
+				compatible = "register-bit-led";
+				reg = <0x01>;
+				mask = <0x08>;
+				trigger = "pse-hs104_0@0x0d:port0delivering";
+			};
+
+			led_lan2_poe {
+				compatible = "register-bit-led";
+				reg = <0x01>;
+				mask = <0x04>;
+				trigger = "pse-hs104_0@0x0d:port1delivering";
+			};
+
+			led_lan3_poe {
+				compatible = "register-bit-led";
+				reg = <0x01>;
+				mask = <0x02>;
+				trigger = "pse-hs104_0@0x0d:port2delivering";
+			};
+
+			led_lan4_poe {
+				compatible = "register-bit-led";
+				reg = <0x01>;
+				mask = <0x01>;
+				trigger = "pse-hs104_0@0x0d:port3delivering";
+			};
+
+			led_lan5_poe {
+				compatible = "register-bit-led";
+				reg = <0x02>;
+				mask = <0x08>;
+				trigger = "pse-hs104_1:port0delivering";
+			};
+
+			led_lan6_poe {
+				compatible = "register-bit-led";
+				reg = <0x02>;
+				mask = <0x04>;
+				trigger = "pse-hs104_1:port1delivering";
+			};
+
+			led_lan7_poe {
+				compatible = "register-bit-led";
+				reg = <0x02>;
+				mask = <0x02>;
+				trigger = "pse-hs104_1:port2delivering";
+			};
+
+			led_lan8_poe {
+				compatible = "register-bit-led";
+				reg = <0x02>;
+				mask = <0x01>;
+				trigger = "pse-hs104_1:port3delivering";
+			};
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "fudan,fm25q128", "winbond,w25q256jv", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		/*spi-tx-width = <4>;*/
+		/*spi-rx-width = <4>;*/
+		/*spi-max-frequency = <104000000>;*/
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* stock is LOADER */
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0000000 0x00e0000>;
+				read-only;
+			};
+
+			/* stock is BDINFO */
+			partition@e0000 {
+				label = "u-boot-env";
+				reg = <0x00e0000 0x0010000>;
+			};
+
+			/* stock is SYSINFO */
+			partition@f0000 {
+				label = "u-boot-env2";
+				reg = <0x00f0000 0x0010000>;
+				read-only;
+			};
+
+			/* stock is JFFS2_CFG */
+			partition@100000 {
+				label = "jffs";
+				reg = <0x0100000 0x0100000>;
+			};
+
+			/* stock is JFFS2_LOG */
+			partition@200000 {
+				label = "jffs2";
+				reg = <0x0200000 0x0100000>;
+			};
+
+			/* stock is RUNTIME */
+			partition@300000 {
+				compatible = "openwrt,uimage", "denx,uimage";
+				label = "firmware";
+				reg = <0x0300000 0x0c00000>;
+				openwrt,ih-magic = <0x93030000>;
+			};
+
+			/* stock is OEMINFO */
+			partition@f00000 {
+				label = "oeminfo";
+				reg = <0x0f00000 0x0100000>;
+				read-only;
+			};
+		};
+	};
+};
+
+/*
+&crypto0 {
+	status = "disabled";
+};
+*/
+
+&mdio_bus0 {
+	/* External RTL8221B PHY */
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <0 1>;
+	};
+
+	/* External RTL8221B PHY */
+	phy8: ethernet-phy@8 {
+		reg = <8>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <0 2>;
+	};
+
+	/* External RTL8221B PHY */
+	phy16: ethernet-phy@16 {
+		reg = <16>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <0 3>;
+	};
+
+	/* External RTL8221B PHY */
+	phy20: ethernet-phy@20 {
+		reg = <20>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <0 4>;
+	};
+
+	/* External RTL8221B PHY */
+	phy24: ethernet-phy@24 {
+		reg = <24>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <1 1>;
+	};
+
+	/* External RTL8221B PHY */
+	phy25: ethernet-phy@25 {
+		reg = <25>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <1 2>;
+	};
+
+	/* External RTL8221B PHY */
+	phy26: ethernet-phy@26 {
+		reg = <26>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <1 3>;
+	};
+
+	/* External RTL8221B PHY */
+	phy27: ethernet-phy@27 {
+		reg = <27>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		rtl9300,smi-address = <1 4>;
+	};
+};
+
+&switch0 {
+	pinctrl-names = "default";
+    pinctrl-0 = <&pinmux_enable_led_sync>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy0>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@8 {
+			reg = <8>;
+			label = "lan2";
+			pcs-handle = <&serdes3>;
+			phy-handle = <&phy8>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@16 {
+			reg = <16>;
+			label = "lan3";
+			pcs-handle = <&serdes4>;
+			phy-handle = <&phy16>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@20 {
+			reg = <20>;
+			label = "lan4";
+			pcs-handle = <&serdes5>;
+			phy-handle = <&phy20>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@24 {
+			reg = <24>;
+			label = "lan5";
+			pcs-handle = <&serdes6>;
+			phy-handle = <&phy24>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@25 {
+			reg = <25>;
+			label = "lan6";
+			pcs-handle = <&serdes7>;
+			phy-handle = <&phy25>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@26 {
+			reg = <26>;
+			label = "lan7";
+			pcs-handle = <&serdes8>;
+			phy-handle = <&phy26>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		port@27 {
+			reg = <27>;
+			label = "lan8";
+			pcs-handle = <&serdes9>;
+			phy-handle = <&phy27>;
+			phy-mode = "2500base-x";
+			led-set = <0>;
+		};
+
+		/* Internal SoC */
+		port@28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+
+			fixed-link {
+				speed = <10000>;
+				full-duplex;
+			};
+		};
+	};
+};