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Add support for Hasivo s1100wp-8gt-se (excl PoE)
Signed-off-by: Bevan Weiss <[email protected]>
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‎target/linux/realtek/dts/rtl9303_hasivo_s1100wp-8gt-se.dts‎

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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "hasivo,s1100wp-8gt-se";
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model = "Hasivo S1100WP-8GT-SE";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MiB */
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};
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_sys: led-0 {
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label = "green:system";
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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realtek,rtl93xx-led-sync;
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led_set0 = <
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( // GREEN LEFT RJ45
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RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK
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)
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( // ORANGE LEFT RJ45
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RTL93XX_LED_SET_10M |
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RTL93XX_LED_SET_100M |
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RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK
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)
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( // GREEN RIGHT RJ45
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RTL93XX_LED_SET_10M |
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RTL93XX_LED_SET_100M |
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RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_ACT
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)
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>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "fudan,fm25q128", "winbond,w25q256jv", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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/*spi-tx-width = <4>;*/
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/*spi-rx-width = <4>;*/
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/*spi-max-frequency = <104000000>;*/
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* stock is LOADER */
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x00e0000>;
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read-only;
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};
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/* stock is BDINFO */
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partition@e0000 {
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label = "u-boot-env";
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reg = <0x00e0000 0x0010000>;
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};
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/* stock is SYSINFO */
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0x00f0000 0x0010000>;
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read-only;
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};
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/* stock is JFFS2_CFG */
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partition@100000 {
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label = "jffs";
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reg = <0x0100000 0x0100000>;
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};
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/* stock is JFFS2_LOG */
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partition@200000 {
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label = "jffs2";
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reg = <0x0200000 0x0100000>;
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};
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/* stock is RUNTIME */
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partition@300000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x0300000 0x0c00000>;
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openwrt,ih-magic = <0x93030000>;
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};
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/* stock is OEMINFO */
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partition@f00000 {
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label = "oeminfo";
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reg = <0x0f00000 0x0100000>;
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read-only;
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};
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};
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};
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};
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/*
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&crypto0 {
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status = "disabled";
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};
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*/
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&mdio_bus0 {
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/* External RTL8221B PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 1>;
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};
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/* External RTL8221B PHY */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 2>;
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};
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/* External RTL8221B PHY */
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phy16: ethernet-phy@16 {
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reg = <16>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 3>;
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};
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/* External RTL8221B PHY */
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phy20: ethernet-phy@20 {
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reg = <20>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 4>;
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};
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/* External RTL8221B PHY */
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <1 1>;
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};
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/* External RTL8221B PHY */
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <1 2>;
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};
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/* External RTL8221B PHY */
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phy26: ethernet-phy@26 {
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reg = <26>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <1 3>;
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};
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/* External RTL8221B PHY */
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phy27: ethernet-phy@27 {
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reg = <27>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <1 4>;
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};
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};
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&switch0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_enable_led_sync>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy0>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@8 {
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reg = <8>;
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label = "lan2";
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pcs-handle = <&serdes3>;
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phy-handle = <&phy8>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@16 {
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reg = <16>;
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label = "lan3";
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pcs-handle = <&serdes4>;
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phy-handle = <&phy16>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@20 {
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reg = <20>;
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label = "lan4";
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pcs-handle = <&serdes5>;
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phy-handle = <&phy20>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@24 {
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reg = <24>;
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label = "lan5";
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pcs-handle = <&serdes6>;
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phy-handle = <&phy24>;
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phy-mode = "2500base-x";
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led-set = <0>;
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};
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port@25 {
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reg = <25>;
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label = "lan6";
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pcs-handle = <&serdes7>;
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phy-handle = <&phy25>;
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phy-mode = "2500base-x";
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led-set = <0>;
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};
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port@26 {
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reg = <26>;
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label = "lan7";
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pcs-handle = <&serdes8>;
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phy-handle = <&phy26>;
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phy-mode = "2500base-x";
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led-set = <0>;
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};
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port@27 {
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reg = <27>;
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label = "lan8";
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pcs-handle = <&serdes9>;
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phy-handle = <&phy27>;
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phy-mode = "2500base-x";
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led-set = <0>;
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};
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/* Internal SoC */
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port@28 {
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ethernet = <&ethernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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};
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};

‎target/linux/realtek/image/rtl930x.mk‎

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endef
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TARGET_DEVICES += hasivo_s1100w-8xgt-se
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define Device/hasivo_s1100wp-8gt-se
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SOC := rtl9303
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DEVICE_VENDOR := Hasivo
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DEVICE_MODEL := S1100WP-8GT-SE
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IMAGE_SIZE := 8364k
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$(Device/kernel-lzma)
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endef
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TARGET_DEVICES += hasivo_s1100wp-8gt-se
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define Device/plasmacloud-common
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SOC := rtl9302
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UIMAGE_MAGIC := 0x93000000

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