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hpoussinhpoussin
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[E1000] Mark register bits as unsigned
1 parent 9decade commit 5bfaecd

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1 file changed

+46
-46
lines changed

1 file changed

+46
-46
lines changed

‎drivers/network/dd/e1000/e1000hw.h‎

Lines changed: 46 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -56,10 +56,10 @@ typedef enum _E1000_RCVBUF_SIZE
5656

5757
/* 3.2.3 Receive Descriptor Format */
5858

59-
#define E1000_RDESC_STATUS_PIF (1 << 7) /* Passed in-exact filter */
60-
#define E1000_RDESC_STATUS_IXSM (1 << 2) /* Ignore Checksum Indication */
61-
#define E1000_RDESC_STATUS_EOP (1 << 1) /* End of Packet */
62-
#define E1000_RDESC_STATUS_DD (1 << 0) /* Descriptor Done */
59+
#define E1000_RDESC_STATUS_PIF (1U << 7) /* Passed in-exact filter */
60+
#define E1000_RDESC_STATUS_IXSM (1U << 2) /* Ignore Checksum Indication */
61+
#define E1000_RDESC_STATUS_EOP (1U << 1) /* End of Packet */
62+
#define E1000_RDESC_STATUS_DD (1U << 0) /* Descriptor Done */
6363

6464
typedef struct _E1000_RECEIVE_DESCRIPTOR
6565
{
@@ -76,12 +76,12 @@ typedef struct _E1000_RECEIVE_DESCRIPTOR
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7777
/* 3.3.3 Legacy Transmit Descriptor Format */
7878

79-
#define E1000_TDESC_CMD_IDE (1 << 7) /* Interrupt Delay Enable */
80-
#define E1000_TDESC_CMD_RS (1 << 3) /* Report Status */
81-
#define E1000_TDESC_CMD_IFCS (1 << 1) /* Insert FCS */
82-
#define E1000_TDESC_CMD_EOP (1 << 0) /* End Of Packet */
79+
#define E1000_TDESC_CMD_IDE (1U << 7) /* Interrupt Delay Enable */
80+
#define E1000_TDESC_CMD_RS (1U << 3) /* Report Status */
81+
#define E1000_TDESC_CMD_IFCS (1U << 1) /* Insert FCS */
82+
#define E1000_TDESC_CMD_EOP (1U << 0) /* End Of Packet */
8383

84-
#define E1000_TDESC_STATUS_DD (1 << 0) /* Descriptor Done */
84+
#define E1000_TDESC_STATUS_DD (1U << 0) /* Descriptor Done */
8585

8686
typedef struct _E1000_TRANSMIT_DESCRIPTOR
8787
{
@@ -148,23 +148,23 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16);
148148

149149

150150
/* E1000_REG_CTRL */
151-
#define E1000_CTRL_LRST (1 << 3) /* Link Reset */
152-
#define E1000_CTRL_ASDE (1 << 5) /* Auto-Speed Detection Enable */
153-
#define E1000_CTRL_SLU (1 << 6) /* Set Link Up */
154-
#define E1000_CTRL_RST (1 << 26) /* Device Reset, Self clearing */
155-
#define E1000_CTRL_VME (1 << 30) /* VLAN Mode Enable */
151+
#define E1000_CTRL_LRST (1U << 3) /* Link Reset */
152+
#define E1000_CTRL_ASDE (1U << 5) /* Auto-Speed Detection Enable */
153+
#define E1000_CTRL_SLU (1U << 6) /* Set Link Up */
154+
#define E1000_CTRL_RST (1U << 26) /* Device Reset, Self clearing */
155+
#define E1000_CTRL_VME (1U << 30) /* VLAN Mode Enable */
156156

157157

158158
/* E1000_REG_STATUS */
159-
#define E1000_STATUS_FD (1 << 0) /* Full Duplex Indication */
160-
#define E1000_STATUS_LU (1 << 1) /* Link Up Indication */
159+
#define E1000_STATUS_FD (1U << 0) /* Full Duplex Indication */
160+
#define E1000_STATUS_LU (1U << 1) /* Link Up Indication */
161161
#define E1000_STATUS_SPEEDSHIFT 6 /* Link speed setting */
162-
#define E1000_STATUS_SPEEDMASK (3 << E1000_STATUS_SPEEDSHIFT)
162+
#define E1000_STATUS_SPEEDMASK (3U << E1000_STATUS_SPEEDSHIFT)
163163

164164

165165
/* E1000_REG_EERD */
166-
#define E1000_EERD_START (1 << 0) /* Start Read*/
167-
#define E1000_EERD_DONE (1 << 4) /* Read Done */
166+
#define E1000_EERD_START (1U << 0) /* Start Read*/
167+
#define E1000_EERD_DONE (1U << 4) /* Read Done */
168168
#define E1000_EERD_ADDR_SHIFT 8
169169
#define E1000_EERD_DATA_SHIFT 16
170170

@@ -173,19 +173,19 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16);
173173
#define E1000_MDIC_REGADD_SHIFT 16 /* PHY Register Address */
174174
#define E1000_MDIC_PHYADD_SHIFT 21 /* PHY Address (1=Gigabit, 2=PCIe) */
175175
#define E1000_MDIC_PHYADD_GIGABIT 1
176-
#define E1000_MDIC_OP_READ (2 << 26) /* Opcode */
177-
#define E1000_MDIC_R (1 << 28) /* Ready Bit */
178-
#define E1000_MDIC_E (1 << 30) /* Error */
176+
#define E1000_MDIC_OP_READ (2U << 26) /* Opcode */
177+
#define E1000_MDIC_R (1U << 28) /* Ready Bit */
178+
#define E1000_MDIC_E (1U << 30) /* Error */
179179

180180

181181
/* E1000_REG_IMS */
182-
#define E1000_IMS_TXDW (1 << 0) /* Transmit Descriptor Written Back */
183-
#define E1000_IMS_TXQE (1 << 1) /* Transmit Queue Empty */
184-
#define E1000_IMS_LSC (1 << 2) /* Sets mask for Link Status Change */
185-
#define E1000_IMS_RXDMT0 (1 << 4) /* Receive Descriptor Minimum Threshold Reached */
186-
#define E1000_IMS_RXT0 (1 << 7) /* Receiver Timer Interrupt */
187-
#define E1000_IMS_TXD_LOW (1 << 15) /* Transmit Descriptor Low Threshold hit */
188-
#define E1000_IMS_SRPD (1 << 16) /* Small Receive Packet Detection */
182+
#define E1000_IMS_TXDW (1U << 0) /* Transmit Descriptor Written Back */
183+
#define E1000_IMS_TXQE (1U << 1) /* Transmit Queue Empty */
184+
#define E1000_IMS_LSC (1U << 2) /* Sets mask for Link Status Change */
185+
#define E1000_IMS_RXDMT0 (1U << 4) /* Receive Descriptor Minimum Threshold Reached */
186+
#define E1000_IMS_RXT0 (1U << 7) /* Receiver Timer Interrupt */
187+
#define E1000_IMS_TXD_LOW (1U << 15) /* Transmit Descriptor Low Threshold hit */
188+
#define E1000_IMS_SRPD (1U << 16) /* Small Receive Packet Detection */
189189

190190

191191
/* E1000_REG_ITR */
@@ -194,31 +194,31 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16);
194194

195195

196196
/* E1000_REG_RCTL */
197-
#define E1000_RCTL_EN (1 << 1) /* Receiver Enable */
198-
#define E1000_RCTL_SBP (1 << 2) /* Store Bad Packets */
199-
#define E1000_RCTL_UPE (1 << 3) /* Unicast Promiscuous Enabled */
200-
#define E1000_RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */
201-
#define E1000_RCTL_BAM (1 << 15) /* Broadcast Accept Mode */
197+
#define E1000_RCTL_EN (1U << 1) /* Receiver Enable */
198+
#define E1000_RCTL_SBP (1U << 2) /* Store Bad Packets */
199+
#define E1000_RCTL_UPE (1U << 3) /* Unicast Promiscuous Enabled */
200+
#define E1000_RCTL_MPE (1U << 4) /* Multicast Promiscuous Enabled */
201+
#define E1000_RCTL_BAM (1U << 15) /* Broadcast Accept Mode */
202202
#define E1000_RCTL_BSIZE_SHIFT 16
203-
#define E1000_RCTL_PMCF (1 << 23) /* Pass MAC Control Frames */
204-
#define E1000_RCTL_BSEX (1 << 25) /* Buffer Size Extension */
205-
#define E1000_RCTL_SECRC (1 << 26) /* Strip Ethernet CRC from incoming packet */
203+
#define E1000_RCTL_PMCF (1U << 23) /* Pass MAC Control Frames */
204+
#define E1000_RCTL_BSEX (1U << 25) /* Buffer Size Extension */
205+
#define E1000_RCTL_SECRC (1U << 26) /* Strip Ethernet CRC from incoming packet */
206206

207207
#define E1000_RCTL_FILTER_BITS (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF)
208208

209209

210210
/* E1000_REG_TCTL */
211-
#define E1000_TCTL_EN (1 << 1) /* Transmit Enable */
212-
#define E1000_TCTL_PSP (1 << 3) /* Pad Short Packets */
211+
#define E1000_TCTL_EN (1U << 1) /* Transmit Enable */
212+
#define E1000_TCTL_PSP (1U << 3) /* Pad Short Packets */
213213

214214
/* E1000_REG_TIPG */
215-
#define E1000_TIPG_IPGT_DEF (10 << 0) /* IPG Transmit Time */
216-
#define E1000_TIPG_IPGR1_DEF (10 << 10) /* IPG Receive Time 1 */
217-
#define E1000_TIPG_IPGR2_DEF (10 << 20) /* IPG Receive Time 2 */
215+
#define E1000_TIPG_IPGT_DEF (10U << 0) /* IPG Transmit Time */
216+
#define E1000_TIPG_IPGR1_DEF (10U << 10) /* IPG Receive Time 1 */
217+
#define E1000_TIPG_IPGR2_DEF (10U << 20) /* IPG Receive Time 2 */
218218

219219

220220
/* E1000_REG_RAH */
221-
#define E1000_RAH_AV (1 << 31) /* Address Valid */
221+
#define E1000_RAH_AV (1U << 31) /* Address Valid */
222222

223223

224224

@@ -236,11 +236,11 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16);
236236

237237

238238
/* E1000_PHY_STATUS */
239-
#define E1000_PS_LINK_STATUS (1 << 2)
239+
#define E1000_PS_LINK_STATUS (1U << 2)
240240

241241

242242

243243
/* E1000_PHY_SPECIFIC_STATUS */
244-
#define E1000_PSS_SPEED_AND_DUPLEX (1 << 11) /* Speed and Duplex Resolved */
244+
#define E1000_PSS_SPEED_AND_DUPLEX (1U << 11) /* Speed and Duplex Resolved */
245245
#define E1000_PSS_SPEEDSHIFT 14
246-
#define E1000_PSS_SPEEDMASK (3 << E1000_PSS_SPEEDSHIFT)
246+
#define E1000_PSS_SPEEDMASK (3U << E1000_PSS_SPEEDSHIFT)

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