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1 parent c42a38f commit 38054f6Copy full SHA for 38054f6
bitsandbytes/backends/xpu/ops.py
@@ -139,6 +139,13 @@ def _gemv_4bit_impl(
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if not isinstance(lib, ErrorHandlerMockBNBNativeLibrary):
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logger.info("Register sycl bitsandbytes kernels for XPU")
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+ # TODO: Remove the triton register when quantization sycl kernel is ready.
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+ if triton_available:
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+ from ..triton import ops as triton_ops
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+
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+ register_kernel("bitsandbytes::quantize_blockwise", "xpu")(triton_ops.quantize_blockwise)
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+ register_kernel("bitsandbytes::quantize_4bit", "xpu")(triton_ops.quantize_4bit)
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@register_kernel("bitsandbytes::dequantize_4bit", "xpu")
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def _(
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A: torch.Tensor,
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