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martijnbastiaanmartijnbastiaan
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Only return speed changes in callisto component
Everything is handled in software now
1 parent cc887cb commit 9f8774e

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9 files changed

+38
-118
lines changed

9 files changed

+38
-118
lines changed

‎bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/BringUp.hs‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ import Protocols
1919
import Bittide.BootPe (BootPeBusses, bootPe)
2020
import Bittide.CaptureUgn (sendUgnC)
2121
import Bittide.ClockControl
22-
import Bittide.ClockControl.Callisto.Types (CallistoResult (..))
2322
import Bittide.Df (asciiDebugMux)
2423
import Bittide.DoubleBufferedRam (InitialContent (Undefined))
2524
import Bittide.Instances.Domains (
@@ -143,7 +142,7 @@ bringUp refClk refRst = withBittideByteOrder $ circuit $ \(bootMm, muMm, ccMm, g
143142
$ sendUgnC localCounter tOutputs.txSamplings
144143
-< switchDataOut
145144

146-
( Fwd callistoResult
145+
( Fwd speedChanges
147146
, Fwd localCounter
148147
, switchDataOut
149148
, sync
@@ -190,6 +189,6 @@ bringUp refClk refRst = withBittideByteOrder $ circuit $ \(bootMm, muMm, ccMm, g
190189
bittideRst
191190
enableGen
192191
(SNat @Si539xHoldTime)
193-
callistoResult.maybeSpeedChange
192+
speedChanges
194193

195194
idC -< (spi, sync, uartTx, Fwd frequencyAdjustments)

‎bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Core.hs‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ import Protocols
99

1010
import Bittide.Calendar (CalendarConfig (..), ValidEntry (..))
1111
import Bittide.CaptureUgn (captureUgn)
12-
import Bittide.ClockControl.Callisto.Types (CallistoResult (..), Stability (..))
12+
import Bittide.ClockControl (SpeedChange)
1313
import Bittide.ClockControl.CallistoSw (SwcccInternalBusses, callistoSwClockControlC)
1414
import Bittide.DoubleBufferedRam (InitialContent (Undefined), wbStorage)
1515
import Bittide.ElasticBuffer (xilinxElasticBufferWb)
@@ -214,7 +214,7 @@ core ::
214214
, "CC_SUITABLE" ::: CSignal Bittide (BitVector LinkCount)
215215
, "RXS" ::: Vec LinkCount (CSignal GthRx (Maybe (BitVector 64)))
216216
)
217-
( CSignal Bittide (CallistoResult LinkCount)
217+
( CSignal Bittide (Maybe SpeedChange)
218218
, "LOCAL_COUNTER" ::: CSignal Bittide (Unsigned 64)
219219
, "TXS" ::: Vec LinkCount (CSignal Bittide (BitVector 64))
220220
, Sync Bittide Basic125
@@ -305,14 +305,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
305305
in
306306
if simulateCc
307307
then swCcOut0
308-
else
309-
pure
310-
$ CallistoResult
311-
{ maybeSpeedChange = Nothing
312-
, stability = repeat (Stability{stable = True, settled = True})
313-
, allStable = True
314-
, allSettled = True
315-
}
308+
else pure Nothing
316309
else swCcOut0
317310

318311
-- Use of `dflipflop` to add pipelining should be replaced by

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/BringUp.hs‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ import Protocols
1919
import Bittide.BootPe (BootPeBusses, bootPe)
2020
import Bittide.CaptureUgn (sendUgnC)
2121
import Bittide.ClockControl
22-
import Bittide.ClockControl.Callisto.Types (CallistoResult (..))
2322
import Bittide.Df (asciiDebugMux)
2423
import Bittide.DoubleBufferedRam (InitialContent (Undefined))
2524
import Bittide.Instances.Domains (
@@ -143,7 +142,7 @@ bringUp refClk refRst = withBittideByteOrder $ circuit $ \(bootMm, muMm, ccMm, j
143142
$ sendUgnC localCounter tOutputs.txSamplings
144143
-< switchDataOut
145144

146-
( Fwd callistoResult
145+
( Fwd speedChanges
147146
, Fwd localCounter
148147
, switchDataOut
149148
, sync
@@ -188,6 +187,6 @@ bringUp refClk refRst = withBittideByteOrder $ circuit $ \(bootMm, muMm, ccMm, j
188187
bittideRst
189188
enableGen
190189
(SNat @Si539xHoldTime)
191-
callistoResult.maybeSpeedChange
190+
speedChanges
192191

193192
idC -< (spi, sync, uartTx, Fwd frequencyAdjustments)

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Core.hs‎

Lines changed: 15 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ import Protocols
99

1010
import Bittide.Calendar (CalendarConfig (..), ValidEntry (..))
1111
import Bittide.CaptureUgn (captureUgn)
12-
import Bittide.ClockControl.Callisto.Types (CallistoResult (..), Stability (..))
12+
import Bittide.ClockControl (SpeedChange)
1313
import Bittide.ClockControl.CallistoSw (SwcccInternalBusses, callistoSwClockControlC)
1414
import Bittide.DoubleBufferedRam (InitialContent (Undefined), wbStorage)
1515
import Bittide.ElasticBuffer (xilinxElasticBufferWb)
@@ -175,7 +175,7 @@ core ::
175175
, CSignal Bittide (BitVector LinkCount)
176176
, Vec LinkCount (CSignal GthRx (Maybe (BitVector 64)))
177177
)
178-
( CSignal Bittide (CallistoResult LinkCount)
178+
( CSignal Bittide (Maybe SpeedChange)
179179
, "LOCAL_COUNTER" ::: CSignal Bittide (Unsigned 64)
180180
, "TXS" ::: Vec LinkCount (CSignal Bittide (BitVector 64))
181181
, Sync Bittide Basic125
@@ -261,25 +261,19 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
261261
-< (ccUartBus, Fwd (pure Nothing))
262262
-- Stop clock control
263263

264-
let swCcOut1 =
265-
if clashSimulation
266-
then
267-
let
268-
-- Should all clock control steps be run in simulation?
269-
-- False means that clock control will always immediately be done.
270-
simulateCc = False
271-
in
272-
if simulateCc
273-
then swCcOut0
274-
else
275-
pure
276-
$ CallistoResult
277-
{ maybeSpeedChange = Nothing
278-
, stability = repeat (Stability{stable = True, settled = True})
279-
, allStable = True
280-
, allSettled = True
281-
}
282-
else swCcOut0
264+
let
265+
swCcOut1 =
266+
if clashSimulation
267+
then
268+
let
269+
-- Should all clock control steps be run in simulation?
270+
-- False means that clock control will always immediately be done.
271+
simulateCc = False
272+
in
273+
if simulateCc
274+
then swCcOut0
275+
else pure Nothing
276+
else swCcOut0
283277

284278
idC
285279
-< ( Fwd swCcOut1

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/BringUp.hs‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ import Protocols
1919
import Bittide.BootPe (BootPeBusses, bootPe)
2020
import Bittide.CaptureUgn (sendUgnC)
2121
import Bittide.ClockControl
22-
import Bittide.ClockControl.Callisto.Types (CallistoResult (..))
2322
import Bittide.Df (asciiDebugMux)
2423
import Bittide.DoubleBufferedRam (InitialContent (Undefined))
2524
import Bittide.Instances.Domains (
@@ -143,7 +142,7 @@ bringUp refClk refRst = withBittideByteOrder $ circuit $ \(bootMm, muMm, ccMm, g
143142
$ sendUgnC localCounter tOutputs.txSamplings
144143
-< switchDataOut
145144

146-
( Fwd callistoResult
145+
( Fwd speedChanges
147146
, Fwd localCounter
148147
, switchDataOut
149148
, sync
@@ -190,6 +189,6 @@ bringUp refClk refRst = withBittideByteOrder $ circuit $ \(bootMm, muMm, ccMm, g
190189
bittideRst
191190
enableGen
192191
(SNat @Si539xHoldTime)
193-
callistoResult.maybeSpeedChange
192+
speedChanges
194193

195194
idC -< (spi, sync, uartTx, Fwd frequencyAdjustments)

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Core.hs‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ import Protocols
99

1010
import Bittide.Calendar (CalendarConfig (..), ValidEntry (..))
1111
import Bittide.CaptureUgn (captureUgn)
12-
import Bittide.ClockControl.Callisto.Types (CallistoResult (..), Stability (..))
12+
import Bittide.ClockControl (SpeedChange)
1313
import Bittide.ClockControl.CallistoSw (SwcccInternalBusses, callistoSwClockControlC)
1414
import Bittide.DoubleBufferedRam (InitialContent (Undefined), wbStorage)
1515
import Bittide.ElasticBuffer (xilinxElasticBufferWb)
@@ -239,7 +239,7 @@ core ::
239239
, CSignal Bittide (BitVector LinkCount)
240240
, "RXS" ::: Vec LinkCount (CSignal GthRx (Maybe (BitVector 64)))
241241
)
242-
( CSignal Bittide (CallistoResult LinkCount)
242+
( CSignal Bittide (Maybe SpeedChange)
243243
, "LOCAL_COUNTER" ::: CSignal Bittide (Unsigned 64)
244244
, "TXS" ::: Vec LinkCount (CSignal Bittide (BitVector 64))
245245
, Sync Bittide Basic125
@@ -333,14 +333,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
333333
in
334334
if simulateCc
335335
then swCcOut0
336-
else
337-
pure
338-
$ CallistoResult
339-
{ maybeSpeedChange = Nothing
340-
, stability = repeat (Stability{stable = True, settled = True})
341-
, allStable = True
342-
, allSettled = True
343-
}
336+
else pure Nothing
344337
else swCcOut0
345338

346339
idC

‎bittide/src/Bittide/ClockControl/Callisto/Types.hs‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,12 @@
11
-- SPDX-FileCopyrightText: 2023 Google LLC
22
--
33
-- SPDX-License-Identifier: Apache-2.0
4-
{-# LANGUAGE GeneralizedNewtypeDeriving #-}
5-
{-# LANGUAGE RecordWildCards #-}
6-
{-# LANGUAGE UndecidableInstances #-}
7-
{-# OPTIONS_GHC -fconstraint-solver-iterations=20 #-}
8-
94
module Bittide.ClockControl.Callisto.Types (
10-
CallistoResult (..),
115
Stability (..),
126
) where
137

148
import Clash.Prelude
159

16-
import Bittide.ClockControl
17-
1810
-- | Stability results to be returned by the 'stability_detector'.
1911
data Stability = Stability
2012
{ stable :: Bool
@@ -24,19 +16,3 @@ data Stability = Stability
2416
-- 'targetDataCount'.
2517
}
2618
deriving (Generic, NFDataX, BitPack, ShowX, Show)
27-
28-
-- | Result of the clock control algorithm.
29-
data CallistoResult (n :: Nat) = CallistoResult
30-
{ maybeSpeedChange :: Maybe SpeedChange
31-
-- ^ Speed change requested for clock multiplier. This is 'Just' for a single
32-
-- cycle.
33-
, stability :: Vec n Stability
34-
-- ^ All stability indicators for all of the elastic buffers.
35-
, allStable :: Bool
36-
-- ^ Joint stability indicator signaling that all elastic buffers
37-
-- are stable.
38-
, allSettled :: Bool
39-
-- ^ Joint "being-settled" indicator signaling that all elastic
40-
-- buffers have been settled.
41-
}
42-
deriving (Generic, NFDataX)

‎bittide/src/Bittide/ClockControl/CallistoSw.hs‎

Lines changed: 5 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,9 @@ import Clash.Functor.Extra ((<<$>>))
1515
import Protocols
1616
import VexRiscv
1717

18-
import Bittide.ClockControl.Callisto.Types (
19-
CallistoResult (CallistoResult),
20-
)
18+
import Bittide.ClockControl (SpeedChange)
2119
import Bittide.ClockControl.Freeze (freeze)
22-
import Bittide.ClockControl.Registers (ClockControlData (..), clockControlWb)
20+
import Bittide.ClockControl.Registers (clockControlWb)
2321
import Bittide.Counter (domainDiffCountersWbC)
2422
import Bittide.ProcessingElement
2523
import Bittide.SharedTypes
@@ -80,7 +78,7 @@ callistoSwClockControlC ::
8078
)
8179
)
8280
( Sync dom free
83-
, CSignal dom (CallistoResult nLinks)
81+
, CSignal dom (Maybe SpeedChange)
8482
, Vec
8583
otherWb
8684
(BitboneMm dom (SwcccRemBusWidth otherWb))
@@ -98,8 +96,7 @@ callistoSwClockControlC freeClk freeRst rxClocks rxResets dumpVcd peConfig =
9896
) <-
9997
Vec.split -< allWishbone
10098

101-
Fwd clockControlData <-
102-
clockControlWb linkMask linksOk (unbundle diffCounters) -< clockControlBus
99+
speedChanges <- clockControlWb linkMask linksOk (unbundle diffCounters) -< clockControlBus
103100

104101
clockControlBus <- arbiterMm -< [ccClockControlBusWide, muClockControlBusWide]
105102
-- We need to extend the width of both wishbone busses since we don't know which
@@ -131,13 +128,4 @@ callistoSwClockControlC freeClk freeRst rxClocks rxResets dumpVcd peConfig =
131128

132129
let diffCounters = fst <<$>> domainDiffs
133130

134-
let
135-
callistoCResult :: Signal dom (CallistoResult nLinks)
136-
callistoCResult =
137-
CallistoResult
138-
<$> clockControlData.clockMod
139-
<*> clockControlData.stabilities
140-
<*> clockControlData.allStable
141-
<*> clockControlData.allSettled
142-
143-
idC -< (sync, Fwd callistoCResult, wbRest)
131+
idC -< (sync, speedChanges, wbRest)

‎bittide/src/Bittide/ClockControl/Registers.hs‎

Lines changed: 6 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,12 @@ import Bittide.ClockControl.Callisto.Types (Stability (..))
1515
import Bittide.ClockControl.Config (CcConf (CcConf, callisto, topology), defCcConf)
1616
import Clash.Class.BitPackC (ByteOrder)
1717
import Clash.Explicit.Reset (unsafeOrReset)
18-
import Clash.Functor.Extra ((<<$>>), (<<*>>))
1918
import GHC.Stack (HasCallStack)
2019
import Protocols.MemoryMap (Access (ReadOnly, WriteOnly), Mm)
2120
import Protocols.MemoryMap.Registers.WishboneStandard (
2221
BusActivity (BusWrite),
2322
RegisterConfig (access, description),
23+
busActivityWrite,
2424
deviceWb,
2525
registerConfig,
2626
registerWb,
@@ -78,7 +78,7 @@ clockControlWb ::
7878
-- | Wishbone accessible clock control circuitry
7979
Circuit
8080
(ToConstBwd Mm, Wishbone dom 'Standard addrW (BitVector 32))
81-
(CSignal dom (ClockControlData nLinks))
81+
(CSignal dom (Maybe SpeedChange))
8282
clockControlWb linkMask linksOk (bundle -> counters) = circuit $ \(mm, wb) -> do
8383
[ wbNumLinks
8484
, wbLinkMask
@@ -102,14 +102,11 @@ clockControlWb linkMask linksOk (bundle -> counters) = circuit $ \(mm, wb) -> do
102102
-- Link configuration
103103
registerWbI_ numLinksConfig numberOfLinks -< (wbNumLinks, Fwd noWrite)
104104
registerWbI_ linkMaskConfig 0 -< (wbLinkMask, Fwd (Just <$> linkMask))
105-
registerWbI_ linkMaskPopCountConfig 0
106-
-< (wbLinkMaskPopCount, Fwd (Just <$> linkMaskPopCount))
105+
registerWbI_ linkMaskPopCountConfig 0 -< (wbLinkMaskPopCount, Fwd (Just <$> linkMaskPopCount))
107106
registerWbI_ linkMaskRevConfig 0 -< (wbLinkMaskRev, Fwd (Just <$> linkMaskRev))
108107
registerWbI_ linksOkConfig 0 -< (wbLinksOk, Fwd (Just <$> linksOk))
109-
(Fwd linksStable, _l0) <-
110-
registerWbI linksStableConfig (0 :: BitVector nLinks) -< (wbLinksStable, Fwd noWrite)
111-
(Fwd linksSettled, _l1) <-
112-
registerWbI linksSettledConfig (0 :: BitVector nLinks) -< (wbLinksSettled, Fwd noWrite)
108+
registerWbI_ linksStableConfig (0 :: BitVector nLinks) -< (wbLinksStable, Fwd noWrite)
109+
registerWbI_ linksSettledConfig (0 :: BitVector nLinks) -< (wbLinksSettled, Fwd noWrite)
113110

114111
-- Data count tracking
115112
registerWbI_ dataCountsConfig (repeat 0)
@@ -127,12 +124,6 @@ clockControlWb linkMask linksOk (bundle -> counters) = circuit $ \(mm, wb) -> do
127124
registerWbI_ configConfig (defCcConfLinks @nLinks) -< (wbConfig, Fwd noWrite)
128125

129126
let
130-
maskedLinksStable = applyMask True linkMask (unpack <$> linksStable)
131-
allLinksStable = and <$> maskedLinksStable
132-
133-
maskedLinksSettled = applyMask True linkMask (unpack <$> linksSettled)
134-
allLinksSettled = and <$> maskedLinksSettled
135-
136127
dataCountsSeenReset :: Reset dom
137128
dataCountsSeenReset =
138129
unsafeOrReset
@@ -145,15 +136,7 @@ clockControlWb linkMask linksOk (bundle -> counters) = circuit $ \(mm, wb) -> do
145136
maxDataCountsSeen1 :: Signal dom (Vec nLinks (RelDataCount m))
146137
maxDataCountsSeen1 = zipWith max <$> maxDataCountsSeen0 <*> maskedCounters
147138

148-
clockControlData :: Signal dom (ClockControlData nLinks)
149-
clockControlData =
150-
ClockControlData
151-
<$> fmap busActivityToMaybeSpeedChange changeSpeed
152-
<*> (Stability <<$>> maskedLinksStable <<*>> maskedLinksSettled)
153-
<*> allLinksStable
154-
<*> allLinksSettled
155-
156-
idC -< Fwd clockControlData
139+
idC -< Fwd (busActivityWrite <$> changeSpeed)
157140
where
158141
noWrite = pure Nothing
159142

@@ -186,7 +169,3 @@ clockControlWb linkMask linksOk (bundle -> counters) = circuit $ \(mm, wb) -> do
186169

187170
maskedCounters :: Signal dom (Vec nLinks (RelDataCount m))
188171
maskedCounters = applyMask 0 linkMask counters
189-
190-
busActivityToMaybeSpeedChange :: Maybe (BusActivity SpeedChange) -> Maybe SpeedChange
191-
busActivityToMaybeSpeedChange (Just (BusWrite change)) = Just change
192-
busActivityToMaybeSpeedChange _ = Nothing

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