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emebemeb
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stm32h7rs: CRC works, tested breakpoints, erase_mass. Minor cleanups.
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‎src/target/stm32h7rs.c‎

Lines changed: 105 additions & 145 deletions
Original file line numberDiff line numberDiff line change
@@ -34,108 +34,99 @@
3434
#include "cortexm.h"
3535
#include "stm32_common.h"
3636

37-
#define FLASH_ACR 0x000U
38-
#define FLASH_KEYR 0x004U
39-
#define FLASH_CR 0x010U
40-
#define FLASH_SR 0x014U
41-
#define FLASH_IER 0x020U
42-
#define FLASH_ISR 0x024U
43-
#define FLASH_ICR 0x028U
44-
//#define FLASH_OPTKEYR 0x008U
45-
//#define FLASH_CCR 0x014U
46-
//#define FLASH_OPTCR 0x018U
47-
//#define FLASH_OPTSR_CUR 0x01cU
48-
//#define FLASH_OPTSR 0x020U
49-
#define FLASH_CRCCR 0x050U
50-
#define FLASH_CRCDATA 0x05cU
51-
5237
/* Flash Program and Erase Controller Register Map */
53-
#define FPEC1_BASE 0x52002000U
54-
#define FLASH_SR_BSY (1U << 0U)
55-
#define FLASH_SR_WBNE (1U << 1U)
56-
#define FLASH_SR_QW (1U << 2U)
57-
#define FLASH_SR_CRC_BUSY (1U << 3U)
58-
#define FLASH_ISR_EOP (1U << 16U)
59-
#define FLASH_ISR_WRPERR (1U << 17U)
60-
#define FLASH_ISR_PGSERR (1U << 18U)
61-
#define FLASH_ISR_STRBERR (1U << 19U)
62-
#define FLASH_ISR_INCERR (1U << 21U)
63-
#define FLASH_ISR_RDSERR (1U << 24U)
64-
#define FLASH_ISR_SNECCERR (1U << 25U)
65-
#define FLASH_ISR_DBECCERR (1U << 26U)
66-
#define FLASH_ISR_CRCEND (1U << 27U)
67-
#define FLASH_ISR_CRCRDERR (1U << 28U)
68-
#define FLASH_ISR_ERROR_READ (FLASH_ISR_RDSERR | FLASH_ISR_SNECCERR | FLASH_ISR_DBECCERR)
69-
#define FLASH_ISR_ERROR_MASK \
38+
#define FPEC1_BASE 0x52002000U
39+
#define FLASH_ACR 0x000U
40+
#define FLASH_KEYR 0x004U
41+
#define FLASH_CR 0x010U
42+
#define FLASH_SR 0x014U
43+
#define FLASH_IER 0x020U
44+
#define FLASH_ISR 0x024U
45+
#define FLASH_ICR 0x028U
46+
#define FLASH_CRCCR 0x030U
47+
#define FLASH_CRCDATA 0x03cU
48+
#define FLASH_SR_BSY (1U << 0U)
49+
#define FLASH_SR_WBNE (1U << 1U)
50+
#define FLASH_SR_QW (1U << 2U)
51+
#define FLASH_SR_CRC_BUSY (1U << 3U)
52+
#define FLASH_ISR_EOP (1U << 16U)
53+
#define FLASH_ISR_WRPERR (1U << 17U)
54+
#define FLASH_ISR_PGSERR (1U << 18U)
55+
#define FLASH_ISR_STRBERR (1U << 19U)
56+
#define FLASH_ISR_INCERR (1U << 21U)
57+
#define FLASH_ISR_RDSERR (1U << 24U)
58+
#define FLASH_ISR_SNECCERR (1U << 25U)
59+
#define FLASH_ISR_DBECCERR (1U << 26U)
60+
#define FLASH_ISR_CRCEND (1U << 27U)
61+
#define FLASH_ISR_CRCRDERR (1U << 28U)
62+
#define FLASH_ISR_ERROR_READ (FLASH_ISR_RDSERR | FLASH_ISR_SNECCERR | FLASH_ISR_DBECCERR)
63+
#define FLASH_ISR_ERROR_MASK \
7064
(FLASH_ISR_WRPERR | FLASH_ISR_PGSERR | FLASH_ISR_STRBERR | FLASH_ISR_INCERR | FLASH_ISR_ERROR_READ)
71-
#define FLASH_CR_LOCK (1U << 0U)
72-
#define FLASH_CR_PG (1U << 1U)
73-
#define FLASH_CR_SER (1U << 2U)
74-
#define FLASH_CR_BER (1U << 3U)
75-
//#define FLASH_CR_PSIZE8 (0U << 4U)
76-
//#define FLASH_CR_PSIZE16 (1U << 4U)
77-
//#define FLASH_CR_PSIZE32 (2U << 4U)
78-
//#define FLASH_CR_PSIZE64 (3U << 4U)
79-
#define FLASH_CR_FW (1U << 4U)
80-
#define FLASH_CR_START (1U << 5U)
81-
#define FLASH_CR_SSN_SHIFT 6U
82-
//#define FLASH_CR_SNB_1 (1U << 8U)
83-
//#define FLASH_CR_SNB (3U << 8U)
84-
#define FLASH_CR_CRC_EN (1U << 15U)
85-
//
86-
//#define FLASH_OPTCR_OPTLOCK (1U << 0U)
87-
//#define FLASH_OPTCR_OPTSTRT (1U << 1U)
88-
//
89-
//#define FLASH_OPTSR_IWDG1_SW (1U << 4U)
90-
//
91-
#define FLASH_CRCCR_ALL_BANK (1U << 7U)
92-
#define FLASH_CRCCR_START_CRC (1U << 16U)
93-
#define FLASH_CRCCR_CLEAN_CRC (1U << 17U)
94-
#define FLASH_CRCCR_CRC_BURST_3 (3U << 20U)
95-
96-
#define STM32H7RS_FLASH_KEY1 0x45670123U
97-
#define STM32H7RS_FLASH_KEY2 0xcdef89abU
98-
99-
#define STM32H7RS_OPT_KEY1 0x08192a3bU
100-
#define STM32H7RS_OPT_KEY2 0x4c5d6e7fU
101-
102-
#define STM32H7RS_FLASH_SIZE 0x1ff1e880U
103-
#define STM32H7RS_FLASH_BANK1_BASE 0x08000000U
104-
#define STM32H7RS_FLASH_BANK_SIZE 0x00010000U
105-
#define NUM_SECTOR_PER_BANK 8U
106-
#define FLASH_SECTOR_SIZE 0x2000U
65+
#define FLASH_CR_LOCK (1U << 0U)
66+
#define FLASH_CR_PG (1U << 1U)
67+
#define FLASH_CR_SER (1U << 2U)
68+
#define FLASH_CR_BER (1U << 3U)
69+
#define FLASH_CR_FW (1U << 4U)
70+
#define FLASH_CR_START (1U << 5U)
71+
#define FLASH_CR_SSN_SHIFT 6U
72+
#define FLASH_CR_CRC_EN (1U << 17U)
73+
#define FLASH_CRCCR_ALL_BANK (1U << 7U)
74+
#define FLASH_CRCCR_START_CRC (1U << 16U)
75+
#define FLASH_CRCCR_CLEAN_CRC (1U << 17U)
76+
#define FLASH_CRCCR_CRC_BURST_3 (3U << 20U)
77+
78+
#define STM32H7RS_FLASH_KEY1 0x45670123U
79+
#define STM32H7RS_FLASH_KEY2 0xcdef89abU
80+
81+
#define STM32H7RS_OPT_KEY1 0x08192a3bU
82+
#define STM32H7RS_OPT_KEY2 0x4c5d6e7fU
83+
84+
#define STM32H7RS_FLASH_SIZE 0x1ff1e880U
85+
#define STM32H7RS_FLASH_BANK1_BASE 0x08000000U
86+
#define STM32H7RS_FLASH_BANK_SIZE 0x00010000U
87+
#define NUM_SECTOR_PER_BANK 8U
88+
#define FLASH_SECTOR_SIZE 0x2000U
10789

10890
/* WWDG base address and register map */
109-
#define STM32H7RS_WWDG_BASE 0x40002c00U
110-
#define STM32H7RS_WWDG_CR (STM32H7RS_WWDG_BASE + 0x00)
111-
#define STM32H7RS_WWDG_CR_RESET 0x0000007fU
91+
#define STM32H7RS_WWDG_BASE 0x40002c00U
92+
#define STM32H7RS_WWDG_CR (STM32H7RS_WWDG_BASE + 0x00)
93+
#define STM32H7RS_WWDG_CR_RESET 0x0000007fU
11294

11395
/* IWDG base address and register map */
114-
#define STM32H7RS_IWDG_BASE 0x58004800U
115-
#define STM32H7RS_IWDG_KEY (STM32H7RS_IWDG_BASE + 0x00U)
116-
#define STM32H7RS_IWDG_KEY_RESET 0x0000aaaaU
117-
118-
/* Access from processor address space.
119-
* Access via the APB-D is at 0xe00e1000 */
120-
#define DBGMCU_IDCODE 0x5c001000U
121-
#define DBGMCU_IDC (DBGMCU_IDCODE + 0U)
122-
#define DBGMCU_CR (DBGMCU_IDCODE + 4U)
123-
#define DBGMCU_APB1FREEZE (DBGMCU_IDCODE + 0x03cU)
124-
#define DBGMCU_APB4FREEZE (DBGMCU_IDCODE + 0x054U)
125-
#define DBGSLEEP_D1 (1U << 0U)
126-
#define DBGSTOP_D1 (1U << 1U)
127-
#define DBGSTBY_D1 (1U << 2U)
128-
#define DBGSTOP_D3 (1U << 7U)
129-
#define DBGSTBY_D3 (1U << 8U)
130-
#define D1DBGCKEN (1U << 21U)
131-
#define D3DBGCKEN (1U << 22U)
132-
#define DBGMCU_APB1FREEZE_WWDG1 (1U << 11U)
133-
#define DBGMCU_APB4FREEZE_IWDG1 (1U << 18U)
134-
135-
#define STM32H7RS_DBGMCU_IDCODE_DEV_MASK 0x00000fffU
136-
#define STM32H7RS_DBGMCU_IDCODE_REV_SHIFT 16U
137-
138-
#define ID_STM32H7RS 0x485U /* RM0477 */
96+
#define STM32H7RS_IWDG_BASE 0x58004800U
97+
#define STM32H7RS_IWDG_KEY (STM32H7RS_IWDG_BASE + 0x00U)
98+
#define STM32H7RS_IWDG_KEY_RESET 0x0000aaaaU
99+
100+
/*
101+
* Access from processor address space.
102+
* Access via the APB-D is at 0xe00e1000
103+
*/
104+
#define DBGMCU_IDCODE 0x5c001000U
105+
#define DBGMCU_IDC (DBGMCU_IDCODE + 0U)
106+
#define DBGMCU_CR (DBGMCU_IDCODE + 4U)
107+
#define DBGMCU_APB1FREEZE (DBGMCU_IDCODE + 0x03cU)
108+
#define DBGMCU_APB4FREEZE (DBGMCU_IDCODE + 0x054U)
109+
#define DBGSLEEP_D1 (1U << 0U)
110+
#define DBGSTOP_D1 (1U << 1U)
111+
#define DBGSTBY_D1 (1U << 2U)
112+
#define DBGSTOP_D3 (1U << 7U)
113+
#define DBGSTBY_D3 (1U << 8U)
114+
#define D1DBGCKEN (1U << 21U)
115+
#define D3DBGCKEN (1U << 22U)
116+
#define DBGMCU_APB1FREEZE_WWDG1 (1U << 11U)
117+
#define DBGMCU_APB4FREEZE_IWDG1 (1U << 18U)
118+
119+
#define STM32H7RS_DBGMCU_IDCODE_DEV_MASK 0x00000fffU
120+
#define STM32H7RS_DBGMCU_IDCODE_REV_SHIFT 16U
121+
122+
#define ID_STM32H7RS 0x485U /* RM0477 */
123+
124+
/*
125+
* Uncomment this to enable DBGMCU setup in attach() and detach()
126+
* This seem to cause problems with reconnecting to the target and is
127+
* also somewhat redundant with similar setup that happens in probe()
128+
*/
129+
//#define CONFIG_EXPERIMENTAL_DBGMCU
139130

140131
typedef struct stm32h7rs_flash {
141132
target_flash_s target_flash;
@@ -214,17 +205,10 @@ bool stm32h7rs_probe(target_s *target)
214205
target->mass_erase = stm32h7rs_mass_erase;
215206
target_add_commands(target, stm32h7rs_cmd_list, target->driver);
216207

217-
/* EMEB - Decide which of these is correct */
218-
#if 0
219-
/* RM0433 Rev 4 is not really clear, what bits are needed in DBGMCU_CR. Maybe more flags needed? */
220-
const uint32_t dbgmcu_ctrl = DBGSLEEP_D1 | D1DBGCKEN;
221-
target_mem32_write32(target, DBGMCU_CR, dbgmcu_ctrl);
222-
#else
223208
/* Now we have a stable debug environment, make sure the WDTs can't bonk the processor out from under us */
224209
target_mem32_write32(target, DBGMCU_APB1FREEZE, DBGMCU_APB1FREEZE_WWDG1);
225210
target_mem32_write32(target, DBGMCU_APB4FREEZE, DBGMCU_APB4FREEZE_IWDG1);
226211
/*
227-
* EMEB - this is redundant w/ stuff that happens at attach()
228212
* Make sure that both domain D1 and D3 debugging are enabled and that we can keep
229213
* debugging through sleep, stop and standby states for domain D1
230214
*/
@@ -233,9 +217,9 @@ bool stm32h7rs_probe(target_s *target)
233217
DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN);
234218
target_mem32_write32(target, STM32H7RS_WWDG_CR, STM32H7RS_WWDG_CR_RESET);
235219
target_mem32_write32(target, STM32H7RS_IWDG_KEY, STM32H7RS_IWDG_KEY_RESET);
236-
#endif
220+
237221

238-
/* Build the RAM map - EMEB: ITCM/DTCM are too big -shared w/ AXI */
222+
/* Build the RAM map */
239223
switch (target->part_id) {
240224
case ID_STM32H7RS: {
241225
/* Table 6. Memory map and default device memory area attributes RM0477, pg151 */
@@ -270,16 +254,7 @@ static bool stm32h7rs_attach(target_s *target)
270254
{
271255
if (!cortexm_attach(target))
272256
return false;
273-
#if 1
274-
/*
275-
* If IWDG runs as HARDWARE watchdog (§44.3.4) erase
276-
* will be aborted by the Watchdog and erase fails!
277-
* Setting IWDG_KR to 0xaaaa does not seem to help!
278-
*/
279-
//const uint32_t optsr = target_mem_read32(target, FPEC1_BASE + FLASH_OPTSR);
280-
//if (!(optsr & FLASH_OPTSR_IWDG1_SW))
281-
// tc_printf(target, "Hardware IWDG running. Expect failure. Set IWDG1_SW!");
282-
#else
257+
#ifdef CONFIG_EXPERIMENTAL_DBGMCU
283258
/*
284259
* Make sure that both domain D1 and D3 debugging are enabled and that we can keep
285260
* debugging through sleep, stop and standby states for domain D1 - this is duplicated as it's undone by detach.
@@ -294,10 +269,10 @@ static bool stm32h7rs_attach(target_s *target)
294269

295270
static void stm32h7rs_detach(target_s *target)
296271
{
297-
#if 1
298-
//stm32h7rs_priv_s *ps = (stm32h7rs_priv_s *)target->target_storage;
299-
//target_mem_write32(target, DBGMCU_CR, ps->dbg_cr);
300-
#else
272+
#ifdef CONFIG_EXPERIMENTAL_DBGMCU
273+
/*
274+
* undo DBGMCU setup done in attach()
275+
*/
301276
target_mem32_write32(target, DBGMCU_CR,
302277
target_mem32_read32(target, DBGMCU_CR) &
303278
~(DBGSLEEP_D1 | DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN));
@@ -307,7 +282,8 @@ static void stm32h7rs_detach(target_s *target)
307282

308283
static bool stm32h7rs_flash_wait_complete(target_s *const target, const uint32_t regbase)
309284
{
310-
uint32_t status = FLASH_SR_QW, istatus = 0U;
285+
uint32_t status = FLASH_SR_QW;
286+
uint32_t istatus = 0U;
311287
/* Loop waiting for the queuewait bit to clear and EOP to set, indicating completion of all ongoing operations */
312288
while (!(istatus & FLASH_ISR_EOP) && (status & FLASH_SR_QW)) {
313289
status = target_mem32_read32(target, regbase + FLASH_SR);
@@ -474,51 +450,34 @@ static bool stm32h7rs_mass_erase(target_s *target, platform_timeout_s *const pri
474450
return stm32h7rs_check_bank(target, FPEC1_BASE);
475451
}
476452

477-
/*
478-
* Print the Unique device ID.
479-
* Can be reused for other STM32 devices with uid as parameter.
480-
*/
481453
static bool stm32h7rs_uid(target_s *target, int argc, const char **argv)
482454
{
483455
(void)argc;
484456
(void)argv;
485-
486457
const uint32_t uid_addr = 0x08fff800U;
487-
488-
tc_printf(target, "0x");
489-
for (size_t i = 0; i < 12U; i += 4U) {
490-
const uint32_t value = target_mem32_read32(target, uid_addr + i);
491-
tc_printf(target, "%02X%02X%02X%02X", (value >> 24U) & 0xffU, (value >> 16U) & 0xffU, (value >> 8U) & 0xffU,
492-
value & 0xffU);
493-
}
494-
tc_printf(target, "\n");
495-
return true;
458+
return stm32_uid(target, uid_addr);
496459
}
497460

498-
static bool stm32h7rs_crc_bank(target_s *target, uint32_t addr)
461+
static bool stm32h7rs_crc_bank(target_s *target)
499462
{
500-
(void) addr;
501463
const uint32_t reg_base = FPEC1_BASE;
502464
if (!stm32h7rs_flash_unlock(target, reg_base))
503465
return false;
504466

505467
target_mem32_write32(target, reg_base + FLASH_CR, FLASH_CR_CRC_EN);
506-
const uint32_t crc_ctrl = FLASH_CRCCR_CRC_BURST_3 | FLASH_CRCCR_CLEAN_CRC | FLASH_CRCCR_ALL_BANK;
507-
target_mem32_write32(target, reg_base + FLASH_CRCCR, crc_ctrl);
468+
const uint32_t crc_ctrl =
469+
FLASH_CRCCR_CLEAN_CRC | FLASH_CRCCR_CRC_BURST_3 | FLASH_CRCCR_ALL_BANK;
508470
target_mem32_write32(target, reg_base + FLASH_CRCCR, crc_ctrl | FLASH_CRCCR_START_CRC);
509471
uint32_t status = FLASH_SR_CRC_BUSY;
510-
#if ENABLE_DEBUG == 1
511-
const uint8_t bank = reg_base == FPEC1_BASE ? 1 : 2;
512-
#endif
513472
while (status & FLASH_SR_CRC_BUSY) {
514473
status = target_mem32_read32(target, reg_base + FLASH_SR);
515474
if (target_check_error(target)) {
516-
DEBUG_ERROR("CRC bank %u: comm failed\n", bank);
475+
DEBUG_ERROR("CRC comm failed\n");
517476
return false;
518477
}
519478
uint32_t istatus = target_mem32_read32(target, reg_base + FLASH_ISR);
520479
if (istatus & FLASH_ISR_ERROR_READ) {
521-
DEBUG_ERROR("CRC bank %u: error status %08" PRIx32 "\n", bank, istatus);
480+
DEBUG_ERROR("CRC error status %08" PRIx32 "\n", istatus);
522481
return false;
523482
}
524483
}
@@ -529,10 +488,10 @@ static bool stm32h7rs_crc(target_s *target, int argc, const char **argv)
529488
{
530489
(void)argc;
531490
(void)argv;
532-
if (!stm32h7rs_crc_bank(target, STM32H7RS_FLASH_BANK1_BASE))
491+
if (!stm32h7rs_crc_bank(target))
533492
return false;
534493
uint32_t crc1 = target_mem32_read32(target, FPEC1_BASE + FLASH_CRCDATA);
535-
tc_printf(target, "CRC: bank1 0x%08" PRIx32 "\n", crc1);
494+
tc_printf(target, "CRC: 0x%08" PRIx32 "\n", crc1);
536495
return true;
537496
}
538497

@@ -573,6 +532,7 @@ static const struct {
573532
char revision;
574533
} stm32h7rs_revisions[] = {
575534
{0x1003U, 'Y'},
535+
{0x2000U, 'B'},
576536
};
577537

578538
static bool stm32h7rs_cmd_rev(target_s *target, int argc, const char **argv)

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