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remove tms570 flash blocks since they do not work
1 parent fd8080c commit 9351065

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2 files changed

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-170
lines changed

2 files changed

+0
-170
lines changed

‎src/command.c‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -574,19 +574,6 @@ static bool cmd_halt_timeout(target_s *target, int argc, const char **argv)
574574
return true;
575575
}
576576

577-
static bool cmd_reset_halt(target_s *target, int argc, const char **argv)
578-
{
579-
(void)target;
580-
uint32_t pulse_len_ms = 0;
581-
if (argc > 1)
582-
pulse_len_ms = strtoul(argv[1], NULL, 0);
583-
target_list_free();
584-
platform_nrst_set_val(true);
585-
platform_delay(pulse_len_ms);
586-
platform_nrst_set_val(false);
587-
return true;
588-
}
589-
590577
static bool cmd_reset(target_s *target, int argc, const char **argv)
591578
{
592579
(void)target;

‎src/target/ti_tms570.c‎

Lines changed: 0 additions & 157 deletions
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,6 @@
4444
/*
4545
* Flash functions
4646
*/
47-
static bool tms570_flash_erase(target_flash_s *flash, target_addr_t addr, size_t len);
48-
static bool tms570_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len);
49-
static bool tms570_flash_prepare(target_flash_s *flash);
50-
static bool tms570_flash_done(target_flash_s *flash);
51-
static bool tms570_flash_initialize(target_s *const target);
5247

5348
bool ti_tms570_probe(target_s *const target)
5449
{
@@ -67,155 +62,3 @@ bool ti_tms570_probe(target_s *const target)
6762

6863
return true;
6964
}
70-
71-
static uint32_t accumulate(uint32_t arg, const uint32_t val)
72-
{
73-
arg += (val & 0xffffU);
74-
return (arg & 0xffffU) + (arg >> 16);
75-
}
76-
77-
/// The flash configuration data is burned into a special OTP block on the target.
78-
/// This data is hashed with a Fletcher checksum, which has the nice property that
79-
/// it can tell us if the endianness is backwards or if we're not talking to the
80-
/// correct device. The checksum value is stored in the last word of the OTP area.
81-
static bool fletcher_checksum(const uint32_t *const otp_data, const size_t otp_data_count, const uint32_t comparison)
82-
{
83-
uint32_t check_low = 0xffffU;
84-
uint32_t check_high = 0xffffU;
85-
86-
for (size_t i = 0; i < otp_data_count; i++) {
87-
uint32_t word = otp_data[i];
88-
// Accumulate low word
89-
check_low = accumulate(check_low, word);
90-
check_high = accumulate(check_high, check_low);
91-
// Accumulate high word
92-
check_low = accumulate(check_low, word >> 16);
93-
check_high = accumulate(check_high, check_low);
94-
}
95-
96-
uint32_t result = (check_high << 16) | check_low;
97-
DEBUG_TARGET("Comparing result %08" PRIx32 " to check value %08" PRIx32 "\n", result, comparison);
98-
return comparison == result;
99-
}
100-
101-
static bool tms570_flash_initialize(target_s *const target)
102-
{
103-
if (target->tms570_flash_initialized)
104-
return true;
105-
DEBUG_TARGET("Initializing flash...\n");
106-
107-
// Read the OTP data out of flash. This is protected with a Fletcher checksum
108-
uint32_t otp_data[12];
109-
for (int i = 0; i < 12; i++) {
110-
const uint32_t value = target_mem32_read32(target, TMS570_FLASH_OTP_BASE + (i * 4));
111-
otp_data[i] = read_be4((const uint8_t *)&value, 0);
112-
DEBUG_TARGET("Flash OTP[0x%08" PRIx32 "]: 0x%08" PRIx32 "\n", TMS570_FLASH_OTP_BASE + (i * 4), otp_data[i]);
113-
}
114-
if (!fletcher_checksum(otp_data, 11, otp_data[11])) {
115-
return false;
116-
}
117-
118-
// Enable all three banks
119-
const uint32_t fmac = target_mem32_read32(target, TMS570_L2FMC_FMAC_ADDR);
120-
target_mem32_write32(target, TMS570_L2FMC_FMAC_ADDR, fmac | 7);
121-
122-
// Disable read margin control.
123-
// (Note: previously this set RMBSEL first and then RM0/1, but do both in one write now)
124-
target_mem32_write32(target, TMS570_L2FMC_FSPRD_ADDR, 0);
125-
126-
// Disable the FSM
127-
target_mem32_write32(target, TMS570_L2FMC_FSM_WR_ENA_ADDR, 0);
128-
129-
// Copy some timing values from OTP
130-
const uint32_t unk_210 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x210);
131-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x210, (unk_210 & 0xffff0000) | (otp_data[0] >> 16));
132-
const uint32_t unk_218 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x218);
133-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x218, (unk_218 & 0xffff0000) | (otp_data[0] & 0xffff));
134-
135-
// Set the 2nd nibble after the first write is completed
136-
const uint32_t unk_21c = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x21c);
137-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x21c, (unk_21c & 0xffff00f0) | (otp_data[1] & 0xff0f));
138-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x21c, (unk_21c & 0xffff0000) | (otp_data[1] & 0xffff));
139-
140-
// ???
141-
const uint32_t unk_214 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x214);
142-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x214, (unk_214 & 0xffff0fff) | (otp_data[3] & 0xf000));
143-
144-
// ???
145-
const uint32_t unk_220 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x220);
146-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x220, (unk_220 & 0xffffff00) | ((otp_data[1] >> 24) & 0xff));
147-
148-
// ???
149-
const uint32_t unk_224 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x224);
150-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x224, (unk_224 & 0xffffff00) | ((otp_data[2] >> 16) & 0xff));
151-
152-
// ???
153-
const uint32_t unk_268 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x268);
154-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x268, (unk_268 & 0xfffff000) | (otp_data[5] & 0xfff));
155-
156-
// ???
157-
const uint32_t unk_26c = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x26c);
158-
target_mem32_write16(
159-
target, TMS570_L2FMC_BASE_ADDR + 0x26c, (unk_26c & 0xfe00ffff) | ((otp_data[8] & 0x1ff) << 16));
160-
161-
// NOTE: This used to be a 16-bit access -- ensure that it's properly swapped
162-
const uint32_t unk_270 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x270);
163-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x270, unk_270 & 0xfe00ffff);
164-
165-
const uint32_t unk_278 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x278);
166-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x278, (unk_278 & 0xffffff80) | ((otp_data[4] - 1) & 0x7f));
167-
168-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x27c, 0x4500);
169-
170-
// Unlock L2FMC
171-
target_mem32_write32(target, TMS570_L2FMC_FLOCK_ADDR, 0x55aa);
172-
173-
const uint32_t fvreadct = target_mem32_read32(target, TMS570_L2FMC_FVREADCT_ADDR);
174-
target_mem32_write32(target, TMS570_L2FMC_FVREADCT_ADDR, (fvreadct & 0xfffffff0) | ((otp_data[10] >> 8) & 0xf));
175-
176-
target_mem32_write32(target, TMS570_L2FMC_FVNVCT_ADDR, 0);
177-
178-
target_mem32_write32(target, TMS570_L2FMC_FBSTROBES_ADDR, 0x00010104);
179-
target_mem32_write32(target, TMS570_L2FMC_FPSTROBES_ADDR, 0x103);
180-
target_mem32_write32(target, TMS570_L2FMC_FBMODE_ADDR, 0);
181-
182-
const uint32_t ftcr = target_mem32_read32(target, TMS570_L2FMC_FTCR_ADDR);
183-
target_mem32_write32(target, TMS570_L2FMC_FTCR_ADDR, ftcr & 0xffffff80);
184-
185-
const uint32_t fvppct = target_mem32_read32(target, TMS570_L2FMC_FVPPCT_ADDR);
186-
target_mem32_write32(target, TMS570_L2FMC_FVPPCT_ADDR,
187-
(fvppct & 0xffffe0e0) | (((otp_data[9] >> 8) & 0x1f) << 8) | (otp_data[9] & 0x1f));
188-
189-
const uint32_t fvwlct = target_mem32_read32(target, TMS570_L2FMC_FVWLCT_ADDR);
190-
target_mem32_write32(target, TMS570_L2FMC_FVWLCT_ADDR, (fvwlct & ~0xf000) | ((otp_data[10] >> 24) & 0xf) << 12);
191-
192-
const uint32_t fefuse = target_mem32_read32(target, TMS570_L2FMC_FEFUSE_ADDR);
193-
target_mem32_write32(target, TMS570_L2FMC_FEFUSE_ADDR, (fefuse & 0xffffffe0) | ((otp_data[10] >> 16) & 0x1f));
194-
195-
const uint32_t unk_a8 = target_mem32_read32(target, TMS570_L2FMC_BASE_ADDR + 0x0a8);
196-
target_mem32_write32(target, TMS570_L2FMC_BASE_ADDR + 0x0a8, (unk_a8 & 0xffffff00) | ((otp_data[3] >> 16) & 0xff));
197-
198-
target_mem32_write32(target, TMS570_L2FMC_FPSTROBES_ADDR, 0x103);
199-
200-
target_mem32_write32(target, TMS570_L2FMC_FBSTROBES_ADDR, 0x10104);
201-
202-
// Reads as 0x55aa
203-
target_mem32_write32(target, TMS570_L2FMC_FLOCK_ADDR, 0);
204-
205-
// Re-enable the FSM
206-
const uint32_t fsm = target_mem32_read32(target, TMS570_L2FMC_FSM_WR_ENA_ADDR);
207-
target_mem32_write32(target, TMS570_L2FMC_FSM_WR_ENA_ADDR, (fsm & 0xfffffff8) | 2);
208-
209-
target->tms570_flash_initialized = true;
210-
return true;
211-
}
212-
213-
static bool tms570_flash_prepare(target_flash_s *flash)
214-
{
215-
target_s *const target = flash->t;
216-
217-
if (!tms570_flash_initialize(target)) {
218-
DEBUG_ERROR("Unable to initialize flash!");
219-
return false;
220-
}
221-
}

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