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Merge commit '17658dbedd94' from llvm.org/release/21.x into stable/21.x
2 parents 0e0f577 + 17658db commit 6b439ca

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llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

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@@ -1640,6 +1640,15 @@ bool HexagonDAGToDAGISel::DetectUseSxtw(SDValue &N, SDValue &R) {
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R = N;
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break;
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}
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case ISD::AssertSext: {
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EVT T = cast<VTSDNode>(N.getOperand(1))->getVT();
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if (T.getSizeInBits() == 32)
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R = N.getOperand(0);
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else
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return false;
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break;
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}
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default:
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return false;
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}
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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; CHECK-NOT: r{{[0-9]+}} = asr(r{{[0-9]+}},#{{[0-9]+}})
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; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = mpyu(r{{[0-9]+}},r{{[0-9]+}})
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; CHECK-NOT: r{{[0-9]+}} += mpyi(r{{[0-9]+}},r{{[0-9]+}})
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = mpy(r{{[0-9]+}},r{{[0-9]+}})
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; ModuleID = '39544.c'
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source_filename = "39544.c"
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define dso_local void @mul_n(i64* nocapture %p, i32* nocapture readonly %a, i32 %k, i32 %n) local_unnamed_addr {
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entry:
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%cmp7 = icmp sgt i32 %n, 0
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br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%conv1 = sext i32 %k to i64
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.lr.ph
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%arrayidx.phi = phi i32* [ %a, %for.body.lr.ph ], [ %arrayidx.inc, %for.body ]
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%arrayidx2.phi = phi i64* [ %p, %for.body.lr.ph ], [ %arrayidx2.inc, %for.body ]
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%i.08 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
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%0 = load i32, i32* %arrayidx.phi, align 4
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%conv = sext i32 %0 to i64
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%mul = mul nsw i64 %conv, %conv1
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store i64 %mul, i64* %arrayidx2.phi, align 8
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%inc = add nuw nsw i32 %i.08, 1
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%exitcond = icmp eq i32 %inc, %n
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%arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
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%arrayidx2.inc = getelementptr i64, i64* %arrayidx2.phi, i32 1
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}

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