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[LV] Add test for preserving common GEP flags.
Add additional test coverage for preserving poison generating flags. Modernize the existing flags tests with auto-generated check lines.
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  • llvm/test/Transforms/LoopVectorize

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+194
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‎llvm/test/Transforms/LoopVectorize/flags.ll‎

Lines changed: 194 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -1,77 +1,217 @@
1-
; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-interleave=1 -force-vector-width=4 -S | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
2+
; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S | FileCheck %s
23

3-
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
4-
5-
;CHECK-LABEL: @flags1(
6-
;CHECK: load <4 x i32>
7-
;CHECK: mul nsw <4 x i32>
8-
;CHECK: store <4 x i32>
9-
;CHECK: ret i32
10-
define i32 @flags1(i32 %n, ptr nocapture %A) nounwind uwtable ssp {
11-
%1 = icmp sgt i32 %n, 9
12-
br i1 %1, label %.lr.ph, label %._crit_edge
4+
define void @flags1(i64 %n, ptr nocapture %A) {
5+
; CHECK-LABEL: define void @flags1(
6+
; CHECK-SAME: i64 [[N:%.*]], ptr captures(none) [[A:%.*]]) {
7+
; CHECK-NEXT: [[ENTRY:.*]]:
8+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
9+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
10+
; CHECK: [[VECTOR_PH]]:
11+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
12+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
13+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
14+
; CHECK: [[VECTOR_BODY]]:
15+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
16+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
17+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
18+
; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD]], splat (i32 3)
19+
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[TMP0]], align 4
20+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
21+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
22+
; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
23+
; CHECK: [[MIDDLE_BLOCK]]:
24+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
25+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
26+
; CHECK: [[SCALAR_PH]]:
27+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
28+
; CHECK-NEXT: br label %[[LOOP:.*]]
29+
; CHECK: [[LOOP]]:
30+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
31+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
32+
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
33+
; CHECK-NEXT: [[TMP5:%.*]] = mul nsw i32 [[TMP4]], 3
34+
; CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 4
35+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
36+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
37+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
38+
; CHECK: [[EXIT]]:
39+
; CHECK-NEXT: ret void
40+
;
41+
entry:
42+
br label %loop
1343

14-
.lr.ph: ; preds = %0, %.lr.ph
15-
%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 9, %0 ]
16-
%2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
44+
loop:
45+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
46+
%2 = getelementptr inbounds i32, ptr %A, i64 %iv
1747
%3 = load i32, ptr %2, align 4
1848
%4 = mul nsw i32 %3, 3
1949
store i32 %4, ptr %2, align 4
20-
%indvars.iv.next = add i64 %indvars.iv, 1
21-
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
22-
%exitcond = icmp eq i32 %lftr.wideiv, %n
23-
br i1 %exitcond, label %._crit_edge, label %.lr.ph
50+
%iv.next = add i64 %iv, 1
51+
%ec = icmp eq i64 %iv.next, %n
52+
br i1 %ec, label %exit, label %loop
2453

25-
._crit_edge: ; preds = %.lr.ph, %0
26-
ret i32 undef
54+
exit:
55+
ret void
2756
}
2857

58+
define void @flags2(i64 %n, ptr %A) {
59+
; CHECK-LABEL: define void @flags2(
60+
; CHECK-SAME: i64 [[N:%.*]], ptr [[A:%.*]]) {
61+
; CHECK-NEXT: [[ENTRY:.*]]:
62+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
63+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
64+
; CHECK: [[VECTOR_PH]]:
65+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
66+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
67+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
68+
; CHECK: [[VECTOR_BODY]]:
69+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
70+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
71+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
72+
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[WIDE_LOAD]], splat (i32 3)
73+
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[TMP0]], align 4
74+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
75+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
76+
; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
77+
; CHECK: [[MIDDLE_BLOCK]]:
78+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
79+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
80+
; CHECK: [[SCALAR_PH]]:
81+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
82+
; CHECK-NEXT: br label %[[LOOP:.*]]
83+
; CHECK: [[LOOP]]:
84+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
85+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
86+
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
87+
; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 3
88+
; CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 4
89+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
90+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
91+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
92+
; CHECK: [[EXIT]]:
93+
; CHECK-NEXT: ret void
94+
;
95+
entry:
96+
br label %loop
2997

30-
;CHECK-LABEL: @flags2(
31-
;CHECK: load <4 x i32>
32-
;CHECK: mul <4 x i32>
33-
;CHECK: store <4 x i32>
34-
;CHECK: ret i32
35-
define i32 @flags2(i32 %n, ptr nocapture %A) nounwind uwtable ssp {
36-
%1 = icmp sgt i32 %n, 9
37-
br i1 %1, label %.lr.ph, label %._crit_edge
38-
39-
.lr.ph: ; preds = %0, %.lr.ph
40-
%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 9, %0 ]
41-
%2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
98+
loop:
99+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
100+
%2 = getelementptr inbounds i32, ptr %A, i64 %iv
42101
%3 = load i32, ptr %2, align 4
43102
%4 = mul i32 %3, 3
44103
store i32 %4, ptr %2, align 4
45-
%indvars.iv.next = add i64 %indvars.iv, 1
46-
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
47-
%exitcond = icmp eq i32 %lftr.wideiv, %n
48-
br i1 %exitcond, label %._crit_edge, label %.lr.ph
104+
%iv.next = add i64 %iv, 1
105+
%ec = icmp eq i64 %iv.next, %n
106+
br i1 %ec, label %exit, label %loop
49107

50-
._crit_edge: ; preds = %.lr.ph, %0
51-
ret i32 undef
108+
exit:
109+
ret void
52110
}
53111

54112
; Make sure we copy fast math flags and use them for the final reduction.
55-
; CHECK-LABEL: fast_math
56-
; CHECK: load <4 x float>
57-
; CHECK: fadd fast <4 x float>
58-
; CHECK: br
59-
; CHECK: call fast float @llvm.vector.reduce.fadd.v4f32
60113
define float @fast_math(ptr noalias %s) {
114+
; CHECK-LABEL: define float @fast_math(
115+
; CHECK-SAME: ptr noalias [[S:%.*]]) {
116+
; CHECK-NEXT: [[ENTRY:.*:]]
117+
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
118+
; CHECK: [[VECTOR_PH]]:
119+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
120+
; CHECK: [[VECTOR_BODY]]:
121+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
122+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ]
123+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds float, ptr [[S]], i64 [[INDEX]]
124+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
125+
; CHECK-NEXT: [[TMP1]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]
126+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
127+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
128+
; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
129+
; CHECK: [[MIDDLE_BLOCK]]:
130+
; CHECK-NEXT: [[TMP3:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP1]])
131+
; CHECK-NEXT: br label %[[EXIT:.*]]
132+
; CHECK: [[SCALAR_PH]]:
133+
; CHECK-NEXT: br label %[[LOOP:.*]]
134+
; CHECK: [[LOOP]]:
135+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
136+
; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[LOOP]] ]
137+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[S]], i64 [[IV]]
138+
; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[ARRAYIDX]], align 4
139+
; CHECK-NEXT: [[ADD]] = fadd fast float [[RED]], [[TMP4]]
140+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
141+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 256
142+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
143+
; CHECK: [[EXIT]]:
144+
; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[LOOP]] ], [ [[TMP3]], %[[MIDDLE_BLOCK]] ]
145+
; CHECK-NEXT: ret float [[ADD_LCSSA]]
146+
;
61147
entry:
62-
br label %for.body
148+
br label %loop
63149

64-
for.body:
65-
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
66-
%q.04 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
67-
%arrayidx = getelementptr inbounds float, ptr %s, i64 %indvars.iv
150+
loop:
151+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
152+
%red = phi float [ 0.000000e+00, %entry ], [ %add, %loop ]
153+
%arrayidx = getelementptr inbounds float, ptr %s, i64 %iv
68154
%0 = load float, ptr %arrayidx, align 4
69-
%add = fadd fast float %q.04, %0
70-
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
71-
%exitcond = icmp eq i64 %indvars.iv.next, 256
72-
br i1 %exitcond, label %for.end, label %for.body
155+
%add = fadd fast float %red, %0
156+
%iv.next = add nuw nsw i64 %iv, 1
157+
%ec = icmp eq i64 %iv.next, 256
158+
br i1 %ec, label %exit, label %loop
73159

74-
for.end:
75-
%add.lcssa = phi float [ %add, %for.body ]
160+
exit:
161+
%add.lcssa = phi float [ %add, %loop ]
76162
ret float %add.lcssa
77163
}
164+
165+
define void @gep_with_shared_nusw_and_others(i64 %n, ptr %A) {
166+
; CHECK-LABEL: define void @gep_with_shared_nusw_and_others(
167+
; CHECK-SAME: i64 [[N:%.*]], ptr [[A:%.*]]) {
168+
; CHECK-NEXT: [[ENTRY:.*]]:
169+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
170+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
171+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
172+
; CHECK: [[VECTOR_PH]]:
173+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4
174+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
175+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
176+
; CHECK: [[VECTOR_BODY]]:
177+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
178+
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
179+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
180+
; CHECK-NEXT: store <4 x float> [[WIDE_LOAD]], ptr [[TMP1]], align 4
181+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
182+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
183+
; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
184+
; CHECK: [[MIDDLE_BLOCK]]:
185+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
186+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
187+
; CHECK: [[SCALAR_PH]]:
188+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
189+
; CHECK-NEXT: br label %[[LOOP:.*]]
190+
; CHECK: [[LOOP]]:
191+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
192+
; CHECK-NEXT: [[GEP_NUSW:%.*]] = getelementptr nusw float, ptr [[A]], i64 [[IV]]
193+
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_NUSW]], align 4
194+
; CHECK-NEXT: [[GEP_NUSW_NUW:%.*]] = getelementptr nusw nuw float, ptr [[A]], i64 [[IV]]
195+
; CHECK-NEXT: store float [[L]], ptr [[GEP_NUSW_NUW]], align 4
196+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
197+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
198+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
199+
; CHECK: [[EXIT]]:
200+
; CHECK-NEXT: ret void
201+
;
202+
entry:
203+
br label %loop
204+
205+
loop:
206+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
207+
%gep.nusw = getelementptr nusw float, ptr %A, i64 %iv
208+
%l = load float, ptr %gep.nusw, align 4
209+
%gep.nusw.nuw = getelementptr nusw nuw float, ptr %A, i64 %iv
210+
store float %l, ptr %gep.nusw.nuw, align 4
211+
%iv.next = add i64 %iv, 1
212+
%ec = icmp eq i64 %iv, %n
213+
br i1 %ec, label %exit, label %loop
214+
215+
exit:
216+
ret void
217+
}

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