x2APIC support for when its forced on us by firmware

Author: braindigitalis

include/acpi.h

@@ -92,6 +92,12 @@ typedef struct {
  */
 #define IRQ_DEFAULT_TRIGGER  0
 
+/**
+ * @brief Returned from @ref get_cpu_id_from_lapic_id if the CPUid
+ * passed in does not map to a logical CPU id.
+ */
+#define INVALID_CPU_ID 255
+
 /**
  * @brief Indicates the source of a PCI IRQ route.
  */
@@ -208,4 +214,8 @@ const char *polarity_str(uint8_t pol);
  */
 const char *sharing_str(uint8_t share);
 
+/**
+ * Main entrypoint for an SMP AP
+ * @param info limine CPU info
+ */
 void kmain_ap(struct limine_smp_info *info);

include/apic.h

@@ -28,35 +28,92 @@
 #define APIC_VERSION   0x0030  /**< LAPIC Version Register (read-only) */
 
 /**
- * @brief Read a 32-bit value from a LAPIC register
+ * @brief Read a Local APIC register.
  *
- * @param reg Register offset from LAPIC base
- * @return uint32_t The value read from the register
+ * Works in both xAPIC and x2APIC modes:
+ * - In xAPIC mode, the register is memory‑mapped at the LAPIC base address.
+ * - In x2APIC mode, registers are accessed via MSRs at 0x800 + (reg >> 4).
+ *
+ * @param reg Register offset (e.g. APIC_EOI = 0xB0).
+ * @return uint32_t Value read from the register.
  */
 uint32_t apic_read(uint64_t reg);
 
 /**
- * @brief Write a 32-bit value to a LAPIC register
+ * @brief Write to a Local APIC register.
+ *
+ * Works in both xAPIC and x2APIC modes:
+ * - In xAPIC mode, the register is memory‑mapped at the LAPIC base address.
+ * - In x2APIC mode, registers are written via MSRs at 0x800 + (reg >> 4).
  *
- * @param reg Register offset from LAPIC base
- * @param value The value to write
+ * @param reg Register offset (e.g. APIC_EOI = 0xB0).
+ * @param val Value to write.
  */
 void apic_write(uint64_t reg, uint32_t value);
 
 /**
- * @brief Get the Local APIC ID of the current CPU
+ * @brief Get the Local APIC ID of the current CPU.
+ *
+ * In xAPIC mode this is an 8-bit value read from the LAPIC ID register.
+ * In x2APIC mode this is a 32-bit value read from MSR 0x802.
+ *
+ * @return uint32_t LAPIC ID of the current CPU.
+ * @note LAPIC IDs are assigned by hardware/firmware and may be
+ *       sparse, non-contiguous, or not zero-based.
+ */
+uint32_t cpu_id(void);
+
+/**
+ * @brief Get the OS-assigned logical CPU ID of the current CPU.
+ *
+ * Logical CPU IDs are zero-based, contiguous indices used internally
+ * by the kernel. They are mapped to LAPIC IDs via cpu_id_mapping[].
+ *
+ * @return uint8_t Logical CPU ID of the current CPU.
+ */
+uint8_t logical_cpu_id(void);
+
+/**
+ * @brief Get the physical address of the Local APIC MMIO region.
  *
- * @return uint8_t APIC ID read from the LAPIC ID register.
- * This value uniquely identifies the core in an SMP system and
- * may be non-contiguous or BIOS-assigned.
+ * This is only valid when xAPIC mode is active. In x2APIC mode,
+ * LAPIC registers are accessed via MSRs instead of MMIO.
+ *
+ * @return uint64_t Physical address of the LAPIC MMIO base.
+ */
+uint64_t get_lapic_address(void);
+
+/**
+ * @brief Determine if x2APIC mode is enabled.
+ *
+ * Checks both CPUID feature flags and the IA32_APIC_BASE MSR to confirm
+ * whether x2APIC is active.
+ *
+ * @return int Non-zero if x2APIC mode is enabled, zero otherwise.
  */
-uint8_t cpu_id();
+int x2apic_enabled(void);
 
+/**
+ * @brief Read a 64-bit Model Specific Register (MSR).
+ *
+ * @param msr The MSR address to read.
+ * @return uint64_t The value read from the MSR.
+ */
+uint64_t rdmsr(uint32_t msr);
 
 /**
- * @brief Get the physical address of the Local APIC
+ * @brief Map a logical CPU ID to its LAPIC ID.
  *
- * @return uint64_t Physical address of the LAPIC MMIO region
+ * @param cpu_id Logical CPU ID (zero-based, kernel-assigned).
+ * @return uint32_t LAPIC ID for the given logical CPU ID.
  */
-uint64_t get_lapic_address();
+uint32_t get_lapic_id_from_cpu_id(uint8_t cpu_id);
 
+/**
+ * @brief Map a LAPIC ID to its logical CPU ID.
+ *
+ * @param lapic_id LAPIC ID as reported by hardware.
+ * @return uint8_t Logical CPU ID assigned to this LAPIC ID,
+ *                 or 255 if unmapped.
+ */
+uint8_t get_cpu_id_from_lapic_id(uint32_t lapic_id);

include/idt.h

@@ -5,8 +5,6 @@
  */
 #pragma once
 
-#include <kernel.h>
-
 #define USE_IOAPIC
 
 typedef struct idt_ptr_t {
@@ -26,6 +24,27 @@ typedef struct idt_entry_t {
 
 extern volatile idt_ptr_t idt64;
 
+/**
+ * @note MAX_CPUS is set to 256 (not the expected physical core count).
+ *
+ * Local APIC IDs in xAPIC mode are 8-bit fields (0–255). These IDs are not
+ * guaranteed to be sequential, zero-based, or densely packed. Some systems
+ * leave gaps in the LAPIC ID space, and the bootstrap processor (BSP) may
+ * not be assigned LAPIC ID 0.
+ *
+ * In x2APIC mode, APIC IDs extend to 32 bits. If firmware enables x2APIC
+ * before handoff, we accept it and operate in that mode, but we currently
+ * only initialise CPUs whose LAPIC IDs are <= 254. LAPIC ID 255 is reserved
+ * for broadcast and never used. Any CPUs with IDs above 254 are ignored.
+ *
+ * By sizing arrays to 256, we can index directly by LAPIC ID without needing
+ * a LAPIC→OS CPU remapping table. This simplifies per‑CPU structures at the
+ * cost of a small amount of extra memory. Future support for >254 LAPIC IDs
+ * may require remapping or dynamic allocation.
+ */
+#define MAX_CPUS 256
+
+
 /**
  * @brief Function pointer type for interrupt and IRQ handlers.
  *

include/pci.h

@@ -278,14 +278,13 @@ bool pci_enable_msix(pci_dev_t device, uint32_t vector, uint16_t entry, uint32_t
  *
  * @param name     Human-readable device name (used in logs/debug output).
  * @param dev      The PCI device handle.
- * @param lapic_id Local APIC ID of the target CPU that should receive the
- *                 interrupt.
+ * @param logical_cpu_id Logical CPU ID of the target CPU that should receive the interrupt.
  * @param handler  Interrupt service routine to register.
  * @param context  Opaque pointer passed to the ISR when the interrupt fires.
  *
- * @warning The lapic_id parameter must be a valid Local APIC ID
+ * @warning The lapic_id parameter must be a valid logical ID
  *          corresponding to an online CPU. Passing an invalid or
- *          offline APIC ID will result in undefined behaviour and
+ *          offline CPU ID will result in undefined behaviour and
  *          may cause interrupts to be lost.
  *
  * @return The assigned interrupt vector (64–255 if MSI/MSI-X was used,
@@ -294,4 +293,4 @@ bool pci_enable_msix(pci_dev_t device, uint32_t vector, uint16_t entry, uint32_t
  * @note Drivers should always check the returned vector to confirm which
  *       interrupt mechanism was actually configured.
  */
-uint32_t pci_setup_interrupt(const char* name, pci_dev_t dev, uint8_t lapic_id, isr_t handler, void *context);
+uint32_t pci_setup_interrupt(const char* name, pci_dev_t dev, uint8_t logical_cpu_id, isr_t handler, void *context);

src/acpi.c

@@ -22,11 +22,29 @@ static uint8_t ioapic_gsi_count[256] = {0};
 
 pci_irq_route_t pci_irq_routes[MAX_PCI_ROUTES] = {};
 
+uint32_t cpu_id_mapping[MAX_CPUS] = { 0 };
 
 uint64_t mhz = 0, tsc_per_sec = 1;
 
 void enumerate_all_gsis(void);
 
+uint32_t get_lapic_id_from_cpu_id(uint8_t cpu_id) {
+	return cpu_id_mapping[cpu_id];
+}
+
+uint8_t get_cpu_id_from_lapic_id(uint32_t lapic_id) {
+	for (uint8_t x = 0; x < MAX_CPUS - 1; ++x) {
+		if (cpu_id_mapping[x] == lapic_id) {
+			return x;
+		}
+	}
+	return INVALID_CPU_ID;
+}
+
+void set_lapic_id_for_cpu_id(uint8_t cpu_id, uint32_t lapic_id) {
+	cpu_id_mapping[cpu_id] = lapic_id;
+}
+
 void init_uacpi(void) {
 	uacpi_status st;
 
@@ -201,10 +219,21 @@ void init_cores() {
 			return;
 		}
 
-		for (uint64_t i = 0; i < smp_request.response->cpu_count; i++) {
+		uint64_t limit = smp_request.response->cpu_count;
+		if (limit > MAX_CPUS - 1) {
+			kprintf("WARNING: Your system has more than 254 CPUs; only 254 will be enabled\n");
+			limit = MAX_CPUS - 1;
+		}
+		for (uint64_t i = 0; i < limit; i++) {
 			struct limine_smp_info *cpu = smp_request.response->cpus[i];
-			if (cpu->lapic_id == smp_request.response->bsp_lapic_id) {
-				continue; // Skip BSP
+			if (cpu->processor_id < 255) {
+				set_lapic_id_for_cpu_id(cpu->processor_id, cpu->lapic_id);
+			}
+			if (cpu->lapic_id == smp_request.response->bsp_lapic_id || cpu->processor_id > 254) {
+				// Skip BSP and IDs over 254 (255 is broadcast, 256+ are too big for our array)
+				continue;
+			} else if (cpu->lapic_id == smp_request.response->bsp_lapic_id) {
+				kprintf("CPU: %d online; ID: %d\n", cpu->processor_id, cpu->lapic_id);
 			}
 			cpu->goto_address = kmain_ap;
 		}

src/ahci.c

@@ -594,7 +594,7 @@ void init_ahci()
 	}
 
 	ahci_base = pci_mem_base(ahci_base);
-	uint32_t irq_num = pci_setup_interrupt("AHCI", ahci_device, cpu_id(), ahci_handler, ahci_base);
+	uint32_t irq_num = pci_setup_interrupt("AHCI", ahci_device, logical_cpu_id(), ahci_handler, ahci_base);
 	dprintf("AHCI base MMIO: %08x INT %d\n", ahci_base, irq_num);
 
 	probe_port((ahci_hba_mem_t*)ahci_base, ahci_device);

src/apic.c

@@ -1,39 +1,90 @@
- #include <kernel.h>
+#include <kernel.h>
+#include <cpuid.h>
+
+#define IA32_APIC_BASE_MSR 0x1B
+#define APIC_BASE_X2APIC_ENABLE (1ULL << 10)
 
  static uint64_t saved_lapic = 0;
 
  uint64_t get_lapic_address() {
-	 if (saved_lapic) {
-		 return saved_lapic;
+	if (saved_lapic) {
+		return saved_lapic;
 	}
-	 uint32_t eax, edx;
-	 __asm__ volatile (
-		 "rdmsr"
-		 : "=a"(eax), "=d"(edx)
-		 : "c"(0x1B)  // APIC_BASE_MSR
-		 );
-	 uint64_t result = ((uint64_t)edx << 32) | eax;
-	 result &= 0xFFFFFFFFFFFFF000ULL;
-	 saved_lapic = result;
-	 return result;
- }
+	uint32_t eax, edx;
+	__asm__ volatile (
+		"rdmsr"
+		: "=a"(eax), "=d"(edx)
+		: "c"(0x1B)  // APIC_BASE_MSR
+		);
+	uint64_t result = ((uint64_t)edx << 32) | eax;
+	result &= 0xFFFFFFFFFFFFF000ULL;
+	saved_lapic = result;
+	return result;
+}
+
+static inline void wrmsr(uint32_t msr, uint64_t value) {
+	uint32_t lo = (uint32_t)value;
+	uint32_t hi = (uint32_t)(value >> 32);
+	__asm__ volatile ("wrmsr"
+		:
+		: "c"(msr), "a"(lo), "d"(hi));
+}
 
-uint32_t apic_read(uint64_t reg)
-{
-	uint64_t lapic = get_lapic_address();
-	uint32_t res = *((volatile uint32_t *)(lapic + reg));
-	return res;
+
+void apic_write(uint64_t reg, uint32_t val) {
+	if (x2apic_enabled()) {
+		wrmsr(0x800 + (reg >> 4), val);
+	} else {
+		uint64_t lapic_base = get_lapic_address();
+		*(volatile uint32_t *)(lapic_base + reg) = val;
+	}
 }
 
-void apic_write(uint64_t reg, uint32_t value)
-{
-	uint64_t lapic = get_lapic_address();
-	*((volatile uint32_t *)(lapic + reg)) = value;
+uint32_t apic_read(uint64_t reg) {
+	if (x2apic_enabled()) {
+		return (uint32_t)rdmsr(0x800 + (reg >> 4));
+	} else {
+		uint64_t lapic_base = get_lapic_address();
+		return *(volatile uint32_t *)(lapic_base + reg);
+	}
 }
 
-uint8_t cpu_id()
-{
-	uint32_t id = apic_read(APIC_ID);
-	id = (id >> 24) & 0xff;
-	return id;
+uint32_t cpu_id(void) {
+	if (x2apic_enabled()) {
+		// x2APIC: full 32-bit ID from MSR 0x802
+		return (uint32_t)rdmsr(0x802);
+	} else {
+		// xAPIC: 8-bit ID from MMIO register (0x20 >> 24)
+		return (apic_read(APIC_ID) >> 24) & 0xFF;
+	}
 }
+
+uint8_t logical_cpu_id(void) {
+	return get_cpu_id_from_lapic_id(cpu_id());
+}
+
+uint64_t rdmsr(uint32_t msr) {
+	uint32_t lo, hi;
+	__asm__ volatile ("rdmsr"
+		: "=a"(lo), "=d"(hi)
+		: "c"(msr));
+	return ((uint64_t)hi << 32) | lo;
+}
+
+int x2apic_supported(void) {
+	unsigned int eax, ebx, ecx, edx;
+
+	if (!__get_cpuid(1, &eax, &ebx, &ecx, &edx))
+		return 0;
+
+	return (ecx & (1u << 21)) != 0; // Bit 21 of ECX = x2APIC support
+}
+
+int x2apic_enabled(void) {
+	 if (!x2apic_supported()) {
+		 return 0; // CPU doesn't even support x2APIC
+	 }
+	 // Read APIC base MSR to see if x2APIC mode is active
+	 uint64_t apic_base = rdmsr(IA32_APIC_BASE_MSR);
+	 return (apic_base & APIC_BASE_X2APIC_ENABLE) != 0;
+ }

src/e1000.c

@@ -320,7 +320,7 @@ bool e1000_start(pci_dev_t *pci_device) {
 
 	if (e1000_device_id == E1000_82540EM) {
 		/* Attempting MSI setup is safe here */
-		pci_setup_interrupt("e1000", *pci_device, cpu_id(), e1000_handler, NULL);
+		pci_setup_interrupt("e1000", *pci_device, logical_cpu_id(), e1000_handler, NULL);
 	} else {
 		/* But not here! The 82541PI actively torpedoes the system if you enable MSI, see its errata:
 		 *