Performance engineering

[brainstorm]

Profiling and optimisation are tangentially mentioned towards the end of issue #25, but better tooling/process is needed to maximise the performance of this firmware on different fronts:

1. Choose overall and per-task heap size allocation based on throughput.
2. Choose adequate application buffer sizes for the different interfaces and subsystems.
3. Choose best fitting priorities for the different tasks, both plain embassy tasks and interrupt-driven ones.
4. Optimise the build for size on boards that do not have big(ger) flash sizes. Same for RAM size:
5. Run cargo tree, cargo bloat and i.e harmonize ed25519-compact instead of bigger counterparts, use lightweight crypto primitives and other basic "util" crates across sunset and ssh-stamp.
6. Add CI/CD instrumentation to track all of the above over time, avoiding regressions.
7. Implement SIMD versions of the cryptographic/hashing primitives?
8. Profile hot spots, cryptographic primitives, etc...

Those performance engineering techniques should be appropriatedly documented (preferably with examples) and ideally implemented in CI to monitor regressions.