CX4 cache and bus access timing fixes

- Step 1+WS on both reads for cache, not just one
- Remove extra cycle on bus reads/writes

Author: AkiteruSDA

bsnes/processor/hg51b/hg51b.cpp

@@ -89,6 +89,7 @@ auto HG51B::cache() -> bool {
   for(uint offset : range(256)) {
     step(wait(address));
     programRAM[io.cache.page][offset]  = read(address++) << 0;
+    step(wait(address));
     programRAM[io.cache.page][offset] |= read(address++) << 8;
   }
   return io.cache.enable = 0, true;

bsnes/processor/hg51b/registers.cpp

@@ -12,13 +12,13 @@ auto HG51B::readRegister(uint7 address) -> uint24 {
   case 0x2e:
     io.bus.enable  = 1;
     io.bus.reading = 1;
-    io.bus.pending = 1 + io.wait.rom;
+    io.bus.pending = io.wait.rom;
     io.bus.address = r.mar;
     return 0x000000;
   case 0x2f:
     io.bus.enable  = 1;
     io.bus.reading = 1;
-    io.bus.pending = 1 + io.wait.ram;
+    io.bus.pending = io.wait.ram;
     io.bus.address = r.mar;
     return 0x000000;
 
@@ -76,13 +76,13 @@ auto HG51B::writeRegister(uint7 address, uint24 data) -> void {
   case 0x2e:
     io.bus.enable  = 1;
     io.bus.writing = 1;
-    io.bus.pending = 1 + io.wait.rom;
+    io.bus.pending = io.wait.rom;
     io.bus.address = r.mar;
     return;
   case 0x2f:
     io.bus.enable  = 1;
     io.bus.writing = 1;
-    io.bus.pending = 1 + io.wait.ram;
+    io.bus.pending = io.wait.ram;
     io.bus.address = r.mar;
     return;