update and add testbenches

Author: builderdev212

problems/getting-started/output-zero/tb/constant_zero.py

@@ -1,4 +1,5 @@
 import logging
+from cocotb.clock import Timer
 
 
 class DataError(Exception):
@@ -20,6 +21,7 @@ def get_signals(self):
         self.zero = self.dut.zero
 
     async def zero_check(self):
+        await Timer(1, units="ns")
         if int(self.zero.value) != 0:
             raise DataError(
                 f"Output should always be 0, got {self.zero.value} instead."

problems/getting-started/output-zero/tb/test_constant_zero.py

@@ -1,7 +1,7 @@
 import os
 import pytest
+
 import cocotb
-from cocotb.clock import Timer
 from cocotb.regression import TestFactory
 from cocotb_test.simulator import run
 
@@ -12,8 +12,6 @@ async def output_stays_zero(dut):
     tb = TB(dut)
 
     tb.log.info("Checking output value...")
-    # Await one nanosecond so the model can start.
-    await Timer(1, units="ns")
     tb.zero_check()
 
 

problems/verilog-language/basics/multi-wire/tb/multi_wire.py

@@ -0,0 +1,64 @@
+import logging
+from cocotb.clock import Timer
+
+
+class DataError(Exception):
+    pass
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        # Start logging
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Simulation Signals
+        self.get_signals()
+
+        # Zero out signals
+        self.zero_signals()
+
+    def get_signals(self):
+        self.a = self.dut.a
+        self.b = self.dut.b
+        self.c = self.dut.c
+
+        self.w = self.dut.w
+        self.x = self.dut.x
+        self.y = self.dut.y
+        self.z = self.dut.z
+
+    def zero_signals(self):
+        self.a.value = 0
+        self.b.value = 0
+        self.c.value = 0
+
+    async def set_input_vals(self, val):
+        self.a.value = val[0]
+        self.b.value = val[1]
+        self.c.value = val[2]
+        await Timer(1, units="ns")
+
+    async def is_equal_check(self):
+        await Timer(1, units="ns")
+        if int(self.w.value) != int(self.a.value):
+            raise DataError(
+                f"w and a should be equal, but {self.w.value} != {self.a.value}."
+            )
+
+        if int(self.x.value) != int(self.b.value):
+            raise DataError(
+                f"x and b should be equal, but {self.x.value} != {self.b.value}."
+            )
+
+        if int(self.y.value) != int(self.b.value):
+            raise DataError(
+                f"y and b should be equal, but {self.y.value} != {self.b.value}."
+            )
+
+        if int(self.z.value) != int(self.c.value):
+            raise DataError(
+                f"z and c should be equal, but {self.z.value} != {self.c.value}."
+            )

problems/verilog-language/basics/multi-wire/tb/test_multi_wire.py

@@ -0,0 +1,66 @@
+import os
+import pytest
+
+import cocotb
+from cocotb.regression import TestFactory
+from cocotb_test.simulator import run
+
+from multi_wire import TB
+
+
+async def output_stays_equal(dut):
+    tb = TB(dut)
+
+    test_vals = [
+        [0, 1, 0],
+        [1, 1, 0],
+        [0, 0, 0],
+        [0, 1, 1],
+    ]
+
+    tb.log.info("Checking output value...")
+    
+    for i in range(len(test_vals)):
+        tb.set_input_vals(test_vals[i])
+        tb.is_equal_check()
+
+
+if cocotb.SIM_NAME:
+    test1 = TestFactory(output_stays_equal)
+    test1.generate_tests()
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "rtl"))
+
+parameter_list = [{}]
+
+
+@pytest.mark.parametrize("parameters", parameter_list)
+def test_constant_zero(request, parameters):
+    dut = "multi_wire"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+    ]
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+        compile_args=["--timing", "-O3"],
+        waves=True,
+    )

problems/verilog-language/basics/simple-wire/rtl/simple_wire.v

@@ -3,10 +3,10 @@
 `default_nettype none
 
 module simple_wire (
-    input  wire in,
-    output wire out
+    input  wire i,
+    output wire o
 );
 
-    assign out = in;
+    assign o = i;
 
 endmodule

problems/verilog-language/basics/simple-wire/tb/simple_wire.py

@@ -0,0 +1,39 @@
+import logging
+from cocotb.clock import Timer
+
+
+class DataError(Exception):
+    pass
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        # Start logging
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Simulation Signals
+        self.get_signals()
+
+        # Zero out signals
+        self.zero_signals()
+
+    def get_signals(self):
+        self.i = self.dut.i
+        self.o = self.dut.o
+
+    def zero_signals(self):
+        self.i.value = 0
+
+    async def set_input_val(self, val):
+        self.i.value = val
+        await Timer(1, units="ns")
+
+    async def is_equal_check(self):
+        await Timer(1, units="ns")
+        if int(self.i.value) != int(self.o.value):
+            raise DataError(
+                f"Output should be equal, but {self.i.value} != {self.o.value}."
+            )

problems/verilog-language/basics/simple-wire/tb/test_simple_wire.py

@@ -0,0 +1,61 @@
+import os
+import pytest
+
+import cocotb
+from cocotb.regression import TestFactory
+from cocotb_test.simulator import run
+
+from simple_wire import TB
+
+
+async def output_stays_equal(dut):
+    tb = TB(dut)
+
+    test_vals = [0, 1, 1, 0, 1, 0]
+
+    tb.log.info("Checking output value...")
+    
+    for i in range(len(test_vals)):
+        tb.set_input_val(test_vals[i])
+        tb.is_equal_check()
+
+
+if cocotb.SIM_NAME:
+    test1 = TestFactory(output_stays_equal)
+    test1.generate_tests()
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "rtl"))
+
+parameter_list = [{}]
+
+
+@pytest.mark.parametrize("parameters", parameter_list)
+def test_constant_zero(request, parameters):
+    dut = "simple_wire"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+    ]
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+        compile_args=["--timing", "-O3"],
+        waves=True,
+    )

pytest.ini

@@ -9,3 +9,5 @@ log_file_level = DEBUG
 testpaths =
     problems/getting-started/getting-started/tb/test_constant_one.py
     problems/getting-started/output-zero/tb/test_constant_zero.py
+    problems/verilog-language/basics/simple-wire/tb/test_simple_wire.py
+    problems/verilog-language/basics/multi-wire/tb/test_multi_wire.py