fix test issue, add more hardware, still need to write testbenches

Author: builderdev212

Containerfile

@@ -1,5 +1,5 @@
 # Setup dependancy versions
-ARG DEBIAN_VERSION=12
+ARG DEBIAN_VERSION=12-slim
 
 FROM docker.io/library/debian:${DEBIAN_VERSION}
 
@@ -23,14 +23,7 @@ WORKDIR /usr/src/verilator
 RUN git checkout v${VERILATOR_VERSION}
 RUN autoconf && ./configure && make -j `nproc` && make install
 WORKDIR /usr/src/
- 
-# compile and install iverilog
-WORKDIR /usr/src/
-RUN git clone https://github.com/steveicarus/iverilog.git
-WORKDIR /usr/src/iverilog/
-RUN sh autoconf.sh && ./configure --prefix /usr && make && make install
- 
-WORKDIR /usr/src/
+
 # setup python virtual environment
 ENV VIRTUAL_ENV=.venv
 RUN python3 -m venv ${VIRTUAL_ENV}

problems/getting-started/getting-started/tb/test_constant_one.py

@@ -5,7 +5,7 @@
 from cocotb.regression import TestFactory
 from cocotb_test.simulator import run
 
-from top_module import TB
+from constant_one import TB
 
 
 async def output_stays_one(dut):

problems/getting-started/output-zero/rtl/constant_zero.v

@@ -0,0 +1,11 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module constant_zero (
+    output wire zero
+);
+
+    assign zero = 0;
+
+endmodule

problems/getting-started/output-zero/tb/constant_zero.py

@@ -0,0 +1,24 @@
+import logging
+
+
+class DataError(Exception):
+    pass
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        # Start logging
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Simulation Signals
+        self.get_signals()
+
+    def get_signals(self):
+        self.zero = self.dut.zero
+
+    async def zero_check(self):
+        if int(self.zero.value) != 0:
+            raise DataError(f"Output should always be 0, got {self.zero.value} instead.")

problems/getting-started/output-zero/tb/test_constant_zero.py

@@ -0,0 +1,58 @@
+import os
+import pytest
+import cocotb
+from cocotb.clock import Timer
+from cocotb.regression import TestFactory
+from cocotb_test.simulator import run
+
+from constant_zero import TB
+
+
+async def output_stays_zero(dut):
+    tb = TB(dut)
+
+    tb.log.info("Checking output value...")
+    # Await one nanosecond so the model can start.
+    await Timer(1, units="ns")
+    tb.zero_check()
+
+
+if cocotb.SIM_NAME:
+    test1 = TestFactory(output_stays_zero)
+    test1.generate_tests()
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "rtl"))
+
+parameter_list = [{}]
+
+
+@pytest.mark.parametrize("parameters", parameter_list)
+def test_constant_zero(request, parameters):
+    dut = "constant_zero"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+    ]
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+        compile_args=["--timing", "-O3"],
+        waves=True,
+    )

problems/verilog-language/basics/7458-chip/rtl/7458.v

@@ -0,0 +1,24 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module 7458 ( 
+    input  wire p1a,
+    input  wire p1b,
+    input  wire p1c,
+    input  wire p1d,
+    input  wire p1e,
+    input  wire p1f,
+    output wire p1y,
+
+    input  wire p2a,
+    input  wire p2b,
+    input  wire p2c,
+    input  wire p2d,
+    output wire p2y
+);
+
+    assign p1y = (p1a && p1b && p1c) || (p1d && p1e && p1f);
+    assign p2y = (p2a && p2b) || (p2c && p2d);
+
+endmodule

problems/verilog-language/basics/and-gate/rtl/and_gate.v

@@ -0,0 +1,13 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module and_gate ( 
+    input  wire a, 
+    input  wire b, 
+    output wire out
+);
+
+    assign out = a && b;
+    
+endmodule

problems/verilog-language/basics/declaring-wires/rtl/declaring_wires.v

@@ -0,0 +1,23 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module declaring_wires (
+    input  wire a,
+    input  wire b,
+    input  wire c,
+    input  wire d,
+    output wire out,
+    output wire out_n
+);
+    
+    wire ab;
+    wire cd;
+    
+    assign ab = a && b;
+    assign cd = c && d;
+    
+    assign out = ab || cd;
+    assign out_n = !out;
+
+endmodule

problems/verilog-language/basics/inverter/rtl/not_gate.v

@@ -0,0 +1,12 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module not_gate (
+    input  wire in,
+    output wire out
+);
+
+	assign out = !in;
+
+endmodule

problems/verilog-language/basics/multi-wire/rtl/multi_wire.v

@@ -0,0 +1,18 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module multi_wire ( 
+    input  wire a,
+    input  wire b,
+    input  wire c,
+
+    output wire w,
+    output wire x,
+    output wire y,
+    output wire z
+);
+    
+    assign {w, x, y, z} = {a, b, b, c};
+
+endmodule