add testbenches for the rest of verilog-language/basics hdl

Author: builderdev212

…log-language/basics/7458-chip/rtl/7458.v …og-language/basics/7458-chip/rtl/c7458.vproblems/verilog-language/basics/7458-chip/rtl/7458.v renamed to problems/verilog-language/basics/7458-chip/rtl/c7458.v problems/verilog-language/basics/7458-chip/rtl/7458.v renamed to problems/verilog-language/basics/7458-chip/rtl/c7458.v

@@ -2,7 +2,7 @@
 `timescale 1ns / 1ps
 `default_nettype none
 
-module 7458 ( 
+module c7458 ( 
     input  wire p1a,
     input  wire p1b,
     input  wire p1c,

problems/verilog-language/basics/7458-chip/tb/c7458.py

@@ -0,0 +1,85 @@
+import logging
+from cocotb.clock import Timer
+
+
+class DataError(Exception):
+    pass
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        # Start logging
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Simulation Signals
+        self.get_signals()
+
+        # Zero out signals
+        self.zero_signals()
+
+    def get_signals(self):
+        self.p1a = self.dut.p1a
+        self.p1b = self.dut.p1b
+        self.p1c = self.dut.p1c
+        self.p1d = self.dut.p1d
+        self.p1e = self.dut.p1e
+        self.p1f = self.dut.p1f
+        self.p1y = self.dut.p1y
+
+        self.p2a = self.dut.p2a
+        self.p2b = self.dut.p2b
+        self.p2c = self.dut.p2c
+        self.p2d = self.dut.p2d
+        self.p2y = self.dut.p2y
+
+    def zero_signals(self):
+        self.p1a.value = 0
+        self.p1b.value = 0
+        self.p1c.value = 0
+        self.p1d.value = 0
+        self.p1e.value = 0
+        self.p1f.value = 0
+
+        self.p2a.value = 0
+        self.p2b.value = 0
+        self.p2c.value = 0
+        self.p2d.value = 0
+
+    async def set_p1_input_val(self, val):
+        self.p1a.value = val[0]
+        self.p1b.value = val[1]
+        self.p1c.value = val[2]
+        self.p1d.value = val[3]
+        self.p1e.value = val[4]
+        self.p1f.value = val[5]
+        await Timer(1, units="ns")
+
+    async def p1_logic_check(self):
+        await Timer(1, units="ns")
+        if (
+            (bool(self.p1a.value) and bool(self.p1b.value) and bool(self.p1c.value))
+            or (bool(self.p1d.value) and bool(self.p1e.value) and bool(self.p1f.value))
+        ) != bool(self.p1y.value):
+            raise DataError(
+                f"(p1a && p1b && p1c) || (p1d && p1e && p1f) should be p1y, but ({self.p1a.value} && {self.p1b.value} && {self.p1c.value}) || ({self.p1d.value} && {self.p1e.value} && {self.p1f.value}) != {self.p1y.value}."
+            )
+
+    async def set_p2_input_val(self, val):
+        self.p2a.value = val[0]
+        self.p2b.value = val[1]
+        self.p2c.value = val[2]
+        self.p2d.value = val[3]
+        await Timer(1, units="ns")
+
+    async def p2_logic_check(self):
+        await Timer(1, units="ns")
+        if (
+            (bool(self.p2a.value) and bool(self.p2b.value))
+            or (bool(self.p2d.value) and bool(self.p2e.value))
+        ) != bool(self.p2y.value):
+            raise DataError(
+                f"(p2a && p2b) || (p2c && p2d) should be p2y, but ({self.p2a.value} && {self.p2b.value}) || ({self.p2c.value} && {self.p2d.value}) != {self.p2y.value}."
+            )

problems/verilog-language/basics/7458-chip/tb/test_c7458.py

@@ -0,0 +1,86 @@
+import os
+import pytest
+
+import cocotb
+from cocotb.regression import TestFactory
+from cocotb_test.simulator import run
+
+from c7458 import TB
+
+
+async def p1_logic_check(dut):
+    tb = TB(dut)
+
+    test_vals = [
+        [0, 0, 0, 0, 0, 0],
+        [0, 1, 0, 0, 1, 0],
+        [0, 0, 0, 1, 1, 1],
+        [1, 1, 0, 1, 0, 1],
+        [1, 1, 1, 1, 1, 1],
+    ]
+
+    tb.log.info("Checking output value...")
+
+    for i in range(len(test_vals)):
+        tb.set_p1_input_val(test_vals[i])
+        tb.p1_logic_check()
+
+
+async def p2_logic_check(dut):
+    tb = TB(dut)
+
+    test_vals = [
+        [0, 0, 0, 0],
+        [0, 1, 0, 0],
+        [0, 0, 0, 1],
+        [1, 1, 1, 1],
+    ]
+
+    tb.log.info("Checking output value...")
+
+    for i in range(len(test_vals)):
+        tb.set_p2_input_val(test_vals[i])
+        tb.p2_logic_check()
+
+
+if cocotb.SIM_NAME:
+    test1 = TestFactory(p1_logic_check)
+    test1.generate_tests()
+    test2 = TestFactory(p2_logic_check)
+    test2.generate_tests()
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "rtl"))
+
+parameter_list = [{}]
+
+
+@pytest.mark.parametrize("parameters", parameter_list)
+def test_constant_zero(request, parameters):
+    dut = "c7458"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+    ]
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+        compile_args=["--timing", "-O3"],
+        waves=True,
+    )

problems/verilog-language/basics/and-gate/tb/and_gate.py

@@ -0,0 +1,43 @@
+import logging
+from cocotb.clock import Timer
+
+
+class DataError(Exception):
+    pass
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        # Start logging
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Simulation Signals
+        self.get_signals()
+
+        # Zero out signals
+        self.zero_signals()
+
+    def get_signals(self):
+        self.a = self.dut.a
+        self.b = self.dut.b
+
+        self.out = self.dut.out
+
+    def zero_signals(self):
+        self.a.value = 0
+        self.b.value = 0
+
+    async def set_input_val(self, val):
+        self.a.value = val[0]
+        self.b.value = val[1]
+        await Timer(1, units="ns")
+
+    async def logic_check(self):
+        await Timer(1, units="ns")
+        if (bool(self.a.value) and bool(self.b.value)) != bool(self.out.value):
+            raise DataError(
+                f"a && b should be output, but ({self.a.value} && {self.b.value}) != {self.out.value}."
+            )

problems/verilog-language/basics/and-gate/tb/test_and_gate.py

@@ -0,0 +1,66 @@
+import os
+import pytest
+
+import cocotb
+from cocotb.regression import TestFactory
+from cocotb_test.simulator import run
+
+from and_gate import TB
+
+
+async def output_logic_check(dut):
+    tb = TB(dut)
+
+    test_vals = [
+        [0, 0],
+        [1, 0],
+        [0, 1],
+        [1, 1],
+    ]
+
+    tb.log.info("Checking output value...")
+
+    for i in range(len(test_vals)):
+        tb.set_input_val(test_vals[i])
+        tb.logic_check()
+
+
+if cocotb.SIM_NAME:
+    test1 = TestFactory(output_logic_check)
+    test1.generate_tests()
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "rtl"))
+
+parameter_list = [{}]
+
+
+@pytest.mark.parametrize("parameters", parameter_list)
+def test_constant_zero(request, parameters):
+    dut = "and_gate"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+    ]
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+        compile_args=["--timing", "-O3"],
+        waves=True,
+    )

problems/verilog-language/basics/declaring-wires/tb/declaring_wires.py

@@ -0,0 +1,57 @@
+import logging
+from cocotb.clock import Timer
+
+
+class DataError(Exception):
+    pass
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        # Start logging
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Simulation Signals
+        self.get_signals()
+
+        # Zero out signals
+        self.zero_signals()
+
+    def get_signals(self):
+        self.a = self.dut.a
+        self.b = self.dut.b
+        self.c = self.dut.c
+        self.d = self.dut.d
+
+        self.out = self.dut.out
+        self.out_n = self.dut.out_n
+
+    def zero_signals(self):
+        self.a.value = 0
+        self.b.value = 0
+        self.c.value = 0
+        self.d.value = 0
+
+    async def set_input_val(self, val):
+        self.a.value = val[0]
+        self.b.value = val[1]
+        self.c.value = val[2]
+        self.d.value = val[3]
+        await Timer(1, units="ns")
+
+    async def logic_check(self):
+        await Timer(1, units="ns")
+        if (
+            (bool(self.a.value) and bool(self.b.value))
+            or (bool(self.c.value) and bool(self.d.value))
+        ) != bool(self.out):
+            raise DataError(
+                f"out should be (a && b) || (c && d), but ({self.a.value} && {self.b.value}) || ({self.c.value} && {self.d.value})"
+            )
+        if int(self.out.value) == int(self.out_n.value):
+            raise DataError(
+                f"out_n should be inverse of out, but {self.out.value} == {self.out_n.value}."
+            )