Skip to content

Commit 732bc75

Browse files
refactor: use &'static [PReg] instead of Vec<PReg>
1 parent 925df1b commit 732bc75

File tree

5 files changed

+25
-17
lines changed

5 files changed

+25
-17
lines changed

src/checker.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -722,7 +722,7 @@ impl<'a, F: Function> Checker<'a, F> {
722722
bb_in.insert(f.entry_block(), CheckerState::default());
723723

724724
let mut stack_pregs = PRegSet::empty();
725-
for &preg in &machine_env.fixed_stack_slots {
725+
for &preg in machine_env.fixed_stack_slots {
726726
stack_pregs.add(preg);
727727
}
728728

src/fastalloc/mod.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -245,9 +245,9 @@ impl<'a, F: Function> Env<'a, F> {
245245
fn new(func: &'a F, env: &'a MachineEnv) -> Self {
246246
use alloc::vec;
247247
let mut regs = [
248-
env.preferred_regs_by_class[RegClass::Int as usize].clone(),
249-
env.preferred_regs_by_class[RegClass::Float as usize].clone(),
250-
env.preferred_regs_by_class[RegClass::Vector as usize].clone(),
248+
Vec::from(env.preferred_regs_by_class[RegClass::Int as usize]),
249+
Vec::from(env.preferred_regs_by_class[RegClass::Float as usize]),
250+
Vec::from(env.preferred_regs_by_class[RegClass::Vector as usize]),
251251
];
252252
regs[0].extend(
253253
env.non_preferred_regs_by_class[RegClass::Int as usize]

src/fastalloc/tests.rs

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -143,15 +143,17 @@ impl RealFunction {
143143
fn mach_env(no_of_regs: usize) -> MachineEnv {
144144
MachineEnv {
145145
preferred_regs_by_class: [
146-
(0..no_of_regs)
147-
.map(|no| PReg::new(no, RegClass::Int))
148-
.collect(),
149-
vec![],
150-
vec![],
146+
Vec::leak(
147+
(0..no_of_regs)
148+
.map(|no| PReg::new(no, RegClass::Int))
149+
.collect(),
150+
),
151+
&[],
152+
&[],
151153
],
152-
non_preferred_regs_by_class: [vec![], vec![], vec![]],
154+
non_preferred_regs_by_class: [&[], &[], &[]],
153155
scratch_by_class: [None, None, None],
154-
fixed_stack_slots: vec![],
156+
fixed_stack_slots: &[],
155157
}
156158
}
157159

src/ion/liveranges.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ impl<'a, F: Function> Env<'a, F> {
104104
is_stack: false,
105105
},
106106
);
107-
for &preg in &self.env.fixed_stack_slots {
107+
for &preg in self.env.fixed_stack_slots {
108108
self.pregs[preg.index()].is_stack = true;
109109
}
110110
for class in 0..self.preferred_victim_by_class.len() {

src/lib.rs

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -338,13 +338,13 @@ impl From<&MachineEnv> for PRegSet {
338338
fn from(env: &MachineEnv) -> Self {
339339
let mut res = Self::default();
340340

341-
for class in env.preferred_regs_by_class.iter() {
341+
for class in env.preferred_regs_by_class {
342342
for preg in class {
343343
res.add(*preg)
344344
}
345345
}
346346

347-
for class in env.non_preferred_regs_by_class.iter() {
347+
for class in env.non_preferred_regs_by_class {
348348
for preg in class {
349349
res.add(*preg)
350350
}
@@ -1434,6 +1434,12 @@ impl<'a> Iterator for OutputIter<'a> {
14341434
/// are available to allocate and what register may be used as a
14351435
/// scratch register for each class, and some other miscellaneous info
14361436
/// as well.
1437+
///
1438+
/// Note that `MachineEnv` is designed to be a global configuration struct that programs
1439+
/// will have very few of and generally want to keep around for their entire lifetime.
1440+
/// In order to make static initialization easier the registers lists are static slices instead
1441+
/// of `Vec`s. If your use case depends on dynamically creating the registers lists, consider
1442+
/// `[Vec::leak`].
14371443
#[derive(Clone, Debug)]
14381444
#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
14391445
pub struct MachineEnv {
@@ -1442,7 +1448,7 @@ pub struct MachineEnv {
14421448
///
14431449
/// If an explicit scratch register is provided in `scratch_by_class` then
14441450
/// it must not appear in this list.
1445-
pub preferred_regs_by_class: [Vec<PReg>; 3],
1451+
pub preferred_regs_by_class: [&'static [PReg]; 3],
14461452

14471453
/// Non-preferred physical registers for each class. These are the
14481454
/// registers that will be allocated if a preferred register is
@@ -1451,7 +1457,7 @@ pub struct MachineEnv {
14511457
///
14521458
/// If an explicit scratch register is provided in `scratch_by_class` then
14531459
/// it must not appear in this list.
1454-
pub non_preferred_regs_by_class: [Vec<PReg>; 3],
1460+
pub non_preferred_regs_by_class: [&'static [PReg]; 3],
14551461

14561462
/// Optional dedicated scratch register per class. This is needed to perform
14571463
/// moves between registers when cyclic move patterns occur. The
@@ -1476,7 +1482,7 @@ pub struct MachineEnv {
14761482
///
14771483
/// `PReg`s in this list cannot be used as an allocatable or scratch
14781484
/// register.
1479-
pub fixed_stack_slots: Vec<PReg>,
1485+
pub fixed_stack_slots: &'static [PReg],
14801486
}
14811487

14821488
/// The output of the register allocator.

0 commit comments

Comments
 (0)