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Add support for RISCV32 ILP32F (#3708)
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7 files changed

+71
-17
lines changed

7 files changed

+71
-17
lines changed

‎.github/workflows/spec_test_on_nuttx.yml‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,11 @@ jobs:
7474
target: "riscv32",
7575
fpu_type: "none"
7676
},
77+
{
78+
config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh",
79+
target: "riscv32_ilp32f",
80+
fpu_type: "fp"
81+
},
7782
# {
7883
# config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh",
7984
# target: "riscv32_ilp32d",
@@ -120,6 +125,10 @@ jobs:
120125
- target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64" }
121126
wamr_test_option: { mode: "-t aot -X" }
122127

128+
# XIP is not fully supported yet on RISCV32 ILP32F, some relocations can not be resolved
129+
- target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh", fpu_type: "fp" }
130+
wamr_test_option: { mode: "-t aot -X" }
131+
123132
# Our xtensa environment doesn't have enough memory
124133
- target_config: { target: "xtensa" }
125134
wamr_feature_option: { mode: "-G" }

‎build-scripts/config_common.cmake‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,8 @@ elseif (WAMR_BUILD_TARGET STREQUAL "RISCV64_LP64")
3939
add_definitions(-DBUILD_TARGET_RISCV64_LP64)
4040
elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32" OR WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32D")
4141
add_definitions(-DBUILD_TARGET_RISCV32_ILP32D)
42+
elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32F")
43+
add_definitions(-DBUILD_TARGET_RISCV32_ILP32F)
4244
elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32")
4345
add_definitions(-DBUILD_TARGET_RISCV32_ILP32)
4446
elseif (WAMR_BUILD_TARGET STREQUAL "ARC")

‎core/config.h‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
&& !defined(BUILD_TARGET_RISCV64_LP64D) \
2121
&& !defined(BUILD_TARGET_RISCV64_LP64) \
2222
&& !defined(BUILD_TARGET_RISCV32_ILP32D) \
23+
&& !defined(BUILD_TARGET_RISCV32_ILP32F) \
2324
&& !defined(BUILD_TARGET_RISCV32_ILP32) \
2425
&& !defined(BUILD_TARGET_ARC)
2526
/* clang-format on */
@@ -43,7 +44,11 @@
4344
#define BUILD_TARGET_XTENSA
4445
#elif defined(__riscv) && (__riscv_xlen == 64)
4546
#define BUILD_TARGET_RISCV64_LP64D
46-
#elif defined(__riscv) && (__riscv_xlen == 32)
47+
#elif defined(__riscv) && (__riscv_xlen == 32) && !defined(__riscv_flen)
48+
#define BUILD_TARGET_RISCV32_ILP32
49+
#elif defined(__riscv) && (__riscv_xlen == 32) && (__riscv_flen == 32)
50+
#define BUILD_TARGET_RISCV32_ILP32F
51+
#elif defined(__riscv) && (__riscv_xlen == 32) && (__riscv_flen == 64)
4752
#define BUILD_TARGET_RISCV32_ILP32D
4853
#elif defined(__arc__)
4954
#define BUILD_TARGET_ARC

‎core/iwasm/common/wasm_runtime_common.c‎

Lines changed: 48 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4718,9 +4718,13 @@ wasm_runtime_invoke_native_raw(WASMExecEnv *exec_env, void *func_ptr,
47184718
* Implementation of wasm_runtime_invoke_native()
47194719
*/
47204720

4721-
/* The invoke native implementation on ARM platform with VFP co-processor */
4721+
/**
4722+
* The invoke native implementation on ARM platform with VFP co-processor,
4723+
* RISCV32 platform with/without FPU/DPFPU and ARC platform.
4724+
*/
47224725
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) \
47234726
|| defined(BUILD_TARGET_RISCV32_ILP32D) \
4727+
|| defined(BUILD_TARGET_RISCV32_ILP32F) \
47244728
|| defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC)
47254729
typedef void (*GenericFunctionPointer)();
47264730
void
@@ -4821,7 +4825,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
48214825
#endif
48224826
n_ints += 2;
48234827
}
4824-
#if defined(BUILD_TARGET_RISCV32_ILP32) \
4828+
#if defined(BUILD_TARGET_RISCV32_ILP32) \
4829+
|| defined(BUILD_TARGET_RISCV32_ILP32F) \
48254830
|| defined(BUILD_TARGET_RISCV32_ILP32D) || defined(BUILD_TARGET_ARC)
48264831
/* part in register, part in stack */
48274832
else if (n_ints == MAX_REG_INTS - 1) {
@@ -4843,19 +4848,32 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
48434848
case VALUE_TYPE_F32:
48444849
if (n_fps < MAX_REG_FLOATS)
48454850
n_fps++;
4851+
#if defined(BUILD_TARGET_RISCV32_ILP32F)
4852+
else if (n_ints < MAX_REG_INTS) {
4853+
n_ints++;
4854+
}
4855+
#endif
48464856
else
48474857
n_stacks++;
48484858
break;
48494859
case VALUE_TYPE_F64:
4860+
#if defined(BUILD_TARGET_RISCV32_ILP32) \
4861+
|| defined(BUILD_TARGET_RISCV32_ILP32F) || defined(BUILD_TARGET_ARC)
4862+
if (n_ints < MAX_REG_INTS - 1) {
4863+
n_ints += 2;
4864+
}
4865+
else if (n_ints == MAX_REG_INTS - 1) {
4866+
n_ints++;
4867+
n_stacks++;
4868+
}
4869+
#endif
4870+
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP)
48504871
if (n_fps < MAX_REG_FLOATS - 1) {
4851-
#if !defined(BUILD_TARGET_RISCV32_ILP32) && !defined(BUILD_TARGET_ARC)
48524872
/* 64-bit data must be 8 bytes aligned in arm */
48534873
if (n_fps & 1)
48544874
n_fps++;
4855-
#endif
48564875
n_fps += 2;
48574876
}
4858-
#if defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC)
48594877
else if (n_fps == MAX_REG_FLOATS - 1) {
48604878
n_fps++;
48614879
n_stacks++;
@@ -4887,7 +4905,7 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
48874905
/* use int regs firstly if available */
48884906
if (n_ints & 1)
48894907
n_ints++;
4890-
ints += 2;
4908+
n_ints += 2;
48914909
}
48924910
else {
48934911
/* 64-bit data in stack must be 8 bytes aligned in riscv32
@@ -4911,7 +4929,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
49114929
n_stacks++;
49124930
}
49134931

4914-
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP)
4932+
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) \
4933+
|| defined(BUILD_TARGET_RISCV32_ILP32F)
49154934
argc1 = MAX_REG_INTS + MAX_REG_FLOATS + n_stacks;
49164935
#elif defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC)
49174936
argc1 = MAX_REG_INTS + n_stacks;
@@ -4928,7 +4947,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
49284947
}
49294948

49304949
ints = argv1;
4931-
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP)
4950+
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) \
4951+
|| defined(BUILD_TARGET_RISCV32_ILP32F)
49324952
fps = ints + MAX_REG_INTS;
49334953
stacks = fps + MAX_REG_FLOATS;
49344954
#elif defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC)
@@ -5018,7 +5038,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
50185038
ints[n_ints++] = *argv_src++;
50195039
ints[n_ints++] = *argv_src++;
50205040
}
5021-
#if defined(BUILD_TARGET_RISCV32_ILP32) \
5041+
#if defined(BUILD_TARGET_RISCV32_ILP32) \
5042+
|| defined(BUILD_TARGET_RISCV32_ILP32F) \
50225043
|| defined(BUILD_TARGET_RISCV32_ILP32D) || defined(BUILD_TARGET_ARC)
50235044
else if (n_ints == MAX_REG_INTS - 1) {
50245045
ints[n_ints++] = *argv_src++;
@@ -5042,22 +5063,36 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
50425063
{
50435064
if (n_fps < MAX_REG_FLOATS)
50445065
*(float32 *)&fps[n_fps++] = *(float32 *)argv_src++;
5066+
#if defined(BUILD_TARGET_RISCV32_ILP32F)
5067+
else if (n_ints < MAX_REG_INTS) {
5068+
ints[n_ints++] = *argv_src++;
5069+
}
5070+
#endif
50455071
else
50465072
*(float32 *)&stacks[n_stacks++] = *(float32 *)argv_src++;
50475073
break;
50485074
}
50495075
case VALUE_TYPE_F64:
50505076
{
5077+
#if defined(BUILD_TARGET_RISCV32_ILP32) \
5078+
|| defined(BUILD_TARGET_RISCV32_ILP32F) || defined(BUILD_TARGET_ARC)
5079+
if (n_ints < MAX_REG_INTS - 1) {
5080+
ints[n_ints++] = *argv_src++;
5081+
ints[n_ints++] = *argv_src++;
5082+
}
5083+
else if (n_ints == MAX_REG_INTS - 1) {
5084+
ints[n_ints++] = *argv_src++;
5085+
stacks[n_stacks++] = *argv_src++;
5086+
}
5087+
#endif
5088+
#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP)
50515089
if (n_fps < MAX_REG_FLOATS - 1) {
5052-
#if !defined(BUILD_TARGET_RISCV32_ILP32) && !defined(BUILD_TARGET_ARC)
50535090
/* 64-bit data must be 8 bytes aligned in arm */
50545091
if (n_fps & 1)
50555092
n_fps++;
5056-
#endif
50575093
fps[n_fps++] = *argv_src++;
50585094
fps[n_fps++] = *argv_src++;
50595095
}
5060-
#if defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC)
50615096
else if (n_fps == MAX_REG_FLOATS - 1) {
50625097
fps[n_fps++] = *argv_src++;
50635098
stacks[n_stacks++] = *argv_src++;
@@ -5249,6 +5284,7 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr,
52495284
#endif /* end of defined(BUILD_TARGET_ARM_VFP) \
52505285
|| defined(BUILD_TARGET_THUMB_VFP) \
52515286
|| defined(BUILD_TARGET_RISCV32_ILP32D) \
5287+
|| defined(BUILD_TARGET_RISCV32_ILP32F) \
52525288
|| defined(BUILD_TARGET_RISCV32_ILP32) \
52535289
|| defined(BUILD_TARGET_ARC) */
52545290

‎doc/build_wamr.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ The script `runtime_lib.cmake` defines a number of variables for configuring the
2828
- For ARM and THUMB, the format is \<arch>\[\<sub-arch>]\[_VFP], where \<sub-arch> is the ARM sub-architecture and the "_VFP" suffix means using VFP coprocessor registers s0-s15 (d0-d7) for passing arguments or returning results in standard procedure-call. Both \<sub-arch> and "_VFP" are optional, e.g. ARMV7, ARMV7_VFP, THUMBV7, THUMBV7_VFP and so on.
2929
- For AARCH64, the format is\<arch>[\<sub-arch>], VFP is enabled by default. \<sub-arch> is optional, e.g. AARCH64, AARCH64V8, AARCH64V8.1 and so on.
3030
- For RISCV64, the format is \<arch\>[_abi], where "_abi" is optional, currently the supported formats are RISCV64, RISCV64_LP64D and RISCV64_LP64: RISCV64 and RISCV64_LP64D are identical, using [LP64D](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (LP64 with hardware floating-point calling convention for FLEN=64). And RISCV64_LP64 uses [LP64](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used).
31-
- For RISCV32, the format is \<arch\>[_abi], where "_abi" is optional, currently the supported formats are RISCV32, RISCV32_ILP32D and RISCV32_ILP32: RISCV32 and RISCV32_ILP32D are identical, using [ILP32D](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (ILP32 with hardware floating-point calling convention for FLEN=64). And RISCV32_ILP32 uses [ILP32](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used).
31+
- For RISCV32, the format is \<arch\>[_abi], where "_abi" is optional, currently the supported formats are RISCV32, RISCV32_ILP32D, RISCV32_ILP32F and RISCV32_ILP32: RISCV32 and RISCV32_ILP32D are identical, using [ILP32D](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (ILP32 with hardware floating-point calling convention for FLEN=64). RISCV32_ILP32F uses [ILP32F](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (ILP32 with hardware floating-point calling convention for FLEN=32). And RISCV32_ILP32 uses [ILP32](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used).
3232

3333
```bash
3434
cmake -DWAMR_BUILD_PLATFORM=linux -DWAMR_BUILD_TARGET=ARM

‎product-mini/platforms/nuttx/wamr.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -101,10 +101,10 @@ else ifeq (${WAMR_BUILD_TARGET}, RISCV32)
101101

102102
ifeq (${CONFIG_ARCH_DPFPU},y)
103103
CFLAGS += -DBUILD_TARGET_RISCV32_ILP32D
104-
else ifneq (${CONFIG_ARCH_FPU},y)
105-
CFLAGS += -DBUILD_TARGET_RISCV32_ILP32
104+
else ifeq (${CONFIG_ARCH_FPU},y)
105+
CFLAGS += -DBUILD_TARGET_RISCV32_ILP32F
106106
else
107-
$(error riscv32 ilp32f is unsupported)
107+
CFLAGS += -DBUILD_TARGET_RISCV32_ILP32
108108
endif
109109

110110
INVOKE_NATIVE += invokeNative_riscv.S

‎wamr-compiler/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,8 @@ elseif (WAMR_BUILD_TARGET STREQUAL "RISCV64_LP64")
121121
add_definitions(-DBUILD_TARGET_RISCV64_LP64)
122122
elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32" OR WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32D")
123123
add_definitions(-DBUILD_TARGET_RISCV32_ILP32D)
124+
elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32F")
125+
add_definitions(-DBUILD_TARGET_RISCV32_ILP32F)
124126
elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32")
125127
add_definitions(-DBUILD_TARGET_RISCV32_ILP32)
126128
else ()

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