Fix issues of fnn.cmp (#1204)

lum1n0us · web-flow · commit b3a27e725713 · 2022-06-03T10:02:51.000+08:00
- use native functions to do f.eq and f.ne
- only use ZF=0 and CF=0 to do f.lt and f.gt
- only use CF=0 to do f.le and f.ge

could use comiss and setCC to replace comiss and jmpCC

be able to pass f32_cmp and f64_cmp

```
cmp_eq:
  xor     eax, eax
  ucomisd xmm0, xmm1
  mov     edx, 0
  setnp   al
  cmovne  eax, edx
  ret

cmp_ne:
  xor     eax, eax
  ucomisd xmm0, xmm1
  mov edx, 1
  setp al
  cmovne eax, edx
  ret
```
diff --git a/core/iwasm/fast-jit/cg/x86-64/jit_codegen_x86_64.cpp b/core/iwasm/fast-jit/cg/x86-64/jit_codegen_x86_64.cpp
@@ -363,7 +363,7 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,
         case GTS:
         {
             if (fp_cmp) {
-                a.jnbe(imm);
+                a.ja(imm);
             }
             else {
                 a.jg(imm);
@@ -373,7 +373,7 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,
         case LES:
         {
             if (fp_cmp) {
-                a.jbe(imm);
+                a.jnb(imm);
             }
             else {
                 a.jng(imm);
@@ -394,7 +394,7 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,
         case LTS:
         {
             if (fp_cmp) {
-                a.jb(imm);
+                a.ja(imm);
             }
             else {
                 a.jl(imm);
@@ -5071,7 +5071,7 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,
         case GTS:
         {
             if (fp_cmp) {
-                a.jnbe(target);
+                a.ja(target);
             }
             else {
                 a.jg(target);
@@ -5081,7 +5081,7 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,
         case LES:
         {
             if (fp_cmp) {
-                a.jbe(target);
+                a.jnb(target);
             }
             else {
                 a.jng(target);
@@ -5094,15 +5094,14 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,
                 a.jnb(target);
             }
             else {
-
                 a.jnl(target);
             }
             break;
         }
         case LTS:
         {
             if (fp_cmp) {
-                a.jb(target);
+                a.ja(target);
             }
             else {
                 a.jl(target);
diff --git a/core/iwasm/fast-jit/fe/jit_emit_compare.c b/core/iwasm/fast-jit/fe/jit_emit_compare.c
@@ -5,6 +5,7 @@
 
 #include "jit_emit_compare.h"
 #include "../jit_frontend.h"
+#include "../jit_codegen.h"
 
 static bool
 jit_compile_op_compare_integer(JitCompContext *cc, IntCond cond, bool is64Bit)
@@ -116,53 +117,129 @@ jit_compile_op_i64_compare(JitCompContext *cc, IntCond cond)
     return jit_compile_op_compare_integer(cc, cond, true);
 }
 
+static int32
+float_cmp_eq(float f1, float f2)
+{
+    if (isnan(f1) || isnan(f2))
+        return 0;
+
+    return f1 == f2;
+}
+
+static int32
+float_cmp_ne(float f1, float f2)
+{
+    if (isnan(f1) || isnan(f2))
+        return 1;
+
+    return f1 != f2;
+}
+
+static int32
+double_cmp_eq(double d1, double d2)
+{
+    if (isnan(d1) || isnan(d2))
+        return 0;
+
+    return d1 == d2;
+}
+
+static int32
+double_cmp_ne(double d1, double d2)
+{
+    if (isnan(d1) || isnan(d2))
+        return 1;
+
+    return d1 != d2;
+}
+
 static bool
 jit_compile_op_compare_float_point(JitCompContext *cc, FloatCond cond,
                                    JitReg lhs, JitReg rhs)
 {
     JitReg res, const_zero, const_one;
 
-    GEN_INSN(CMP, cc->cmp_reg, lhs, rhs);
+    if (cond == FLOAT_EQ) {
+        JitInsn *insn = NULL;
+        JitRegKind kind = jit_reg_kind(lhs);
 
-    res = jit_cc_new_reg_I32(cc);
-    const_zero = NEW_CONST(I32, 0);
-    const_one = NEW_CONST(I32, 1);
-    switch (cond) {
-        case FLOAT_EQ:
-        {
-            GEN_INSN(SELECTEQ, res, cc->cmp_reg, const_one, const_zero);
-            break;
-        }
-        case FLOAT_NE:
-        {
-            GEN_INSN(SELECTNE, res, cc->cmp_reg, const_one, const_zero);
-            break;
+#if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64)
+        res = jit_codegen_get_hreg_by_name("eax");
+#else
+        res = jit_cc_new_reg_I32(cc);
+#endif
+
+        if (kind == JIT_REG_KIND_F32) {
+            insn = GEN_INSN(CALLNATIVE, res,
+                            NEW_CONST(PTR, (uintptr_t)float_cmp_eq), 2);
         }
-        case FLOAT_LT:
-        {
-            GEN_INSN(SELECTLTS, res, cc->cmp_reg, const_one, const_zero);
-            break;
+        else {
+            insn = GEN_INSN(CALLNATIVE, res,
+                            NEW_CONST(PTR, (uintptr_t)double_cmp_eq), 2);
         }
-        case FLOAT_GT:
-        {
-            GEN_INSN(SELECTGTS, res, cc->cmp_reg, const_one, const_zero);
-            break;
+        if (!insn) {
+            goto fail;
         }
-        case FLOAT_LE:
-        {
-            GEN_INSN(SELECTLES, res, cc->cmp_reg, const_one, const_zero);
-            break;
+        *(jit_insn_opndv(insn, 2)) = lhs;
+        *(jit_insn_opndv(insn, 3)) = rhs;
+    }
+    else if (cond == FLOAT_NE) {
+        JitInsn *insn = NULL;
+        JitRegKind kind = jit_reg_kind(lhs);
+#if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64)
+        res = jit_codegen_get_hreg_by_name("eax");
+#else
+        res = jit_cc_new_reg_I32(cc);
+#endif
+        if (kind == JIT_REG_KIND_F32) {
+            insn = GEN_INSN(CALLNATIVE, res,
+                            NEW_CONST(PTR, (uintptr_t)float_cmp_ne), 2);
         }
-        case FLOAT_GE:
-        {
-            GEN_INSN(SELECTGES, res, cc->cmp_reg, const_one, const_zero);
-            break;
+        else {
+            insn = GEN_INSN(CALLNATIVE, res,
+                            NEW_CONST(PTR, (uintptr_t)double_cmp_ne), 2);
         }
-        default:
-        {
-            bh_assert(!"unknown FloatCond");
+        if (!insn) {
             goto fail;
         }
+        *(jit_insn_opndv(insn, 2)) = lhs;
+        *(jit_insn_opndv(insn, 3)) = rhs;
+    }
+    else {
+        res = jit_cc_new_reg_I32(cc);
+        const_zero = NEW_CONST(I32, 0);
+        const_one = NEW_CONST(I32, 1);
+        switch (cond) {
+            case FLOAT_LT:
+            {
+                GEN_INSN(CMP, cc->cmp_reg, rhs, lhs);
+                GEN_INSN(SELECTLTS, res, cc->cmp_reg, const_one, const_zero);
+                break;
+            }
+            case FLOAT_GT:
+            {
+                GEN_INSN(CMP, cc->cmp_reg, lhs, rhs);
+                GEN_INSN(SELECTGTS, res, cc->cmp_reg, const_one, const_zero);
+                break;
+            }
+            case FLOAT_LE:
+            {
+                GEN_INSN(CMP, cc->cmp_reg, rhs, lhs);
+                GEN_INSN(SELECTLES, res, cc->cmp_reg, const_one, const_zero);
+                break;
+            }
+            case FLOAT_GE:
+            {
+                GEN_INSN(CMP, cc->cmp_reg, lhs, rhs);
+                GEN_INSN(SELECTGES, res, cc->cmp_reg, const_one, const_zero);
+                break;
+            }
+            default:
+            {
+                bh_assert(!"unknown FloatCond");
+                goto fail;
+            }
+        }
     }
     PUSH_I32(res);
 

Original file line number	Diff line number	Diff line change
`@@ -363,7 +363,7 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,`
`363`	`363`	`case GTS:`
`364`	`364`	`{`
`365`	`365`	`if (fp_cmp) {`
`366`		`- a.jnbe(imm);`
	`366`	`+ a.ja(imm);`
`367`	`367`	`}`
`368`	`368`	`else {`
`369`	`369`	`a.jg(imm);`
`@@ -373,7 +373,7 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,`
`373`	`373`	`case LES:`
`374`	`374`	`{`
`375`	`375`	`if (fp_cmp) {`
`376`		`- a.jbe(imm);`
	`376`	`+ a.jnb(imm);`
`377`	`377`	`}`
`378`	`378`	`else {`
`379`	`379`	`a.jng(imm);`
`@@ -394,7 +394,7 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,`
`394`	`394`	`case LTS:`
`395`	`395`	`{`
`396`	`396`	`if (fp_cmp) {`
`397`		`- a.jb(imm);`
	`397`	`+ a.ja(imm);`
`398`	`398`	`}`
`399`	`399`	`else {`
`400`	`400`	`a.jl(imm);`
`@@ -5071,7 +5071,7 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,`
`5071`	`5071`	`case GTS:`
`5072`	`5072`	`{`
`5073`	`5073`	`if (fp_cmp) {`
`5074`		`- a.jnbe(target);`
	`5074`	`+ a.ja(target);`
`5075`	`5075`	`}`
`5076`	`5076`	`else {`
`5077`	`5077`	`a.jg(target);`
`@@ -5081,7 +5081,7 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,`
`5081`	`5081`	`case LES:`
`5082`	`5082`	`{`
`5083`	`5083`	`if (fp_cmp) {`
`5084`		`- a.jbe(target);`
	`5084`	`+ a.jnb(target);`
`5085`	`5085`	`}`
`5086`	`5086`	`else {`
`5087`	`5087`	`a.jng(target);`
`@@ -5094,15 +5094,14 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,`
`5094`	`5094`	`a.jnb(target);`
`5095`	`5095`	`}`
`5096`	`5096`	`else {`
`5097`		`-`
`5098`	`5097`	`a.jnl(target);`
`5099`	`5098`	`}`
`5100`	`5099`	`break;`
`5101`	`5100`	`}`
`5102`	`5101`	`case LTS:`
`5103`	`5102`	`{`
`5104`	`5103`	`if (fp_cmp) {`
`5105`		`- a.jb(target);`
	`5104`	`+ a.ja(target);`
`5106`	`5105`	`}`
`5107`	`5106`	`else {`
`5108`	`5107`	`a.jl(target);`