Update support for the relaxed-simd proposal (#944)

This wasm proposal is almost phase 4 so now seemed like a reasonable
time to sync the implementation here in `wasm-tools` with the upstream
specification. The changes here are:

* The "sat" in the float-to-int intrinsics naming was removed since
  it's not present in the upstream instruction.
* Dot-product instructions now have "relaxed" in their name.
  Additionally the float-based dot-product instruction has been removed
  from the upstream proposal.
* Opcodes were audited to ensure they match the latest upstream
  proposal.
* The "fma" and "fnma" naming was updated to "madd" and "nmadd"
* Generators in `wasm-smith` were updated to match the name of the
  instruction.
* The validator was reorganized to put all the relaxed simd instructions
  next to each other.

The upstream spec test suite was also updated which brought in some
BLESS=1 snapshot updates as well along with a minor tweak to an error
message.

Author: alexcrichton

crates/wasm-encoder/src/core/code.rs

@@ -769,15 +769,17 @@ pub enum Instruction<'a> {
     F64x2ConvertLowI32x4U,
     F32x4DemoteF64x2Zero,
     F64x2PromoteLowF32x4,
+
+    // Relaxed simd proposal
     I8x16RelaxedSwizzle,
-    I32x4RelaxedTruncSatF32x4S,
-    I32x4RelaxedTruncSatF32x4U,
-    I32x4RelaxedTruncSatF64x2SZero,
-    I32x4RelaxedTruncSatF64x2UZero,
-    F32x4RelaxedFma,
-    F32x4RelaxedFnma,
-    F64x2RelaxedFma,
-    F64x2RelaxedFnma,
+    I32x4RelaxedTruncF32x4S,
+    I32x4RelaxedTruncF32x4U,
+    I32x4RelaxedTruncF64x2SZero,
+    I32x4RelaxedTruncF64x2UZero,
+    F32x4RelaxedMadd,
+    F32x4RelaxedNmadd,
+    F64x2RelaxedMadd,
+    F64x2RelaxedNmadd,
     I8x16RelaxedLaneselect,
     I16x8RelaxedLaneselect,
     I32x4RelaxedLaneselect,
@@ -787,9 +789,8 @@ pub enum Instruction<'a> {
     F64x2RelaxedMin,
     F64x2RelaxedMax,
     I16x8RelaxedQ15mulrS,
-    I16x8DotI8x16I7x16S,
-    I32x4DotI8x16I7x16AddS,
-    F32x4RelaxedDotBf16x8AddF32x4,
+    I16x8RelaxedDotI8x16I7x16S,
+    I32x4RelaxedDotI8x16I7x16AddS,
 
     // Atomic instructions (the threads proposal)
     MemoryAtomicNotify(MemArg),
@@ -2370,35 +2371,35 @@ impl Encode for Instruction<'_> {
                 sink.push(0xFD);
                 0x100u32.encode(sink);
             }
-            Instruction::I32x4RelaxedTruncSatF32x4S => {
+            Instruction::I32x4RelaxedTruncF32x4S => {
                 sink.push(0xFD);
                 0x101u32.encode(sink);
             }
-            Instruction::I32x4RelaxedTruncSatF32x4U => {
+            Instruction::I32x4RelaxedTruncF32x4U => {
                 sink.push(0xFD);
                 0x102u32.encode(sink);
             }
-            Instruction::I32x4RelaxedTruncSatF64x2SZero => {
+            Instruction::I32x4RelaxedTruncF64x2SZero => {
                 sink.push(0xFD);
                 0x103u32.encode(sink);
             }
-            Instruction::I32x4RelaxedTruncSatF64x2UZero => {
+            Instruction::I32x4RelaxedTruncF64x2UZero => {
                 sink.push(0xFD);
                 0x104u32.encode(sink);
             }
-            Instruction::F32x4RelaxedFma => {
+            Instruction::F32x4RelaxedMadd => {
                 sink.push(0xFD);
                 0x105u32.encode(sink);
             }
-            Instruction::F32x4RelaxedFnma => {
+            Instruction::F32x4RelaxedNmadd => {
                 sink.push(0xFD);
                 0x106u32.encode(sink);
             }
-            Instruction::F64x2RelaxedFma => {
+            Instruction::F64x2RelaxedMadd => {
                 sink.push(0xFD);
                 0x107u32.encode(sink);
             }
-            Instruction::F64x2RelaxedFnma => {
+            Instruction::F64x2RelaxedNmadd => {
                 sink.push(0xFD);
                 0x108u32.encode(sink);
             }
@@ -2438,18 +2439,14 @@ impl Encode for Instruction<'_> {
                 sink.push(0xFD);
                 0x111u32.encode(sink);
             }
-            Instruction::I16x8DotI8x16I7x16S => {
+            Instruction::I16x8RelaxedDotI8x16I7x16S => {
                 sink.push(0xFD);
                 0x112u32.encode(sink);
             }
-            Instruction::I32x4DotI8x16I7x16AddS => {
+            Instruction::I32x4RelaxedDotI8x16I7x16AddS => {
                 sink.push(0xFD);
                 0x113u32.encode(sink);
             }
-            Instruction::F32x4RelaxedDotBf16x8AddF32x4 => {
-                sink.push(0xFD);
-                0x114u32.encode(sink);
-            }
 
             // Atmoic instructions from the thread proposal
             Instruction::MemoryAtomicNotify(memarg) => {

crates/wasm-smith/src/core/code_builder.rs

@@ -350,10 +350,10 @@ instructions! {
     (Some(simd_v128_v128_on_stack), i8x16_swizzle, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), i8x16_relaxed_swizzle, Vector),
     (Some(simd_v128_v128_v128_on_stack), v128_bitselect, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), i8x16_laneselect, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), i16x8_laneselect, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), i32x4_laneselect, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), i64x2_laneselect, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), i8x16_relaxed_laneselect, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), i16x8_relaxed_laneselect, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), i32x4_relaxed_laneselect, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), i64x2_relaxed_laneselect, Vector),
     (Some(simd_v128_v128_on_stack), i8x16_eq, Vector),
     (Some(simd_v128_v128_on_stack), i8x16_ne, Vector),
     (Some(simd_v128_v128_on_stack), i8x16_lt_s, Vector),
@@ -544,22 +544,21 @@ instructions! {
     (Some(simd_v128_on_stack), f64x2_convert_low_i32x4u, Vector),
     (Some(simd_v128_on_stack), f32x4_demote_f64x2_zero, Vector),
     (Some(simd_v128_on_stack), f64x2_promote_low_f32x4, Vector),
-    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_sat_f32x4s, Vector),
-    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_sat_f32x4u, Vector),
-    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_sat_f64x2s_zero, Vector),
-    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_sat_f64x2u_zero, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_fma, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_fnma, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_fma, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_fnma, Vector),
+    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_f32x4s, Vector),
+    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_f32x4u, Vector),
+    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_f64x2s_zero, Vector),
+    (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_f64x2u_zero, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_relaxed_madd, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_relaxed_nmadd, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_relaxed_madd, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_relaxed_nmadd, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f32x4_relaxed_min, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f32x4_relaxed_max, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f64x2_relaxed_min, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f64x2_relaxed_max, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), i16x8_relaxed_q15mulr_s, Vector),
-    (Some(simd_v128_v128_on_stack_relaxed), i16x8_dot_i8x16_i7x16_s, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), i32x4_dot_i8x16_i7x16_add_s, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_relaxed_dot_bf16x8_add_f32x4, Vector),
+    (Some(simd_v128_v128_on_stack_relaxed), i16x8_relaxed_dot_i8x16_i7x16_s, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), i32x4_relaxed_dot_i8x16_i7x16_add_s, Vector),
 }
 
 pub(crate) struct CodeBuilderAllocations {
@@ -5332,32 +5331,25 @@ simd_unop!(F32x4DemoteF64x2Zero, f32x4_demote_f64x2_zero);
 simd_unop!(F64x2PromoteLowF32x4, f64x2_promote_low_f32x4);
 simd_ternop!(V128Bitselect, v128_bitselect);
 simd_binop!(I8x16RelaxedSwizzle, i8x16_relaxed_swizzle);
-simd_unop!(I32x4RelaxedTruncSatF32x4S, i32x4_relaxed_trunc_sat_f32x4s);
-simd_unop!(I32x4RelaxedTruncSatF32x4U, i32x4_relaxed_trunc_sat_f32x4u);
-simd_unop!(
-    I32x4RelaxedTruncSatF64x2SZero,
-    i32x4_relaxed_trunc_sat_f64x2s_zero
-);
-simd_unop!(
-    I32x4RelaxedTruncSatF64x2UZero,
-    i32x4_relaxed_trunc_sat_f64x2u_zero
-);
-simd_ternop!(F32x4RelaxedFma, f32x4_fma);
-simd_ternop!(F32x4RelaxedFnma, f32x4_fnma);
-simd_ternop!(F64x2RelaxedFma, f64x2_fma);
-simd_ternop!(F64x2RelaxedFnma, f64x2_fnma);
-simd_ternop!(I8x16RelaxedLaneselect, i8x16_laneselect);
-simd_ternop!(I16x8RelaxedLaneselect, i16x8_laneselect);
-simd_ternop!(I32x4RelaxedLaneselect, i32x4_laneselect);
-simd_ternop!(I64x2RelaxedLaneselect, i64x2_laneselect);
+simd_unop!(I32x4RelaxedTruncF32x4S, i32x4_relaxed_trunc_f32x4s);
+simd_unop!(I32x4RelaxedTruncF32x4U, i32x4_relaxed_trunc_f32x4u);
+simd_unop!(I32x4RelaxedTruncF64x2SZero, i32x4_relaxed_trunc_f64x2s_zero);
+simd_unop!(I32x4RelaxedTruncF64x2UZero, i32x4_relaxed_trunc_f64x2u_zero);
+simd_ternop!(F32x4RelaxedMadd, f32x4_relaxed_madd);
+simd_ternop!(F32x4RelaxedNmadd, f32x4_relaxed_nmadd);
+simd_ternop!(F64x2RelaxedMadd, f64x2_relaxed_madd);
+simd_ternop!(F64x2RelaxedNmadd, f64x2_relaxed_nmadd);
+simd_ternop!(I8x16RelaxedLaneselect, i8x16_relaxed_laneselect);
+simd_ternop!(I16x8RelaxedLaneselect, i16x8_relaxed_laneselect);
+simd_ternop!(I32x4RelaxedLaneselect, i32x4_relaxed_laneselect);
+simd_ternop!(I64x2RelaxedLaneselect, i64x2_relaxed_laneselect);
 simd_binop!(F32x4RelaxedMin, f32x4_relaxed_min);
 simd_binop!(F32x4RelaxedMax, f32x4_relaxed_max);
 simd_binop!(F64x2RelaxedMin, f64x2_relaxed_min);
 simd_binop!(F64x2RelaxedMax, f64x2_relaxed_max);
 simd_binop!(I16x8RelaxedQ15mulrS, i16x8_relaxed_q15mulr_s);
-simd_binop!(I16x8DotI8x16I7x16S, i16x8_dot_i8x16_i7x16_s);
-simd_ternop!(I32x4DotI8x16I7x16AddS, i32x4_dot_i8x16_i7x16_add_s);
+simd_binop!(I16x8RelaxedDotI8x16I7x16S, i16x8_relaxed_dot_i8x16_i7x16_s);
 simd_ternop!(
-    F32x4RelaxedDotBf16x8AddF32x4,
-    f32x4_relaxed_dot_bf16x8_add_f32x4
+    I32x4RelaxedDotI8x16I7x16AddS,
+    i32x4_relaxed_dot_i8x16_i7x16_add_s
 );

crates/wasmparser/src/binary_reader.rs

@@ -1352,14 +1352,14 @@ impl<'a> BinaryReader<'a> {
             0xfe => visitor.visit_f64x2_convert_low_i32x4_s(),
             0xff => visitor.visit_f64x2_convert_low_i32x4_u(),
             0x100 => visitor.visit_i8x16_relaxed_swizzle(),
-            0x101 => visitor.visit_i32x4_relaxed_trunc_sat_f32x4_s(),
-            0x102 => visitor.visit_i32x4_relaxed_trunc_sat_f32x4_u(),
-            0x103 => visitor.visit_i32x4_relaxed_trunc_sat_f64x2_s_zero(),
-            0x104 => visitor.visit_i32x4_relaxed_trunc_sat_f64x2_u_zero(),
-            0x105 => visitor.visit_f32x4_relaxed_fma(),
-            0x106 => visitor.visit_f32x4_relaxed_fnma(),
-            0x107 => visitor.visit_f64x2_relaxed_fma(),
-            0x108 => visitor.visit_f64x2_relaxed_fnma(),
+            0x101 => visitor.visit_i32x4_relaxed_trunc_f32x4_s(),
+            0x102 => visitor.visit_i32x4_relaxed_trunc_f32x4_u(),
+            0x103 => visitor.visit_i32x4_relaxed_trunc_f64x2_s_zero(),
+            0x104 => visitor.visit_i32x4_relaxed_trunc_f64x2_u_zero(),
+            0x105 => visitor.visit_f32x4_relaxed_madd(),
+            0x106 => visitor.visit_f32x4_relaxed_nmadd(),
+            0x107 => visitor.visit_f64x2_relaxed_madd(),
+            0x108 => visitor.visit_f64x2_relaxed_nmadd(),
             0x109 => visitor.visit_i8x16_relaxed_laneselect(),
             0x10a => visitor.visit_i16x8_relaxed_laneselect(),
             0x10b => visitor.visit_i32x4_relaxed_laneselect(),
@@ -1369,9 +1369,8 @@ impl<'a> BinaryReader<'a> {
             0x10f => visitor.visit_f64x2_relaxed_min(),
             0x110 => visitor.visit_f64x2_relaxed_max(),
             0x111 => visitor.visit_i16x8_relaxed_q15mulr_s(),
-            0x112 => visitor.visit_i16x8_dot_i8x16_i7x16_s(),
-            0x113 => visitor.visit_i32x4_dot_i8x16_i7x16_add_s(),
-            0x114 => visitor.visit_f32x4_relaxed_dot_bf16x8_add_f32x4(),
+            0x112 => visitor.visit_i16x8_relaxed_dot_i8x16_i7x16_s(),
+            0x113 => visitor.visit_i32x4_relaxed_dot_i8x16_i7x16_add_s(),
 
             _ => bail!(pos, "unknown 0xfd subopcode: 0x{code:x}"),
         })

crates/wasmparser/src/lib.rs

@@ -658,14 +658,14 @@ macro_rules! for_each_operator {
             // Relaxed SIMD operators
             // https://github.com/WebAssembly/relaxed-simd
             @relaxed_simd I8x16RelaxedSwizzle => visit_i8x16_relaxed_swizzle
-            @relaxed_simd I32x4RelaxedTruncSatF32x4S => visit_i32x4_relaxed_trunc_sat_f32x4_s
-            @relaxed_simd I32x4RelaxedTruncSatF32x4U => visit_i32x4_relaxed_trunc_sat_f32x4_u
-            @relaxed_simd I32x4RelaxedTruncSatF64x2SZero => visit_i32x4_relaxed_trunc_sat_f64x2_s_zero
-            @relaxed_simd I32x4RelaxedTruncSatF64x2UZero => visit_i32x4_relaxed_trunc_sat_f64x2_u_zero
-            @relaxed_simd F32x4RelaxedFma => visit_f32x4_relaxed_fma
-            @relaxed_simd F32x4RelaxedFnma => visit_f32x4_relaxed_fnma
-            @relaxed_simd F64x2RelaxedFma => visit_f64x2_relaxed_fma
-            @relaxed_simd F64x2RelaxedFnma => visit_f64x2_relaxed_fnma
+            @relaxed_simd I32x4RelaxedTruncF32x4S => visit_i32x4_relaxed_trunc_f32x4_s
+            @relaxed_simd I32x4RelaxedTruncF32x4U => visit_i32x4_relaxed_trunc_f32x4_u
+            @relaxed_simd I32x4RelaxedTruncF64x2SZero => visit_i32x4_relaxed_trunc_f64x2_s_zero
+            @relaxed_simd I32x4RelaxedTruncF64x2UZero => visit_i32x4_relaxed_trunc_f64x2_u_zero
+            @relaxed_simd F32x4RelaxedMadd => visit_f32x4_relaxed_madd
+            @relaxed_simd F32x4RelaxedNmadd => visit_f32x4_relaxed_nmadd
+            @relaxed_simd F64x2RelaxedMadd => visit_f64x2_relaxed_madd
+            @relaxed_simd F64x2RelaxedNmadd => visit_f64x2_relaxed_nmadd
             @relaxed_simd I8x16RelaxedLaneselect => visit_i8x16_relaxed_laneselect
             @relaxed_simd I16x8RelaxedLaneselect => visit_i16x8_relaxed_laneselect
             @relaxed_simd I32x4RelaxedLaneselect => visit_i32x4_relaxed_laneselect
@@ -675,9 +675,8 @@ macro_rules! for_each_operator {
             @relaxed_simd F64x2RelaxedMin => visit_f64x2_relaxed_min
             @relaxed_simd F64x2RelaxedMax => visit_f64x2_relaxed_max
             @relaxed_simd I16x8RelaxedQ15mulrS => visit_i16x8_relaxed_q15mulr_s
-            @relaxed_simd I16x8DotI8x16I7x16S => visit_i16x8_dot_i8x16_i7x16_s
-            @relaxed_simd I32x4DotI8x16I7x16AddS => visit_i32x4_dot_i8x16_i7x16_add_s
-            @relaxed_simd F32x4RelaxedDotBf16x8AddF32x4 => visit_f32x4_relaxed_dot_bf16x8_add_f32x4
+            @relaxed_simd I16x8RelaxedDotI8x16I7x16S => visit_i16x8_relaxed_dot_i8x16_i7x16_s
+            @relaxed_simd I32x4RelaxedDotI8x16I7x16AddS => visit_i32x4_relaxed_dot_i8x16_i7x16_add_s
 
             // Typed Function references
             @function_references CallRef { hty: $crate::HeapType } => visit_call_ref

crates/wasmparser/src/validator/core.rs

@@ -214,7 +214,7 @@ impl ModuleState {
                 {
                     return Err(BinaryReaderError::new(
                         format!(
-                            "invalid element type `{}` for table type `{}`",
+                            "type mismatch: invalid element type `{}` for table type `{}`",
                             ty_to_str(e.ty.into()),
                             ty_to_str(table.element_type.into()),
                         ),