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abrownabrown
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x64: remove old Inst::Mul* variants
1 parent ccaa726 commit 0771ae7

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4 files changed

+1
-312
lines changed

4 files changed

+1
-312
lines changed

‎cranelift/codegen/src/isa/x64/inst.isle‎

Lines changed: 0 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -62,15 +62,6 @@
6262
(dividend Gpr)
6363
(dst WritableGpr))
6464

65-
;; Unsigned multiplication producing the high bits of the result in one
66-
;; register and the low bits in another register.
67-
(Mul (size OperandSize)
68-
(signed bool)
69-
(src1 Gpr)
70-
(src2 GprMem)
71-
(dst_lo WritableGpr)
72-
(dst_hi WritableGpr))
73-
7465
;; Same as `Mul`, but for the BMI2 `mulx` instruction. This is different
7566
;; where the two `dst_*` registers can be arbitrary registers and it
7667
;; is always unsigned multiplication. Note that this instruction does
@@ -86,26 +77,6 @@
8677
(dst_lo WritableGpr)
8778
(dst_hi WritableGpr))
8879

89-
;; Same as `Mul` but the 16-bit multiplication result is stored in `AX`.
90-
(Mul8 (signed bool)
91-
(src1 Gpr)
92-
(src2 GprMem)
93-
(dst WritableGpr))
94-
95-
;; The two-operand form of `imul` which produces a truncated same-size
96-
;; result as the operands.
97-
(IMul (size OperandSize)
98-
(src1 Gpr)
99-
(src2 GprMem)
100-
(dst WritableGpr))
101-
102-
;; The three-operand form of `imul` where the third operand must be
103-
;; a constant.
104-
(IMulImm (size OperandSize)
105-
(src1 GprMem)
106-
(src2 i32)
107-
(dst WritableGpr))
108-
10980
;; A synthetic instruction sequence used as part of the lowering of the
11081
;; `srem` instruction which returns 0 if the divisor is -1 and
11182
;; otherwise executes an `idiv` instruction.

‎cranelift/codegen/src/isa/x64/inst/emit.rs‎

Lines changed: 0 additions & 136 deletions
Original file line numberDiff line numberDiff line change
@@ -366,142 +366,6 @@ pub(crate) fn emit(
366366
}
367367
}
368368

369-
Inst::Mul {
370-
signed,
371-
size,
372-
src1,
373-
src2,
374-
dst_lo,
375-
dst_hi,
376-
} => {
377-
let src1 = src1.to_reg();
378-
let dst_lo = dst_lo.to_reg().to_reg();
379-
let dst_hi = dst_hi.to_reg().to_reg();
380-
debug_assert_eq!(src1, regs::rax());
381-
debug_assert_eq!(dst_lo, regs::rax());
382-
debug_assert_eq!(dst_hi, regs::rdx());
383-
let src2 = src2.clone().to_reg_mem().clone();
384-
385-
let rex_flags = RexFlags::from(*size);
386-
let prefix = match size {
387-
OperandSize::Size16 => LegacyPrefixes::_66,
388-
OperandSize::Size32 => LegacyPrefixes::None,
389-
OperandSize::Size64 => LegacyPrefixes::None,
390-
_ => unreachable!(),
391-
};
392-
393-
let subopcode = if *signed { 5 } else { 4 };
394-
match src2 {
395-
RegMem::Reg { reg } => {
396-
let src = int_reg_enc(reg);
397-
emit_std_enc_enc(sink, prefix, 0xF7, 1, subopcode, src, rex_flags)
398-
}
399-
RegMem::Mem { addr: src } => {
400-
let amode = src.finalize(state.frame_layout(), sink);
401-
emit_std_enc_mem(sink, prefix, 0xF7, 1, subopcode, &amode, rex_flags, 0);
402-
}
403-
}
404-
}
405-
Inst::Mul8 {
406-
signed,
407-
src1,
408-
src2,
409-
dst,
410-
} => {
411-
let src1 = src1.to_reg();
412-
let dst = dst.to_reg().to_reg();
413-
debug_assert_eq!(src1, regs::rax());
414-
debug_assert_eq!(dst, regs::rax());
415-
let src2 = src2.clone().to_reg_mem().clone();
416-
417-
let mut rex_flags = RexFlags::from(OperandSize::Size8);
418-
let prefix = LegacyPrefixes::None;
419-
let subopcode = if *signed { 5 } else { 4 };
420-
match src2 {
421-
RegMem::Reg { reg } => {
422-
// The intel manual states:
423-
//
424-
// > r/m8 can not be encoded to access the following byte
425-
// > registers if a REX prefix is used: AH, BH, CH, DH
426-
//
427-
// And apparently that also means that a REX prefix must be
428-
// used if it's not one of those registers.
429-
if !(reg == regs::rax()
430-
|| reg == regs::rbx()
431-
|| reg == regs::rcx()
432-
|| reg == regs::rdx())
433-
{
434-
rex_flags.always_emit();
435-
}
436-
let src = int_reg_enc(reg);
437-
emit_std_enc_enc(sink, prefix, 0xF6, 1, subopcode, src, rex_flags)
438-
}
439-
RegMem::Mem { addr } => {
440-
let amode = addr.finalize(state.frame_layout(), sink);
441-
emit_std_enc_mem(sink, prefix, 0xF6, 1, subopcode, &amode, rex_flags, 0);
442-
}
443-
}
444-
}
445-
Inst::IMul {
446-
size,
447-
src1,
448-
src2,
449-
dst,
450-
} => {
451-
let src1 = src1.to_reg();
452-
let dst = dst.to_reg().to_reg();
453-
debug_assert_eq!(src1, dst);
454-
let src2 = src2.clone().to_reg_mem().clone();
455-
456-
let rex = RexFlags::from(*size);
457-
let prefix = LegacyPrefixes::None;
458-
match src2 {
459-
RegMem::Reg { reg } => {
460-
emit_std_reg_reg(sink, prefix, 0x0FAF, 2, dst, reg, rex);
461-
}
462-
463-
RegMem::Mem { addr } => {
464-
let amode = addr.finalize(state.frame_layout(), sink);
465-
emit_std_reg_mem(sink, prefix, 0x0FAF, 2, dst, &amode, rex, 0);
466-
}
467-
}
468-
}
469-
470-
Inst::IMulImm {
471-
size,
472-
src1,
473-
src2,
474-
dst,
475-
} => {
476-
let dst = dst.to_reg().to_reg();
477-
let src1 = src1.clone().to_reg_mem().clone();
478-
479-
let rex = RexFlags::from(*size);
480-
let prefix = match size {
481-
// NB: the intel manual doesn't seem to mention this prefix as
482-
// being required
483-
OperandSize::Size16 => LegacyPrefixes::_66,
484-
_ => LegacyPrefixes::None,
485-
};
486-
let imm_size = if i8::try_from(*src2).is_ok() {
487-
1
488-
} else {
489-
if *size == OperandSize::Size16 { 2 } else { 4 }
490-
};
491-
let opcode = if imm_size == 1 { 0x6B } else { 0x69 };
492-
match src1 {
493-
RegMem::Reg { reg } => {
494-
emit_std_reg_reg(sink, prefix, opcode, 1, dst, reg, rex);
495-
}
496-
497-
RegMem::Mem { addr } => {
498-
let amode = addr.finalize(state.frame_layout(), sink);
499-
emit_std_reg_mem(sink, prefix, opcode, 1, dst, &amode, rex, imm_size);
500-
}
501-
}
502-
emit_simm(sink, imm_size, *src2 as u32);
503-
}
504-
505369
Inst::MulX {
506370
size,
507371
src1,

‎cranelift/codegen/src/isa/x64/inst/mod.rs‎

Lines changed: 0 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -113,10 +113,6 @@ impl Inst {
113113
| Inst::MovToPReg { .. }
114114
| Inst::MovsxRmR { .. }
115115
| Inst::MovzxRmR { .. }
116-
| Inst::Mul { .. }
117-
| Inst::Mul8 { .. }
118-
| Inst::IMul { .. }
119-
| Inst::IMulImm { .. }
120116
| Inst::Nop { .. }
121117
| Inst::Pop64 { .. }
122118
| Inst::Push64 { .. }
@@ -776,27 +772,6 @@ impl PrettyPrint for Inst {
776772
format!("{op} {dividend}, {divisor}, {dst} ; trap={trap}")
777773
}
778774

779-
Inst::Mul {
780-
size,
781-
signed,
782-
src1,
783-
src2,
784-
dst_lo,
785-
dst_hi,
786-
} => {
787-
let src1 = pretty_print_reg(src1.to_reg(), size.to_bytes());
788-
let dst_lo = pretty_print_reg(dst_lo.to_reg().to_reg(), size.to_bytes());
789-
let dst_hi = pretty_print_reg(dst_hi.to_reg().to_reg(), size.to_bytes());
790-
let src2 = src2.pretty_print(size.to_bytes());
791-
let suffix = suffix_bwlq(*size);
792-
let op = ljustify(if *signed {
793-
format!("imul{suffix}")
794-
} else {
795-
format!("mul{suffix}")
796-
});
797-
format!("{op} {src1}, {src2}, {dst_lo}, {dst_hi}")
798-
}
799-
800775
Inst::MulX {
801776
size,
802777
src1,
@@ -817,50 +792,6 @@ impl PrettyPrint for Inst {
817792
format!("{op} {src1}, {src2}, {dst_lo}, {dst_hi}")
818793
}
819794

820-
Inst::Mul8 {
821-
signed,
822-
src1,
823-
src2,
824-
dst,
825-
} => {
826-
let src1 = pretty_print_reg(src1.to_reg(), 1);
827-
let dst = pretty_print_reg(dst.to_reg().to_reg(), 1);
828-
let src2 = src2.pretty_print(1);
829-
let op = ljustify(if *signed {
830-
"imulb".to_string()
831-
} else {
832-
"mulb".to_string()
833-
});
834-
format!("{op} {src1}, {src2}, {dst}")
835-
}
836-
837-
Inst::IMul {
838-
size,
839-
src1,
840-
src2,
841-
dst,
842-
} => {
843-
let src1 = pretty_print_reg(src1.to_reg(), size.to_bytes());
844-
let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes());
845-
let src2 = src2.pretty_print(size.to_bytes());
846-
let suffix = suffix_bwlq(*size);
847-
let op = ljustify(format!("imul{suffix}"));
848-
format!("{op} {src1}, {src2}, {dst}")
849-
}
850-
851-
Inst::IMulImm {
852-
size,
853-
src1,
854-
src2,
855-
dst,
856-
} => {
857-
let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes());
858-
let src1 = src1.pretty_print(size.to_bytes());
859-
let suffix = suffix_bwlq(*size);
860-
let op = ljustify(format!("imul{suffix}"));
861-
format!("{op} {src1}, {src2:#x}, {dst}")
862-
}
863-
864795
Inst::CheckedSRemSeq {
865796
size,
866797
divisor,
@@ -2012,36 +1943,6 @@ fn x64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
20121943
collector.reg_fixed_use(dividend, regs::rax());
20131944
collector.reg_fixed_def(dst, regs::rax());
20141945
}
2015-
Inst::Mul {
2016-
src1,
2017-
src2,
2018-
dst_lo,
2019-
dst_hi,
2020-
..
2021-
} => {
2022-
collector.reg_fixed_use(src1, regs::rax());
2023-
collector.reg_fixed_def(dst_lo, regs::rax());
2024-
collector.reg_fixed_def(dst_hi, regs::rdx());
2025-
src2.get_operands(collector);
2026-
}
2027-
Inst::Mul8 {
2028-
src1, src2, dst, ..
2029-
} => {
2030-
collector.reg_fixed_use(src1, regs::rax());
2031-
collector.reg_fixed_def(dst, regs::rax());
2032-
src2.get_operands(collector);
2033-
}
2034-
Inst::IMul {
2035-
src1, src2, dst, ..
2036-
} => {
2037-
collector.reg_use(src1);
2038-
collector.reg_reuse_def(dst, 0);
2039-
src2.get_operands(collector);
2040-
}
2041-
Inst::IMulImm { src1, dst, .. } => {
2042-
collector.reg_def(dst);
2043-
src1.get_operands(collector);
2044-
}
20451946
Inst::MulX {
20461947
src1,
20471948
src2,

‎cranelift/codegen/src/isa/x64/pcc.rs‎

Lines changed: 1 addition & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -126,14 +126,7 @@ pub(crate) fn check(
126126
undefined_result(ctx, vcode, dst, 64, 64)?;
127127
Ok(())
128128
}
129-
Inst::Mul {
130-
size,
131-
dst_lo,
132-
dst_hi,
133-
ref src2,
134-
..
135-
}
136-
| Inst::MulX {
129+
Inst::MulX {
137130
size,
138131
dst_lo,
139132
dst_hi,
@@ -150,46 +143,6 @@ pub(crate) fn check(
150143
undefined_result(ctx, vcode, dst_hi, 64, size.to_bits().into())?;
151144
Ok(())
152145
}
153-
Inst::Mul8 { dst, ref src2, .. } => {
154-
match <&RegMem>::from(src2) {
155-
RegMem::Mem { addr } => {
156-
check_load(ctx, None, addr, vcode, I8, 64)?;
157-
}
158-
RegMem::Reg { .. } => {}
159-
}
160-
undefined_result(ctx, vcode, dst, 64, 16)?;
161-
Ok(())
162-
}
163-
Inst::IMul {
164-
size,
165-
dst,
166-
ref src2,
167-
..
168-
} => {
169-
match <&RegMem>::from(src2) {
170-
RegMem::Mem { addr } => {
171-
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
172-
}
173-
RegMem::Reg { .. } => {}
174-
}
175-
undefined_result(ctx, vcode, dst, 64, size.to_bits().into())?;
176-
Ok(())
177-
}
178-
Inst::IMulImm {
179-
size,
180-
dst,
181-
ref src1,
182-
..
183-
} => {
184-
match <&RegMem>::from(src1) {
185-
RegMem::Mem { addr } => {
186-
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
187-
}
188-
RegMem::Reg { .. } => {}
189-
}
190-
undefined_result(ctx, vcode, dst, 64, size.to_bits().into())?;
191-
Ok(())
192-
}
193146
Inst::CheckedSRemSeq {
194147
dst_quotient,
195148
dst_remainder,

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