riscv64: Implement near relocations (#11585)

* riscv64: Implement near relocations

This is the same as #11570 but for the riscv64 backend. The intention is
to support "near" relocations which don't require `Abs8` relocations for
upcoming use in Wasmtime. The same design as #11570 is used here.

* Review comments

Author: alexcrichton

cranelift/codegen/src/binemit/mod.rs

@@ -120,6 +120,12 @@ pub enum Reloc {
     /// <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses>
     RiscvGotHi20,
 
+    /// High 20 bits of a 32-bit PC-relative offset relocation
+    ///
+    /// This is the `R_RISCV_PCREL_HI20` relocation from the RISC-V ELF psABI document.
+    /// <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses>
+    RiscvPCRelHi20,
+
     /// s390x TLS GD64 - 64-bit offset of tls_index for GD symbol in GOT
     S390xTlsGd64,
     /// s390x TLS GDCall - marker to enable optimization of TLS calls
@@ -152,6 +158,7 @@ impl fmt::Display for Reloc {
             Self::RiscvCallPlt => write!(f, "RiscvCallPlt"),
             Self::RiscvTlsGdHi20 => write!(f, "RiscvTlsGdHi20"),
             Self::RiscvGotHi20 => write!(f, "RiscvGotHi20"),
+            Self::RiscvPCRelHi20 => write!(f, "RiscvPCRelHi20"),
             Self::RiscvPCRelLo12I => write!(f, "RiscvPCRelLo12I"),
             Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"),
             Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"),

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -139,7 +139,14 @@
       (kind IntegerCompare))
 
     ;; Load an inline symbol reference.
-    (LoadExtName
+    (LoadExtNameGot
+      (rd WritableReg)
+      (name BoxExternalName))
+    (LoadExtNameNear
+      (rd WritableReg)
+      (name BoxExternalName)
+      (offset i64))
+    (LoadExtNameFar
       (rd WritableReg)
       (name BoxExternalName)
       (offset i64))
@@ -2750,8 +2757,43 @@
 
 
 ;;;; load extern name
-(decl load_ext_name (ExternalName i64) Reg)
-(extern constructor load_ext_name load_ext_name)
+(decl load_ext_name (ExternalName i64 RelocDistance) Reg)
+(rule (load_ext_name name offset _dist)
+  (if-let true (is_pic))
+  (rv_add (load_ext_name_got name) (imm $I64 (i64_cast_unsigned offset))))
+(rule 1 (load_ext_name name 0 _dist)
+  (if-let true (is_pic))
+  (load_ext_name_got name))
+(rule (load_ext_name name offset (RelocDistance.Near))
+  (if-let false (is_pic))
+  (load_ext_name_near name offset))
+(rule (load_ext_name name offset (RelocDistance.Far))
+  (if-let false (is_pic))
+  (load_ext_name_far name offset))
+
+(decl pure is_pic () bool)
+(extern constructor is_pic is_pic)
+
+;; Helper for emitting `MInst.LoadExtNameGot` instructions.
+(decl load_ext_name_got (BoxExternalName) Reg)
+(rule (load_ext_name_got extname)
+      (let ((dst WritableReg (temp_writable_reg $I64))
+            (_ Unit (emit (MInst.LoadExtNameGot dst extname))))
+        dst))
+
+;; Helper for emitting `MInst.LoadExtNameNear` instructions.
+(decl load_ext_name_near (BoxExternalName i64) Reg)
+(rule (load_ext_name_near extname offset)
+      (let ((dst WritableReg (temp_writable_reg $I64))
+            (_ Unit (emit (MInst.LoadExtNameNear dst extname offset))))
+        dst))
+
+;; Helper for emitting `MInst.LoadExtNameFar` instructions.
+(decl load_ext_name_far (BoxExternalName i64) Reg)
+(rule (load_ext_name_far extname offset)
+      (let ((dst WritableReg (temp_writable_reg $I64))
+            (_ Unit (emit (MInst.LoadExtNameFar dst extname offset))))
+        dst))
 
 (decl elf_tls_get_addr (ExternalName) Reg)
 (rule (elf_tls_get_addr name)

cranelift/codegen/src/isa/riscv64/inst/emit.rs

@@ -8,6 +8,7 @@ use crate::isa::riscv64::lower::isle::generated_code::{
 use cranelift_control::ControlPlane;
 
 pub struct EmitInfo {
+    #[expect(dead_code, reason = "may want to be used in the future")]
     shared_flag: settings::Flags,
     isa_flags: super::super::riscv_settings::Flags,
 }
@@ -170,7 +171,9 @@ impl Inst {
             | Inst::ReturnCallInd { .. }
             | Inst::Jal { .. }
             | Inst::CondBr { .. }
-            | Inst::LoadExtName { .. }
+            | Inst::LoadExtNameGot { .. }
+            | Inst::LoadExtNameNear { .. }
+            | Inst::LoadExtNameFar { .. }
             | Inst::ElfTlsGetAddr { .. }
             | Inst::LoadAddr { .. }
             | Inst::Mov { .. }
@@ -1999,76 +2002,108 @@ impl Inst {
                 .emit(sink, emit_info, state);
             }
 
-            &Inst::LoadExtName {
+            &Inst::LoadExtNameGot { rd, ref name } => {
+                // Load a PC-relative address into a register.
+                // RISC-V does this slightly differently from other arches. We emit a relocation
+                // with a label, instead of the symbol itself.
+                //
+                // See: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses
+                //
+                // Emit the following code:
+                // label:
+                //   auipc rd, 0              # R_RISCV_GOT_HI20 (symbol_name)
+                //   ld    rd, rd, 0          # R_RISCV_PCREL_LO12_I (label)
+
+                // Create the label that is going to be published to the final binary object.
+                let auipc_label = sink.get_label();
+                sink.bind_label(auipc_label, &mut state.ctrl_plane);
+
+                // Get the current PC.
+                sink.add_reloc(Reloc::RiscvGotHi20, &**name, 0);
+                Inst::Auipc {
+                    rd,
+                    imm: Imm20::from_i32(0),
+                }
+                .emit_uncompressed(sink, emit_info, state, start_off);
+
+                // The `ld` here, points to the `auipc` label instead of directly to the symbol.
+                sink.add_reloc(Reloc::RiscvPCRelLo12I, &auipc_label, 0);
+                Inst::Load {
+                    rd,
+                    op: LoadOP::Ld,
+                    flags: MemFlags::trusted(),
+                    from: AMode::RegOffset(rd.to_reg(), 0),
+                }
+                .emit_uncompressed(sink, emit_info, state, start_off);
+            }
+
+            &Inst::LoadExtNameFar {
                 rd,
                 ref name,
                 offset,
             } => {
-                if emit_info.shared_flag.is_pic() {
-                    // Load a PC-relative address into a register.
-                    // RISC-V does this slightly differently from other arches. We emit a relocation
-                    // with a label, instead of the symbol itself.
-                    //
-                    // See: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses
-                    //
-                    // Emit the following code:
-                    // label:
-                    //   auipc rd, 0              # R_RISCV_GOT_HI20 (symbol_name)
-                    //   ld    rd, rd, 0          # R_RISCV_PCREL_LO12_I (label)
-
-                    // Create the label that is going to be published to the final binary object.
-                    let auipc_label = sink.get_label();
-                    sink.bind_label(auipc_label, &mut state.ctrl_plane);
-
-                    // Get the current PC.
-                    sink.add_reloc(Reloc::RiscvGotHi20, &**name, 0);
-                    Inst::Auipc {
-                        rd,
-                        imm: Imm20::from_i32(0),
-                    }
-                    .emit_uncompressed(sink, emit_info, state, start_off);
+                // In the non PIC sequence we relocate the absolute address into
+                // a preallocated space, load it into a register and jump over
+                // it.
+                //
+                // Emit the following code:
+                //   ld rd, label_data
+                //   j label_end
+                // label_data:
+                //   <8 byte space>           # ABS8
+                // label_end:
 
-                    // The `ld` here, points to the `auipc` label instead of directly to the symbol.
-                    sink.add_reloc(Reloc::RiscvPCRelLo12I, &auipc_label, 0);
-                    Inst::Load {
-                        rd,
-                        op: LoadOP::Ld,
-                        flags: MemFlags::trusted(),
-                        from: AMode::RegOffset(rd.to_reg(), 0),
-                    }
-                    .emit_uncompressed(sink, emit_info, state, start_off);
-                } else {
-                    // In the non PIC sequence we relocate the absolute address into
-                    // a prealocatted space, load it into a register and jump over it.
-                    //
-                    // Emit the following code:
-                    //   ld rd, label_data
-                    //   j label_end
-                    // label_data:
-                    //   <8 byte space>           # ABS8
-                    // label_end:
-
-                    let label_data = sink.get_label();
-                    let label_end = sink.get_label();
-
-                    // Load the value from a label
-                    Inst::Load {
-                        rd,
-                        op: LoadOP::Ld,
-                        flags: MemFlags::trusted(),
-                        from: AMode::Label(label_data),
-                    }
-                    .emit(sink, emit_info, state);
+                let label_data = sink.get_label();
+                let label_end = sink.get_label();
 
-                    // Jump over the data
-                    Inst::gen_jump(label_end).emit(sink, emit_info, state);
+                // Load the value from a label
+                Inst::Load {
+                    rd,
+                    op: LoadOP::Ld,
+                    flags: MemFlags::trusted(),
+                    from: AMode::Label(label_data),
+                }
+                .emit(sink, emit_info, state);
 
-                    sink.bind_label(label_data, &mut state.ctrl_plane);
-                    sink.add_reloc(Reloc::Abs8, name.as_ref(), offset);
-                    sink.put8(0);
+                // Jump over the data
+                Inst::gen_jump(label_end).emit(sink, emit_info, state);
 
-                    sink.bind_label(label_end, &mut state.ctrl_plane);
+                sink.bind_label(label_data, &mut state.ctrl_plane);
+                sink.add_reloc(Reloc::Abs8, name.as_ref(), offset);
+                sink.put8(0);
+
+                sink.bind_label(label_end, &mut state.ctrl_plane);
+            }
+
+            &Inst::LoadExtNameNear {
+                rd,
+                ref name,
+                offset,
+            } => {
+                // Emit the following code:
+                // label:
+                //   auipc rd, 0              # R_RISCV_PCREL_HI20 (symbol_name)
+                //   ld    rd, rd, 0          # R_RISCV_PCREL_LO12_I (label)
+
+                let auipc_label = sink.get_label();
+                sink.bind_label(auipc_label, &mut state.ctrl_plane);
+
+                // Get the current PC.
+                sink.add_reloc(Reloc::RiscvPCRelHi20, &**name, offset);
+                Inst::Auipc {
+                    rd,
+                    imm: Imm20::from_i32(0),
+                }
+                .emit_uncompressed(sink, emit_info, state, start_off);
+
+                sink.add_reloc(Reloc::RiscvPCRelLo12I, &auipc_label, 0);
+                Inst::AluRRImm12 {
+                    alu_op: AluOPRRI::Addi,
+                    rd,
+                    rs: rd.to_reg(),
+                    imm12: Imm12::ZERO,
                 }
+                .emit_uncompressed(sink, emit_info, state, start_off);
             }
 
             &Inst::ElfTlsGetAddr { rd, ref name } => {

cranelift/codegen/src/isa/riscv64/inst/mod.rs

@@ -390,7 +390,9 @@ fn riscv64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
             collector.reg_use(rs1);
             collector.reg_use(rs2);
         }
-        Inst::LoadExtName { rd, .. } => {
+        Inst::LoadExtNameGot { rd, .. }
+        | Inst::LoadExtNameNear { rd, .. }
+        | Inst::LoadExtNameFar { rd, .. } => {
             collector.reg_def(rd);
         }
         Inst::ElfTlsGetAddr { rd, .. } => {
@@ -1411,13 +1413,25 @@ impl Inst {
                     format!("{op_name} {rd},{src},({addr})")
                 }
             }
-            &MInst::LoadExtName {
+            &MInst::LoadExtNameGot { rd, ref name } => {
+                let rd = format_reg(rd.to_reg());
+                format!("load_ext_name_got {rd},{}", name.display(None))
+            }
+            &MInst::LoadExtNameNear {
+                rd,
+                ref name,
+                offset,
+            } => {
+                let rd = format_reg(rd.to_reg());
+                format!("load_ext_name_near {rd},{}{offset:+}", name.display(None))
+            }
+            &MInst::LoadExtNameFar {
                 rd,
                 ref name,
                 offset,
             } => {
                 let rd = format_reg(rd.to_reg());
-                format!("load_sym {},{}{:+}", rd, name.display(None), offset)
+                format!("load_ext_name_far {rd},{}{offset:+}", name.display(None))
             }
             &Inst::ElfTlsGetAddr { rd, ref name } => {
                 let rd = format_reg(rd.to_reg());

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -2379,8 +2379,8 @@
 
 ;;;;;  Rules for `func_addr`;;;;;;;;;
 (rule
-  (lower (func_addr (func_ref_data _ name _)))
-  (load_ext_name name 0))
+  (lower (func_addr (func_ref_data _ name dist)))
+  (load_ext_name name 0 dist))
 
 ;;;;;  Rules for `fcvt_to_uint`;;;;;;;;;
 
@@ -2538,8 +2538,8 @@
 
 ;;;;;  Rules for `symbol_value`;;;;;;;;;
 (rule
-   (lower (symbol_value (symbol_value_data name _ offset)))
-   (load_ext_name name offset))
+   (lower (symbol_value (symbol_value_data name dist offset)))
+   (load_ext_name name offset dist))
 
 ;;;;;  Rules for `tls_value` ;;;;;;;;;;;;;;
 
@@ -2679,12 +2679,12 @@
         output))
 
 ;; Direct call to an out-of-range function (implicitly via pointer).
-(rule (lower (call (func_ref_data sig_ref name _) args))
+(rule (lower (call (func_ref_data sig_ref name dist) args))
       (let ((output ValueRegsVec (gen_call_output sig_ref))
             (abi Sig (abi_sig sig_ref))
             (uses CallArgList (gen_call_args abi args))
             (defs CallRetList (gen_call_rets abi output))
-            (target Reg (load_ext_name name 0))
+            (target Reg (load_ext_name name 0 dist))
             (info BoxCallIndInfo (gen_call_ind_info abi target uses defs (try_call_none)))
             (_ Unit (emit_side_effect (call_ind_impl info))))
         output))
@@ -2712,12 +2712,12 @@
         (emit_side_effect (call_impl info))))
 
 ;; Direct call to an out-of-range function (implicitly via pointer).
-(rule (lower_branch (try_call (func_ref_data sig_ref name _) args et) targets)
+(rule (lower_branch (try_call (func_ref_data sig_ref name dist) args et) targets)
       (let ((abi Sig (abi_sig sig_ref))
             (trycall OptionTryCallInfo (try_call_info et targets))
             (uses CallArgList (gen_call_args abi args))
             (defs CallRetList (gen_try_call_rets abi))
-            (target Reg (load_ext_name name 0))
+            (target Reg (load_ext_name name 0 dist))
             (info BoxCallIndInfo (gen_call_ind_info abi target uses defs trycall)))
         (emit_side_effect (call_ind_impl info))))
 
@@ -2742,10 +2742,10 @@
         (side_effect (return_call_impl info))))
 
 ;; Direct call to an out-of-range function (implicitly via pointer).
-(rule (lower (return_call (func_ref_data sig_ref name _) args))
+(rule (lower (return_call (func_ref_data sig_ref name dist) args))
       (let ((abi Sig (abi_sig sig_ref))
             (uses CallArgList (gen_return_call_args abi args))
-            (target Reg (load_ext_name name 0))
+            (target Reg (load_ext_name name 0 dist))
             (info BoxReturnCallIndInfo (gen_return_call_ind_info abi target uses)))
         (side_effect (return_call_ind_impl info))))