x64: remove AluRM (#10494)

This `Inst` form was used for read-modify-write instructions during
lowering, but these have been replaced by the new assembler.

Author: abrown

cranelift/codegen/src/isa/x64/inst.isle

@@ -20,13 +20,6 @@
                 (src2 GprMemImm)
                 (dst WritableGpr))
 
-       ;; Integer arithmetic read-modify-write on memory.
-       (AluRM (size OperandSize) ;; 1, 2, 4 or 8
-              (op AluRmiROpcode)
-              (src1_dst SyntheticAmode)
-              (src2 Gpr)
-              (lock bool))
-
        ;; Integer arithmetic binary op that relies on the VEX prefix.
        ;; NOTE: we don't currently support emitting VEX instructions with memory
        ;; arguments, so `src2` is artificially constrained to be a Gpr.
@@ -5032,12 +5025,6 @@
         (if-let true (use_avx))
         (xmm_rmir_vex (AvxOpcode.Vpcmpgtq) x y))
 
-;; Helpers for read-modify-write ALU form (AluRM).
-(decl alu_rm (Type AluRmiROpcode Amode Gpr) SideEffectNoResult)
-(rule (alu_rm ty opcode src1_dst src2)
-      (let ((size OperandSize (operand_size_of_type_32_64 ty)))
-        (SideEffectNoResult.Inst (MInst.AluRM size opcode src1_dst src2 false))))
-
 (decl x64_add_mem (Type Amode Gpr) SideEffectNoResult)
 (spec (x64_add_mem ty addr val)
       (provide (= result (store_effect

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -250,47 +250,6 @@ pub(crate) fn emit(
             );
         }
 
-        Inst::AluRM {
-            size,
-            src1_dst,
-            src2,
-            op,
-            lock,
-        } => {
-            let src2 = src2.to_reg();
-            let src1_dst = src1_dst.finalize(state.frame_layout(), sink).clone();
-
-            let opcode = match op {
-                AluRmiROpcode::Add => 0x01,
-                AluRmiROpcode::Sub => 0x29,
-                AluRmiROpcode::And => 0x21,
-                AluRmiROpcode::Or => 0x09,
-                AluRmiROpcode::Xor => 0x31,
-                _ => panic!("Unsupported read-modify-write ALU opcode"),
-            };
-
-            let prefix = match (size, lock) {
-                (OperandSize::Size16, false) => LegacyPrefixes::_66,
-                (OperandSize::Size16, true) => LegacyPrefixes::_66F0,
-                (_, false) => LegacyPrefixes::None,
-                (_, true) => LegacyPrefixes::_F0,
-            };
-            let opcode = if *size == OperandSize::Size8 {
-                opcode - 1
-            } else {
-                opcode
-            };
-
-            let mut rex = RexFlags::from(*size);
-            if *size == OperandSize::Size8 {
-                debug_assert!(src2.is_real());
-                rex.always_emit_if_8bit_needed(src2);
-            }
-
-            let enc_g = int_reg_enc(src2);
-            emit_std_enc_mem(sink, prefix, opcode, 1, enc_g, &src1_dst, rex, 0);
-        }
-
         Inst::AluRmRVex {
             size,
             op,

cranelift/codegen/src/isa/x64/inst/emit_tests.rs

@@ -1629,243 +1629,6 @@ fn test_x64_emit() {
         "sbbq    %r15, 99(%rdi), %r15",
     ));
 
-    // ========================================================
-    // AluRM
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size32,
-            op: AluRmiROpcode::Add,
-            src1_dst: Amode::imm_reg(99, rdi).into(),
-            src2: Gpr::unwrap_new(r12),
-            lock: false,
-        },
-        "44016763",
-        "addl    %r12d, 99(%rdi)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size64,
-            op: AluRmiROpcode::Add,
-            src1_dst: Amode::imm_reg_reg_shift(0, Gpr::unwrap_new(rbp), Gpr::unwrap_new(rax), 3)
-                .into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "480144C500",
-        "addq    %rax, 0(%rbp,%rax,8)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size32,
-            op: AluRmiROpcode::Sub,
-            src1_dst: Amode::imm_reg(0, rsp).into(),
-            src2: Gpr::unwrap_new(rcx),
-            lock: false,
-        },
-        "290C24",
-        "subl    %ecx, 0(%rsp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size64,
-            op: AluRmiROpcode::Sub,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "48294500",
-        "subq    %rax, 0(%rbp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size32,
-            op: AluRmiROpcode::And,
-            src1_dst: Amode::imm_reg(0, rsp).into(),
-            src2: Gpr::unwrap_new(rcx),
-            lock: false,
-        },
-        "210C24",
-        "andl    %ecx, 0(%rsp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size64,
-            op: AluRmiROpcode::And,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "48214500",
-        "andq    %rax, 0(%rbp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size32,
-            op: AluRmiROpcode::Or,
-            src1_dst: Amode::imm_reg(0, rsp).into(),
-            src2: Gpr::unwrap_new(rcx),
-            lock: false,
-        },
-        "090C24",
-        "orl     %ecx, 0(%rsp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size64,
-            op: AluRmiROpcode::Or,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "48094500",
-        "orq     %rax, 0(%rbp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size32,
-            op: AluRmiROpcode::Xor,
-            src1_dst: Amode::imm_reg(0, rsp).into(),
-            src2: Gpr::unwrap_new(rcx),
-            lock: false,
-        },
-        "310C24",
-        "xorl    %ecx, 0(%rsp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size64,
-            op: AluRmiROpcode::Xor,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "48314500",
-        "xorq    %rax, 0(%rbp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size16,
-            op: AluRmiROpcode::Add,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "66014500",
-        "addw    %ax, 0(%rbp)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size16,
-            op: AluRmiROpcode::Sub,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(r12),
-            lock: false,
-        },
-        "6644296500",
-        "subw    %r12w, 0(%rbp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size8,
-            op: AluRmiROpcode::Add,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: false,
-        },
-        "004500",
-        "addb    %al, 0(%rbp)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size8,
-            op: AluRmiROpcode::Sub,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(rbp),
-            lock: false,
-        },
-        "40286D00",
-        "subb    %bpl, 0(%rbp)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size8,
-            op: AluRmiROpcode::Xor,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(r10),
-            lock: false,
-        },
-        "44305500",
-        "xorb    %r10b, 0(%rbp)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size8,
-            op: AluRmiROpcode::And,
-            src1_dst: Amode::imm_reg(0, rbp).into(),
-            src2: Gpr::unwrap_new(r15),
-            lock: false,
-        },
-        "44207D00",
-        "andb    %r15b, 0(%rbp)",
-    ));
-
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size64,
-            op: AluRmiROpcode::And,
-            src1_dst: Amode::imm_reg(0, rdx).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: true,
-        },
-        "F0482102",
-        "lock andq    %rax, 0(%rdx)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size32,
-            op: AluRmiROpcode::Or,
-            src1_dst: Amode::imm_reg(0, rdx).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: true,
-        },
-        "F00902",
-        "lock orl     %eax, 0(%rdx)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size16,
-            op: AluRmiROpcode::Xor,
-            src1_dst: Amode::imm_reg(0, rdx).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: true,
-        },
-        "66F03102",
-        "lock xorw    %ax, 0(%rdx)",
-    ));
-    insns.push((
-        Inst::AluRM {
-            size: OperandSize::Size8,
-            op: AluRmiROpcode::Add,
-            src1_dst: Amode::imm_reg(0, r9).into(),
-            src2: Gpr::unwrap_new(rax),
-            lock: true,
-        },
-        "F0410001",
-        "lock addb    %al, 0(%r9)",
-    ));
-
     // ========================================================
     // UnaryRmR
 

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -74,7 +74,6 @@ impl Inst {
             // These instructions are part of SSE2, which is a basic requirement in Cranelift, and
             // don't have to be checked.
             Inst::AluRmiR { .. }
-            | Inst::AluRM { .. }
             | Inst::AtomicRmwSeq { .. }
             | Inst::Bswap { .. }
             | Inst::CallKnown { .. }
@@ -713,20 +712,6 @@ impl PrettyPrint for Inst {
                 let op = ljustify2(op.to_string(), suffix_lqb(*size));
                 format!("{op} {dst}, {dst}, {dst}")
             }
-            Inst::AluRM {
-                size,
-                op,
-                src1_dst,
-                src2,
-                lock,
-            } => {
-                let size_bytes = size.to_bytes();
-                let src2 = pretty_print_reg(src2.to_reg(), size_bytes);
-                let src1_dst = src1_dst.pretty_print(size_bytes);
-                let op = ljustify2(op.to_string(), suffix_bwlq(*size));
-                let prefix = if *lock { "lock " } else { "" };
-                format!("{prefix}{op} {src2}, {src1_dst}")
-            }
             Inst::AluRmRVex {
                 size,
                 op,
@@ -2012,10 +1997,6 @@ fn x64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
             src2.get_operands(collector);
         }
         Inst::AluConstOp { dst, .. } => collector.reg_def(dst),
-        Inst::AluRM { src1_dst, src2, .. } => {
-            collector.reg_use(src2);
-            src1_dst.get_operands(collector);
-        }
         Inst::AluRmRVex {
             src1, src2, dst, ..
         } => {

cranelift/codegen/src/isa/x64/pcc.rs

@@ -158,17 +158,6 @@ pub(crate) fn check(
             }
         },
 
-        Inst::AluRM {
-            size,
-            op: _,
-            ref src1_dst,
-            src2: _,
-            lock: _,
-        } => {
-            check_load(ctx, None, src1_dst, vcode, size.to_type(), 64)?;
-            check_store(ctx, None, src1_dst, vcode, size.to_type())
-        }
-
         Inst::AluRmRVex {
             size,
             ref src2,