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S390x: emit new instructions added in z17 (#12319)
* s390x: Emit instructions from MIE4 & VXRS_EXT3 on z17 This emits & tests a bunch of instructions: * from Miscellaneous-Instruction-Extensions Facility 4: * CLZ, 64bit * CTZ, 64bit * from Vector-Enhancements Facility 3: * 32x4, 64x2 & 128x1 variants of the following: * Divide * Remainder * 64x2 & 128x1 multiply variants * 128x1 vaiants of: * Compare * CLZ * CTZ * Max * Min * Average * Negation * Evaluate Co-authored-by: Jimmy Brisson <[email protected]> * s390x: Emit vector blend on z17 * Rename x86_blendv to blendv Now that s390x implements blendv as well, we should refer to the instruction without the x86 prefix. --------- Co-authored-by: Ulrich Weigand <[email protected]>
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23 files changed

+3286
-101
lines changed

23 files changed

+3286
-101
lines changed

cranelift/codegen/meta/src/shared/instructions.rs

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@@ -1667,7 +1667,7 @@ pub(crate) fn define(
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ig.push(
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Inst::new(
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"x86_blendv",
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"blendv",
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r#"
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A bitselect-lookalike instruction except with the semantics of
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`blendv`-related instructions on x86.

cranelift/codegen/src/isa/aarch64/mod.rs

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@@ -227,7 +227,7 @@ impl TargetIsa for AArch64Backend {
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true
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}
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fn has_x86_blendv_lowering(&self, _: Type) -> bool {
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fn has_blendv_lowering(&self, _: Type) -> bool {
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false
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}
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cranelift/codegen/src/isa/mod.rs

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@@ -391,9 +391,9 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
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/// Returns whether this ISA has instructions for `ceil`, `floor`, etc.
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fn has_round(&self) -> bool;
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/// Returns whether the CLIF `x86_blendv` instruction is implemented for
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/// Returns whether the CLIF `blendv` instruction is implemented for
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/// this ISA for the specified type.
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fn has_x86_blendv_lowering(&self, ty: Type) -> bool;
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fn has_blendv_lowering(&self, ty: Type) -> bool;
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/// Returns whether the CLIF `x86_pshufb` instruction is implemented for
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/// this ISA.

cranelift/codegen/src/isa/pulley_shared/mod.rs

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@@ -232,7 +232,7 @@ where
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true
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}
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fn has_x86_blendv_lowering(&self, _ty: ir::Type) -> bool {
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fn has_blendv_lowering(&self, _ty: ir::Type) -> bool {
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false
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}
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cranelift/codegen/src/isa/riscv64/mod.rs

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@@ -205,7 +205,7 @@ impl TargetIsa for Riscv64Backend {
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true
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}
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fn has_x86_blendv_lowering(&self, _: Type) -> bool {
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fn has_blendv_lowering(&self, _: Type) -> bool {
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false
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}
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