From 97f1e927abcc98468b7045d2c02c78afc520792f Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 16:45:24 +0100 Subject: [PATCH 01/61] Move most things from std to core and alloc --- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/ctxhash.rs | 4 +-- cranelift/codegen/src/data_value.rs | 6 ++-- cranelift/codegen/src/dominator_tree.rs | 6 ++-- cranelift/codegen/src/egraph.rs | 4 +-- cranelift/codegen/src/egraph/cost.rs | 12 +++---- cranelift/codegen/src/egraph/elaborate.rs | 6 ++-- cranelift/codegen/src/incremental_cache.rs | 2 +- cranelift/codegen/src/ir/condcodes.rs | 2 +- cranelift/codegen/src/ir/constant.rs | 2 +- cranelift/codegen/src/ir/extname.rs | 2 +- cranelift/codegen/src/ir/instructions.rs | 6 ++-- cranelift/codegen/src/ir/jumptable.rs | 4 +-- cranelift/codegen/src/ir/memtype.rs | 6 ++-- cranelift/codegen/src/ir/pcc.rs | 18 +++++----- cranelift/codegen/src/isa/aarch64/abi.rs | 4 +-- .../src/isa/aarch64/inst/emit_tests.rs | 2 +- .../codegen/src/isa/aarch64/inst/imms.rs | 2 +- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 6 ++-- .../codegen/src/isa/aarch64/inst/regs.rs | 2 +- .../codegen/src/isa/aarch64/lower/isle.rs | 8 ++--- cranelift/codegen/src/isa/aarch64/mod.rs | 2 +- cranelift/codegen/src/isa/mod.rs | 6 ++-- .../codegen/src/isa/pulley_shared/abi.rs | 4 +-- .../src/isa/pulley_shared/inst/args.rs | 4 +-- .../codegen/src/isa/pulley_shared/inst/mod.rs | 2 +- .../codegen/src/isa/pulley_shared/mod.rs | 2 +- cranelift/codegen/src/isa/riscv64/abi.rs | 6 ++-- .../codegen/src/isa/riscv64/inst/args.rs | 6 ++-- .../src/isa/riscv64/inst/emit_tests.rs | 2 +- .../codegen/src/isa/riscv64/inst/imms.rs | 2 +- cranelift/codegen/src/isa/riscv64/inst/mod.rs | 10 +++--- .../codegen/src/isa/riscv64/lower/isle.rs | 4 +-- cranelift/codegen/src/isa/riscv64/mod.rs | 2 +- cranelift/codegen/src/isa/s390x/abi.rs | 6 ++-- .../codegen/src/isa/s390x/inst/emit_tests.rs | 16 ++++----- cranelift/codegen/src/isa/s390x/inst/imms.rs | 2 +- cranelift/codegen/src/isa/s390x/inst/mod.rs | 8 ++--- cranelift/codegen/src/isa/s390x/lower/isle.rs | 10 +++--- cranelift/codegen/src/isa/s390x/mod.rs | 2 +- cranelift/codegen/src/isa/unwind/systemv.rs | 6 ++-- cranelift/codegen/src/isa/winch.rs | 2 +- cranelift/codegen/src/isa/x64/abi.rs | 6 ++-- cranelift/codegen/src/isa/x64/inst/args.rs | 6 ++-- cranelift/codegen/src/isa/x64/inst/emit.rs | 2 +- .../codegen/src/isa/x64/inst/emit_tests.rs | 2 +- .../codegen/src/isa/x64/inst/external.rs | 2 +- cranelift/codegen/src/isa/x64/inst/mod.rs | 8 ++--- cranelift/codegen/src/isa/x64/inst/regs.rs | 2 +- cranelift/codegen/src/isa/x64/lower.rs | 2 +- cranelift/codegen/src/isa/x64/lower/isle.rs | 2 +- cranelift/codegen/src/isa/x64/mod.rs | 2 +- cranelift/codegen/src/isle_prelude.rs | 4 +-- .../codegen/src/legalizer/globalvalue.rs | 2 +- cranelift/codegen/src/loop_analysis.rs | 4 +-- cranelift/codegen/src/machinst/abi.rs | 12 +++---- cranelift/codegen/src/machinst/blockorder.rs | 2 +- cranelift/codegen/src/machinst/buffer.rs | 12 +++---- cranelift/codegen/src/machinst/helpers.rs | 2 +- cranelift/codegen/src/machinst/isle.rs | 4 +-- cranelift/codegen/src/machinst/lower.rs | 6 ++-- cranelift/codegen/src/machinst/mod.rs | 4 +-- cranelift/codegen/src/machinst/reg.rs | 36 +++++++++---------- cranelift/codegen/src/machinst/valueregs.rs | 2 +- cranelift/codegen/src/machinst/vcode.rs | 11 +++--- cranelift/codegen/src/opts.rs | 2 +- cranelift/codegen/src/remove_constant_phis.rs | 2 +- cranelift/codegen/src/result.rs | 10 +++--- cranelift/codegen/src/settings.rs | 2 +- cranelift/codegen/src/take_and_replace.rs | 4 +-- cranelift/codegen/src/timing.rs | 14 ++++---- cranelift/codegen/src/verifier/mod.rs | 8 ++--- 72 files changed, 194 insertions(+), 193 deletions(-) diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 56d90b18975c..32112265eb68 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -65,7 +65,7 @@ default = ["std", "unwind", "host-arch", "timing"] # The "std" feature enables use of libstd. The "core" feature enables use # of some minimal std-like replacement libraries. At least one of these two # features need to be enabled. -std = ["serde?/std"] +std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # The "core" feature used to enable a hashmap workaround, but is now # deprecated (we (i) always use hashbrown, and (ii) don't support a diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 98931566aad3..10fe7af5b032 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -5,7 +5,7 @@ //! an array or pool of shared data). use hashbrown::hash_table::HashTable; -use std::hash::{Hash, Hasher}; +use core::hash::{Hash, Hasher}; /// Trait that allows for equality comparison given some external /// context. @@ -92,7 +92,7 @@ impl CtxHashMap { match self.raw.find_mut(hash as u64, |bucket| { hash == bucket.hash && ctx.ctx_eq(&bucket.k, &k) }) { - Some(bucket) => Some(std::mem::replace(&mut bucket.v, v)), + Some(bucket) => Some(core::mem::replace(&mut bucket.v, v)), None => { let data = BucketData { hash, k, v }; self.raw diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index 4eeb8c117ace..a2e69a724e1b 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -247,13 +247,13 @@ impl DataValue { /// Write a [DataValue] to a memory location in native-endian byte order. pub unsafe fn write_value_to(&self, p: *mut u128) { let size = self.ty().bytes() as usize; - self.write_to_slice_ne(unsafe { std::slice::from_raw_parts_mut(p as *mut u8, size) }); + self.write_to_slice_ne(unsafe { core::slice::from_raw_parts_mut(p as *mut u8, size) }); } /// Read a [DataValue] from a memory location using a given [Type] in native-endian byte order. pub unsafe fn read_value_from(p: *const u128, ty: Type) -> Self { DataValue::read_from_slice_ne( - unsafe { std::slice::from_raw_parts(p as *const u8, ty.bytes() as usize) }, + unsafe { core::slice::from_raw_parts(p as *const u8, ty.bytes() as usize) }, ty, ) } @@ -290,7 +290,7 @@ pub enum DataValueCastFailure { // This is manually implementing Error and Display instead of using thiserror to reduce the amount // of dependencies used by Cranelift. -impl std::error::Error for DataValueCastFailure {} +impl core::error::Error for DataValueCastFailure {} impl Display for DataValueCastFailure { fn fmt(&self, f: &mut Formatter) -> fmt::Result { diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 10ab9c891ebb..23d099a4251a 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -94,7 +94,7 @@ impl SpanningTree { } } -impl std::ops::Index for SpanningTree { +impl core::ops::Index for SpanningTree { type Output = SpanningTreeNode; fn index(&self, idx: u32) -> &Self::Output { @@ -102,7 +102,7 @@ impl std::ops::Index for SpanningTree { } } -impl std::ops::IndexMut for SpanningTree { +impl core::ops::IndexMut for SpanningTree { fn index_mut(&mut self, idx: u32) -> &mut Self::Output { &mut self.nodes[idx as usize] } @@ -439,7 +439,7 @@ impl DominatorTree { } let semi_candidate = self.eval(self.nodes[pred].pre_number, last_linked); - semi = std::cmp::min(semi, semi_candidate); + semi = core::cmp::min(semi, semi_candidate); } let w_node = &mut self.stree[w]; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph.rs index 9993f7941f10..46fdaf36985b 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph.rs @@ -660,7 +660,7 @@ where let old_vals = ctx.func.dfg.inst_results(inst); let new_vals = if let Some(val) = new_val.as_ref() { - std::slice::from_ref(val) + core::slice::from_ref(val) } else { ctx.func.dfg.inst_results(new_inst) }; @@ -1075,7 +1075,7 @@ impl<'a> CtxEq<(Type, InstructionData), (Type, InstructionData)> for GVNContext< impl<'a> CtxHash<(Type, InstructionData)> for GVNContext<'a> { fn ctx_hash(&self, state: &mut H, (ty, inst): &(Type, InstructionData)) { - std::hash::Hash::hash(&ty, state); + core::hash::Hash::hash(&ty, state); inst.hash(state, self.value_lists); } } diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index 1ff56fcd61f9..062196964c96 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -48,7 +48,7 @@ impl core::fmt::Debug for Cost { impl Ord for Cost { #[inline] - fn cmp(&self, other: &Self) -> std::cmp::Ordering { + fn cmp(&self, other: &Self) -> core::cmp::Ordering { // We make sure that the high bits are the op cost and the low bits are // the depth. This means that we can use normal integer comparison to // order by op cost and then depth. @@ -65,7 +65,7 @@ impl Ord for Cost { impl PartialOrd for Cost { #[inline] - fn partial_cmp(&self, other: &Self) -> Option { + fn partial_cmp(&self, other: &Self) -> Option { Some(self.cmp(other)) } } @@ -172,24 +172,24 @@ impl Cost { } } -impl std::iter::Sum for Cost { +impl core::iter::Sum for Cost { fn sum>(iter: I) -> Self { iter.fold(Self::zero(), |a, b| a + b) } } -impl std::default::Default for Cost { +impl core::default::Default for Cost { fn default() -> Cost { Cost::zero() } } -impl std::ops::Add for Cost { +impl core::ops::Add for Cost { type Output = Cost; fn add(self, other: Cost) -> Cost { let op_cost = self.op_cost().saturating_add(other.op_cost()); - let depth = std::cmp::max(self.depth(), other.depth()); + let depth = core::cmp::max(self.depth(), other.depth()); Cost::new(op_cost, depth) } } diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index d9d156eb41c8..9328354b2dc2 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -82,7 +82,7 @@ impl PartialOrd for BestEntry { impl Ord for BestEntry { #[inline] - fn cmp(&self, other: &Self) -> std::cmp::Ordering { + fn cmp(&self, other: &Self) -> core::cmp::Ordering { self.0.cmp(&other.0).then_with(|| { // Note that this comparison is reversed. When costs are equal, // prefer the value with the bigger index. This is a heuristic that @@ -321,9 +321,9 @@ impl<'a> Elaborator<'a> { debug_assert!(!best[x].1.is_reserved_value()); debug_assert!(!best[y].1.is_reserved_value()); best[value] = if use_worst { - std::cmp::max(best[x], best[y]) + core::cmp::max(best[x], best[y]) } else { - std::cmp::min(best[x], best[y]) + core::cmp::min(best[x], best[y]) }; trace!( " -> best of union({:?}, {:?}) = {:?}", diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index 9b9d935241e8..a597d18869ce 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -111,7 +111,7 @@ pub trait CacheKvStore { #[derive(Clone, Hash, PartialEq, Eq)] pub struct CacheKeyHash([u8; 32]); -impl std::fmt::Display for CacheKeyHash { +impl core::fmt::Display for CacheKeyHash { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "CacheKeyHash:{:?}", self.0) } diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index e791649bb69c..009f95bf391c 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -344,7 +344,7 @@ impl FromStr for FloatCC { #[cfg(test)] mod tests { use super::*; - use std::string::ToString; + use alloc::string::ToString; #[test] fn int_complement() { diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index a9ac61e06a02..67310cd9462f 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -272,7 +272,7 @@ impl ConstantPool { #[cfg(test)] mod tests { use super::*; - use std::string::ToString; + use alloc::string::ToString; #[test] fn empty() { diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index f29d854b1a44..d28ebcb4e7b2 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -99,7 +99,7 @@ pub struct TestcaseName(Box<[u8]>); impl fmt::Display for TestcaseName { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.write_char('%')?; - f.write_str(std::str::from_utf8(&self.0).unwrap()) + f.write_str(core::str::from_utf8(&self.0).unwrap()) } } diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 2b94d9da1e33..80c04e48e6fb 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -429,7 +429,7 @@ impl InstructionData { exception_tables: &'a ir::ExceptionTables, ) -> &'a [BlockCall] { match self { - Self::Jump { destination, .. } => std::slice::from_ref(destination), + Self::Jump { destination, .. } => core::slice::from_ref(destination), Self::Brif { blocks, .. } => blocks.as_slice(), Self::BranchTable { table, .. } => jump_tables.get(*table).unwrap().all_branches(), Self::TryCall { exception, .. } | Self::TryCallIndirect { exception, .. } => { @@ -451,7 +451,7 @@ impl InstructionData { exception_tables: &'a mut ir::ExceptionTables, ) -> &'a mut [BlockCall] { match self { - Self::Jump { destination, .. } => std::slice::from_mut(destination), + Self::Jump { destination, .. } => core::slice::from_mut(destination), Self::Brif { blocks, .. } => blocks.as_mut_slice(), Self::BranchTable { table, .. } => { jump_tables.get_mut(*table).unwrap().all_branches_mut() @@ -1162,7 +1162,7 @@ mod tests { fn inst_data_size() { // The size of `InstructionData` is performance sensitive, so make sure // we don't regress it unintentionally. - assert_eq!(std::mem::size_of::(), 16); + assert_eq!(core::mem::size_of::(), 16); } #[test] diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 5a26ef4e4768..5bdad87d941f 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -31,7 +31,7 @@ impl JumpTableData { /// Create a new jump table with the provided blocks. pub fn new(def: BlockCall, table: &[BlockCall]) -> Self { Self { - table: std::iter::once(def).chain(table.iter().copied()).collect(), + table: core::iter::once(def).chain(table.iter().copied()).collect(), } } @@ -114,8 +114,8 @@ mod tests { use crate::entity::EntityRef; use crate::ir::instructions::ValueListPool; use crate::ir::{Block, BlockArg, BlockCall, Value}; + use alloc::string::ToString; use alloc::vec::Vec; - use std::string::ToString; #[test] fn empty() { diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index 4df26f1647e5..b7b0d7e2db1e 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -108,14 +108,14 @@ pub enum MemoryTypeData { Empty, } -impl std::default::Default for MemoryTypeData { +impl core::default::Default for MemoryTypeData { fn default() -> Self { Self::Empty } } -impl std::fmt::Display for MemoryTypeData { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::Display for MemoryTypeData { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self { Self::Struct { size, fields } => { write!(f, "struct {size} {{")?; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index 4fb88fd02ebf..b10f43f78d06 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -78,13 +78,13 @@ use crate::isa::TargetIsa; use crate::machinst::{BlockIndex, LowerBackend, VCode}; use crate::trace; use regalloc2::Function as _; -use std::fmt; +use core::fmt; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; /// The result of checking proof-carrying-code facts. -pub type PccResult = std::result::Result; +pub type PccResult = core::result::Result; /// An error or inconsistency discovered when checking proof-carrying /// code. @@ -332,7 +332,7 @@ impl Expr { } else { Expr { base: BaseExpr::min(&lhs.base, &rhs.base), - offset: std::cmp::min(lhs.offset, rhs.offset), + offset: core::cmp::min(lhs.offset, rhs.offset), } } } @@ -347,7 +347,7 @@ impl Expr { } else { Expr { base: BaseExpr::max(&lhs.base, &rhs.base), - offset: std::cmp::max(lhs.offset, rhs.offset), + offset: core::cmp::max(lhs.offset, rhs.offset), } } } @@ -651,8 +651,8 @@ impl Fact { }, ) if bw_lhs == bw_rhs && max_lhs >= min_rhs && max_rhs >= min_lhs => Fact::Range { bit_width: *bw_lhs, - min: std::cmp::max(*min_lhs, *min_rhs), - max: std::cmp::min(*max_lhs, *max_rhs), + min: core::cmp::max(*min_lhs, *min_rhs), + max: core::cmp::min(*max_lhs, *max_rhs), }, ( @@ -693,8 +693,8 @@ impl Fact { { Fact::Mem { ty: *ty_lhs, - min_offset: std::cmp::max(*min_offset_lhs, *min_offset_rhs), - max_offset: std::cmp::min(*max_offset_lhs, *max_offset_rhs), + min_offset: core::cmp::max(*min_offset_lhs, *min_offset_rhs), + max_offset: core::cmp::min(*max_offset_lhs, *max_offset_rhs), nullable: *nullable_lhs && *nullable_rhs, } } @@ -910,7 +910,7 @@ impl<'a> FactContext<'a> { ) if bw_lhs == bw_rhs && add_width >= *bw_lhs => { let computed_min = min_lhs.checked_add(*min_rhs)?; let computed_max = max_lhs.checked_add(*max_rhs)?; - let computed_max = std::cmp::min(max_value_for_width(add_width), computed_max); + let computed_max = core::cmp::min(max_value_for_width(add_width), computed_max); Some(Fact::Range { bit_width: *bw_lhs, min: computed_min, diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 20f8476a604a..c7443cfd7c22 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -16,7 +16,7 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::borrow::ToOwned; +use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because @@ -348,7 +348,7 @@ impl ABIMachineSpec for AArch64MachineDeps { } else { // Every arg takes a minimum slot of 8 bytes. (16-byte stack // alignment happens separately after all args.) - std::cmp::max(size, 8) + core::cmp::max(size, 8) }; if !is_winch_return { diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index d8e6cd6a2083..baa42a265cb2 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -27,7 +27,7 @@ fn test_aarch64_binemit() { // // #!/bin/sh // tmp=`mktemp /tmp/XXXXXXXX.o` - // aarch64-linux-gnu-as /dev/stdin -o $tmp + // aarch64-linux-gnu-as /dev/corein -o $tmp // aarch64-linux-gnu-objdump -d $tmp // rm -f $tmp // diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index e408f26985a9..fcd67deed576 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -4,7 +4,7 @@ use crate::ir::types::*; use crate::isa::aarch64::inst::{OperandSize, ScalarSize}; use crate::machinst::PrettyPrint; -use std::string::String; +use alloc::string::String; /// An immediate that represents the NZCV flags. #[derive(Clone, Copy, Debug)] diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index cc5ff8eb3aec..c47e20f94280 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -12,8 +12,8 @@ use crate::machinst::{PrettyPrint, Reg, RegClass, Writable}; use alloc::vec::Vec; use core::slice; use smallvec::{SmallVec, smallvec}; -use std::fmt::Write; -use std::string::{String, ToString}; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub(crate) mod regs; pub(crate) use self::regs::*; @@ -3109,6 +3109,6 @@ mod tests { } else { 32 }; - assert_eq!(expected, std::mem::size_of::()); + assert_eq!(expected, core::mem::size_of::()); } } diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index f5a6eb526daf..7db69df4ebe4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -8,7 +8,7 @@ use crate::machinst::{Reg, RegClass, Writable}; use regalloc2::PReg; use regalloc2::VReg; -use std::string::{String, ToString}; +use alloc::string::{String, ToString}; //============================================================================= // Registers, the Universe thereof, and printing diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index b372ace5cb2d..307414f1012b 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -33,8 +33,8 @@ use crate::{ }; use core::u32; use regalloc2::PReg; -use std::boxed::Box; -use std::vec::Vec; +use alloc::boxed::Box; +use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxCallIndInfo = Box>; @@ -237,7 +237,7 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { fn lshl_from_u64(&mut self, ty: Type, n: u64) -> Option { let shiftimm = ShiftOpShiftImm::maybe_from_shift(n)?; let shiftee_bits = ty_bits(ty); - if shiftee_bits <= std::u8::MAX as usize { + if shiftee_bits <= core::u8::MAX as usize { let shiftimm = shiftimm.mask(shiftee_bits as u8); Some(ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm)) } else { @@ -248,7 +248,7 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { fn ashr_from_u64(&mut self, ty: Type, n: u64) -> Option { let shiftimm = ShiftOpShiftImm::maybe_from_shift(n)?; let shiftee_bits = ty_bits(ty); - if shiftee_bits <= std::u8::MAX as usize { + if shiftee_bits <= core::u8::MAX as usize { let shiftimm = shiftimm.mask(shiftee_bits as u8); Some(ShiftOpAndAmt::new(ShiftOp::ASR, shiftimm)) } else { diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 892911edd833..5c265aebeb0d 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -15,7 +15,7 @@ use crate::settings as shared_settings; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use std::string::String; +use alloc::string::String; use target_lexicon::{Aarch64Architecture, Architecture, OperatingSystem, Triple}; // New backend: diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 8728c299c1b4..2bc2033983ef 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -23,7 +23,7 @@ //! # #[macro_use] extern crate target_lexicon; //! use cranelift_codegen::isa; //! use cranelift_codegen::settings::{self, Configurable}; -//! use std::str::FromStr; +//! use core::str::FromStr; //! use target_lexicon::Triple; //! //! let shared_builder = settings::builder(); @@ -55,11 +55,11 @@ use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; use crate::{Reg, flowgraph}; +use alloc::string::String; use alloc::{boxed::Box, sync::Arc, vec::Vec}; use core::fmt; use core::fmt::{Debug, Formatter}; use cranelift_control::ControlPlane; -use std::string::String; use target_lexicon::{Architecture, PointerWidth, Triple, triple}; // This module is made public here for benchmarking purposes. No guarantees are @@ -146,7 +146,7 @@ pub enum LookupError { // This is manually implementing Error and Display instead of using thiserror to reduce the amount // of dependencies used by Cranelift. -impl std::error::Error for LookupError {} +impl core::error::Error for LookupError {} impl fmt::Display for LookupError { fn fmt(&self, f: &mut Formatter) -> fmt::Result { diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 3529408fb50e..72bafa7c30d6 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -14,7 +14,7 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::borrow::ToOwned; +use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). @@ -130,7 +130,7 @@ where // Compute size and 16-byte stack alignment happens // separately after all args. let size = reg_ty.bits() / 8; - let size = std::cmp::max(size, 8); + let size = core::cmp::max(size, 8); // Align. debug_assert!(size.is_power_of_two()); diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index 6ddd6a09dc98..b53f5d3fafa6 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -5,7 +5,7 @@ use crate::ir::ExternalName; use crate::machinst::abi::StackAMode; use pulley_interpreter::encode; use pulley_interpreter::regs::Reg as _; -use std::fmt; +use core::fmt; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). @@ -61,7 +61,7 @@ macro_rules! newtype_of_reg { // NB: We cannot implement `DerefMut` because that would let people do // nasty stuff like `*my_xreg.deref_mut() = some_freg`, breaking the // invariants that `XReg` provides. - impl std::ops::Deref for $newtype_reg { + impl core::ops::Deref for $newtype_reg { type Target = Reg; fn deref(&self) -> &Reg { diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index 9bf27e8b8aca..d76705a7fb9f 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -611,7 +611,7 @@ const TRAP_OPCODE: &'static [u8] = &[ #[test] fn test_trap_encoding() { - let mut dst = std::vec::Vec::new(); + let mut dst = alloc::vec::Vec::new(); pulley_interpreter::encode::trap(&mut dst); assert_eq!(dst, TRAP_OPCODE); } diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index c3f16efa2b33..018c859d4e41 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -21,7 +21,7 @@ use alloc::vec::Vec; use core::fmt::Debug; use core::marker::PhantomData; use cranelift_control::ControlPlane; -use std::string::String; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; pub use settings::Flags as PulleyFlags; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index 129255219225..70c799cd06d0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -20,7 +20,7 @@ use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::borrow::ToOwned; +use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). @@ -59,7 +59,7 @@ impl RiscvFlags { // Due to a limitation in regalloc2, we can't support types // larger than 1024 bytes. So limit that here. - return std::cmp::min(size, 1024); + return core::cmp::min(size, 1024); } return 0; @@ -165,7 +165,7 @@ impl ABIMachineSpec for Riscv64MachineDeps { // Compute size and 16-byte stack alignment happens // separately after all args. let size = reg_ty.bits() / 8; - let size = std::cmp::max(size, 8); + let size = core::cmp::max(size, 8); // Align. debug_assert!(size.is_power_of_two()); next_stack = align_to(next_stack, size); diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index a4cca654296e..918a4854b3a3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -8,7 +8,7 @@ use crate::isa::riscv64::lower::isle::generated_code::{ }; use crate::machinst::isle::WritableReg; -use std::fmt::Result; +use core::fmt::Result; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). @@ -53,7 +53,7 @@ macro_rules! newtype_of_reg { // NB: We cannot implement `DerefMut` because that would let people do // nasty stuff like `*my_xreg.deref_mut() = some_freg`, breaking the // invariants that `XReg` provides. - impl std::ops::Deref for $newtype_reg { + impl core::ops::Deref for $newtype_reg { type Target = Reg; fn deref(&self) -> &Reg { @@ -651,7 +651,7 @@ impl Display for FpuOPWidth { impl TryFrom for FpuOPWidth { type Error = &'static str; - fn try_from(value: Type) -> std::result::Result { + fn try_from(value: Type) -> core::result::Result { match value { F16 => Ok(FpuOPWidth::H), F32 => Ok(FpuOPWidth::S), diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 9ad30a98d0be..3b0cf59b633f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -1,6 +1,6 @@ use crate::isa::riscv64::inst::*; use crate::isa::riscv64::lower::isle::generated_code::FpuOPWidth; -use std::borrow::Cow; +use alloc::borrow::Cow; fn fa7() -> Reg { f_reg(17) diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 1b9621231a1b..92a8ceb60b83 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -2,7 +2,7 @@ // Some variants are never constructed, but we still want them as options in the future. use super::Inst; -use std::fmt::{Debug, Display, Formatter, Result}; +use core::fmt::{Debug, Display, Formatter, Result}; #[derive(Copy, Clone, Debug, Default)] pub struct Imm12 { diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 2521e8d358b9..8db973aa426e 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -15,9 +15,9 @@ pub use crate::ir::condcodes::FloatCC; use alloc::vec::Vec; use regalloc2::RegClass; use smallvec::{SmallVec, smallvec}; -use std::boxed::Box; -use std::fmt::Write; -use std::string::{String, ToString}; +use alloc::boxed::Box; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; @@ -38,7 +38,7 @@ use crate::isa::riscv64::abi::Riscv64MachineDeps; #[cfg(test)] mod emit_tests; -use std::fmt::{Display, Formatter}; +use core::fmt::{Display, Formatter}; pub(crate) type VecU8 = Vec; @@ -85,7 +85,7 @@ impl CondBrTarget { } impl Display for CondBrTarget { - fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result { match self { CondBrTarget::Label(l) => write!(f, "{}", l.to_string()), CondBrTarget::Fallthrough => write!(f, "0"), diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index 87bf480f2f5f..e567660def01 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -22,8 +22,8 @@ use crate::{ machinst::{ArgPair, CallArgList, CallRetList, InstOutput}, }; use regalloc2::PReg; -use std::boxed::Box; -use std::vec::Vec; +use alloc::boxed::Box; +use alloc::vec::Vec; use wasmtime_math::{f32_cvt_to_int_bounds, f64_cvt_to_int_bounds}; type BoxCallInfo = Box>; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 873b69851090..49060989a2df 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -16,7 +16,7 @@ use crate::{CodegenError, ir}; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use std::string::String; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; mod abi; pub(crate) mod inst; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 7b8ad6da166e..8174d3479106 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -147,7 +147,7 @@ use crate::settings; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::borrow::ToOwned; +use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -399,11 +399,11 @@ impl ABIMachineSpec for S390xMachineDeps { // Compute size. Every argument or return value takes a slot of // at least 8 bytes. let size = (ty_bits(param.value_type) / 8) as u32; - let slot_size = std::cmp::max(size, 8); + let slot_size = core::cmp::max(size, 8); // Align the stack slot. debug_assert!(slot_size.is_power_of_two()); - let slot_align = std::cmp::min(slot_size, 8); + let slot_align = core::cmp::min(slot_size, 8); next_stack = align_to(next_stack, slot_align); // If the type is actually of smaller size (and the argument diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index aa6f9e6b19c9..569c16ac5c4d 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -12039,7 +12039,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102000", - "std %f1, 0(%r2)", + "core %f1, 0(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12054,7 +12054,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102FFF", - "std %f1, 4095(%r2)", + "core %f1, 4095(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12069,7 +12069,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1020008067", - "stdy %f1, -524288(%r2)", + "corey %f1, -524288(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12084,7 +12084,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED102FFF7F67", - "stdy %f1, 524287(%r2)", + "corey %f1, 524287(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12129,7 +12129,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123000", - "std %f1, 0(%r2,%r3)", + "core %f1, 0(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12144,7 +12144,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123FFF", - "std %f1, 4095(%r2,%r3)", + "core %f1, 4095(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12159,7 +12159,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1230008067", - "stdy %f1, -524288(%r2,%r3)", + "corey %f1, -524288(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12174,7 +12174,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED123FFF7F67", - "stdy %f1, 524287(%r2,%r3)", + "corey %f1, 524287(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 8ceebbcdac15..9559f34ac7f8 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,7 +1,7 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; -use std::string::String; +use alloc::string::String; /// An unsigned 12-bit immediate. #[derive(Clone, Copy, Debug)] diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 1e9c0aeb72be..7d9757bae776 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -9,8 +9,8 @@ use crate::{CodegenError, CodegenResult, settings}; use alloc::boxed::Box; use alloc::vec::Vec; use smallvec::SmallVec; -use std::fmt::Write; -use std::string::{String, ToString}; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; pub mod imms; @@ -55,7 +55,7 @@ pub struct ReturnCallInfo { fn inst_size_test() { // This test will help with unintentionally growing the size // of the Inst enum. - assert_eq!(32, std::mem::size_of::()); + assert_eq!(32, core::mem::size_of::()); } /// A register pair. Enum so it can be destructured in ISLE. @@ -2968,7 +2968,7 @@ impl Inst { (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None), (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None), (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")), - (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")), + (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("core"), Some("corey")), (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None), (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None), (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None), diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index b4bbbc7ec9c1..02765c8b7bbf 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -24,9 +24,9 @@ use crate::{ }, }; use regalloc2::PReg; -use std::boxed::Box; -use std::cell::Cell; -use std::vec::Vec; +use alloc::boxed::Box; +use core::cell::Cell; +use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxReturnCallInfo = Box>; @@ -631,7 +631,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, S390xBackend> { #[inline] fn fcvt_to_sint_lb32(&mut self, size: u8) -> u64 { let lb = (-2.0_f32).powi((size - 1).into()); - std::cmp::max(lb.to_bits() + 1, (lb - 1.0).to_bits()) as u64 + core::cmp::max(lb.to_bits() + 1, (lb - 1.0).to_bits()) as u64 } #[inline] @@ -642,7 +642,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, S390xBackend> { #[inline] fn fcvt_to_sint_lb64(&mut self, size: u8) -> u64 { let lb = (-2.0_f64).powi((size - 1).into()); - std::cmp::max(lb.to_bits() + 1, (lb - 1.0).to_bits()) + core::cmp::max(lb.to_bits() + 1, (lb - 1.0).to_bits()) } #[inline] diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 8768b4eebf84..511ddf77305d 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -15,7 +15,7 @@ use crate::settings as shared_settings; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use std::string::String; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; // New backend: diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index d85694e87852..5989e0b2a12b 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -23,10 +23,10 @@ pub enum RegisterMappingError { // This is manually implementing Error and Display instead of using thiserror to reduce the amount // of dependencies used by Cranelift. -impl std::error::Error for RegisterMappingError {} +impl core::error::Error for RegisterMappingError {} -impl std::fmt::Display for RegisterMappingError { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::Display for RegisterMappingError { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self { RegisterMappingError::MissingBank => write!(f, "unable to find bank for register info"), RegisterMappingError::UnsupportedArchitecture => write!( diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index c37ddd373ee0..df8fdce35223 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -8,7 +8,7 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext for slot in slots.iter_mut() { if let ABIArgSlot::Stack { offset, ty, .. } = slot { let size = if uses_extension { - i64::from(std::cmp::max(ty.bytes(), 8)) + i64::from(core::cmp::max(ty.bytes(), 8)) } else { i64::from(ty.bytes()) }; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 81897510640d..cd07032c2bc2 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -9,14 +9,14 @@ use crate::isa::{CallConv, unwind::UnwindInst, x64::inst::*, x64::settings as x6 use crate::machinst::abi::*; use crate::machinst::*; use crate::settings; +use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use args::*; +use std::sync::OnceLock; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::borrow::ToOwned; -use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -358,7 +358,7 @@ impl ABIMachineSpec for X64ABIMachineSpec { { size } else { - let size = std::cmp::max(size, 8); + let size = core::cmp::max(size, 8); // Align. debug_assert!(size.is_power_of_two()); diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index c34983643e87..35c22ca49b3c 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,8 +7,8 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use std::fmt; -use std::string::String; +use core::fmt; +use alloc::string::String; /// An extension trait for converting `Writable{Xmm,Gpr}` to `Writable`. pub trait ToWritableReg { @@ -87,7 +87,7 @@ macro_rules! newtype_of_reg { // NB: We cannot implement `DerefMut` because that would let people do // nasty stuff like `*my_gpr.deref_mut() = some_xmm_reg`, breaking the // invariants that `Gpr` provides. - impl std::ops::Deref for $newtype_reg { + impl core::ops::Deref for $newtype_reg { type Target = Reg; fn deref(&self) -> &Reg { diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 406f9961f7ca..363f9194bd6f 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -735,7 +735,7 @@ pub(crate) fn emit( // Emit jump table (table of 32-bit offsets). sink.bind_label(start_of_jumptable, state.ctrl_plane_mut()); let jt_off = sink.cur_offset(); - for &target in targets.iter().chain(std::iter::once(default_target)) { + for &target in targets.iter().chain(core::iter::once(default_target)) { let word_off = sink.cur_offset(); // off_into_table is an addend here embedded in the label to be later patched at // the end of codegen. The offset is initially relative to this jump table entry; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 1bd8b0f6b28e..9e47ea081b56 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -2,7 +2,7 @@ //! //! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases. //! -//! to see stdout: cargo test -- --nocapture +//! to see coreout: cargo test -- --nocapture //! //! for this specific case, as of 24 Aug 2020: //! diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 2394103a63f6..b326429501e3 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -7,7 +7,7 @@ use super::{ use crate::{Reg, Writable, ir::TrapCode}; use cranelift_assembler_x64 as asm; use regalloc2::{PReg, RegClass}; -use std::string::String; +use alloc::string::String; /// Define the types of registers Cranelift will use. #[derive(Clone, Debug)] diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 298dc938b235..4c77b2c564b1 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -16,8 +16,8 @@ use alloc::vec::Vec; use core::slice; use cranelift_assembler_x64 as asm; use smallvec::{SmallVec, smallvec}; -use std::fmt::{self, Write}; -use std::string::{String, ToString}; +use core::fmt::{self, Write}; +use alloc::string::{String, ToString}; pub mod args; mod emit; @@ -60,7 +60,7 @@ pub struct ReturnCallInfo { fn inst_size_test() { // This test will help with unintentionally growing the size // of the Inst enum. - assert_eq!(48, std::mem::size_of::()); + assert_eq!(48, core::mem::size_of::()); } impl Inst { @@ -1384,7 +1384,7 @@ impl MachInst for Inst { } fn gen_nop(preferred_size: usize) -> Inst { - Inst::nop(std::cmp::min(preferred_size, 9) as u8) + Inst::nop(core::cmp::min(preferred_size, 9) as u8) } fn gen_nop_units() -> Vec> { diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index f4c0fc2abbfc..2bcc23d8c426 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -9,7 +9,7 @@ use crate::machinst::Reg; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; use regalloc2::{PReg, RegClass, VReg}; -use std::string::String; +use alloc::string::String; // Constructors for Regs. diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 522a155ff1f4..a000f8ece143 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -16,7 +16,7 @@ use crate::machinst::lower::*; use crate::machinst::*; use crate::result::CodegenResult; use crate::settings::Flags; -use std::boxed::Box; +use alloc::boxed::Box; use target_lexicon::Triple; /// Identifier for a particular input of an instruction. diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 073284605ef7..57bfa06ee7fd 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -22,10 +22,10 @@ use crate::machinst::{ ArgPair, CallArgList, CallInfo, CallRetList, InstOutput, MachInst, VCodeConstant, VCodeConstantData, }; +use alloc::boxed::Box; use alloc::vec::Vec; use cranelift_assembler_x64 as asm; use regalloc2::PReg; -use std::boxed::Box; /// Type representing out-of-line data for calls. This type optional because the /// call instruction is also used by Winch to emit calls, but the diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 0edaf5ccb79c..37a386504347 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -16,10 +16,10 @@ use crate::machinst::{ use crate::result::{CodegenError, CodegenResult}; use crate::settings::{self as shared_settings, Flags}; use crate::{Final, MachBufferFinalized}; +use alloc::string::String; use alloc::{borrow::ToOwned, boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use std::string::String; use target_lexicon::Triple; mod abi; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index 6a9a57db40bf..a2b58b15431d 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -130,7 +130,7 @@ macro_rules! isle_common_prelude_methods { #[inline] fn i64_sextend_u64(&mut self, ty: Type, x: u64) -> i64 { - let shift_amt = std::cmp::max(0, 64 - ty.bits()); + let shift_amt = core::cmp::max(0, 64 - ty.bits()); ((x as i64) << shift_amt) >> shift_amt } @@ -167,7 +167,7 @@ macro_rules! isle_common_prelude_methods { #[inline] fn ty_bits(&mut self, ty: Type) -> u8 { - use std::convert::TryInto; + use core::convert::TryInto; ty.bits().try_into().unwrap() } diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index d829302fbd81..45444d161934 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -50,7 +50,7 @@ fn const_vector_scale( assert!(ty.bytes() <= 16); // Use a minimum of 128-bits for the base type. - let base_bytes = std::cmp::max(ty.bytes(), 16); + let base_bytes = core::cmp::max(ty.bytes(), 16); let scale = (isa.dynamic_vector_bytes(ty) / base_bytes) as i64; assert!(scale > 0); let pos = FuncCursor::new(func).at_inst(inst); diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index b9ac3a7c6a38..5d88c519af5a 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -62,13 +62,13 @@ impl LoopLevel { /// A clamped loop level from a larger-width (usize) depth. pub fn clamped(level: usize) -> Self { Self( - u8::try_from(std::cmp::min(level, (Self::INVALID as usize) - 1)) + u8::try_from(core::cmp::min(level, (Self::INVALID as usize) - 1)) .expect("Clamped value must always convert"), ) } } -impl std::default::Default for LoopLevel { +impl core::default::Default for LoopLevel { fn default() -> Self { LoopLevel::invalid() } diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index e8949062f457..6b8baee92330 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -107,11 +107,11 @@ use crate::settings::ProbestackStrategy; use crate::{ir, isa}; use crate::{machinst::*, trace}; use alloc::boxed::Box; +use core::marker::PhantomData; +use hashbrown::HashMap; use regalloc2::{MachineEnv, PReg, PRegSet}; use rustc_hash::FxHashMap; use smallvec::smallvec; -use std::collections::HashMap; -use std::marker::PhantomData; /// A small vector of instructions (with some reasonable size); appropriate for /// a small fixed sequence implementing one operation. @@ -1022,7 +1022,7 @@ impl SigSet { // NB: we do _not_ implement `IndexMut` because these signatures are // deduplicated and shared! -impl std::ops::Index for SigSet { +impl core::ops::Index for SigSet { type Output = SigData; fn index(&self, sig: Sig) -> &Self::Output { @@ -1244,7 +1244,7 @@ impl Callee { // We always at least machine-word-align slots, but also // satisfy the user's requested alignment. debug_assert!(data.align_shift < 32); - let align = std::cmp::max(M::word_bytes(), 1u32 << data.align_shift); + let align = core::cmp::max(M::word_bytes(), 1u32 << data.align_shift); let mask = align - 1; let start_offset = checked_round_up(unaligned_start_offset, mask) .ok_or(CodegenError::ImplLimitExceeded)?; @@ -2183,7 +2183,7 @@ impl Callee { // establishes live-ranges for in-register arguments and // constrains them at the start of the function to the // locations defined by the ABI. - Some(M::gen_args(std::mem::take(&mut self.reg_args))) + Some(M::gen_args(core::mem::take(&mut self.reg_args))) } else { None } @@ -2612,6 +2612,6 @@ mod tests { fn sig_data_size() { // The size of `SigData` is performance sensitive, so make sure // we don't regress it unintentionally. - assert_eq!(std::mem::size_of::(), 24); + assert_eq!(core::mem::size_of::(), 24); } } diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index e41f1fa4f14c..9e48e2c4d607 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -78,7 +78,7 @@ pub struct BlockLoweringOrder { lowered_succ_indices: Vec, /// Ranges in `lowered_succ_indices` giving the successor lists for each lowered /// block. Indexed by lowering-order index (`BlockIndex`). - lowered_succ_ranges: Vec<(Option, std::ops::Range)>, + lowered_succ_ranges: Vec<(Option, core::ops::Range)>, /// BlockIndex for each original Block. blockindex_by_block: SecondaryMap, /// Cold blocks. These blocks are not reordered in the diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index f386e2af50b5..a9e4a8878020 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -184,11 +184,11 @@ use core::ops::Range; use cranelift_control::ControlPlane; use cranelift_entity::{PrimaryMap, SecondaryMap, entity_impl}; use smallvec::SmallVec; -use std::cmp::Ordering; -use std::collections::BinaryHeap; -use std::mem; -use std::string::String; -use std::vec::Vec; +use core::cmp::Ordering; +use alloc::collections::BinaryHeap; +use core::mem; +use alloc::string::String; +use alloc::vec::Vec; #[cfg(feature = "enable-serde")] use serde::{Deserialize, Serialize}; @@ -1820,7 +1820,7 @@ impl MachBufferFinalized { /// Return the code in this mach buffer as a hex string for testing purposes. pub fn stringify_code_bytes(&self) -> String { // This is pretty lame, but whatever .. - use std::fmt::Write; + use core::fmt::Write; let mut s = String::with_capacity(self.data.len() * 2); for b in &self.data { write!(&mut s, "{b:02X}").unwrap(); diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 411af0cdc7f9..01f397c8c67f 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -1,7 +1,7 @@ //! Miscellaneous helpers for machine backends. use crate::ir::Type; -use std::ops::{Add, BitAnd, Not, Sub}; +use core::ops::{Add, BitAnd, Not, Sub}; /// Returns the size (in bits) of a given type. pub fn ty_bits(ty: Type) -> usize { diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index ee8b29ceafcb..f73ede5b257b 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -218,7 +218,7 @@ macro_rules! isle_lower_prelude_methods { _ => return None, }; let ty = self.lower_ctx.output_ty(inst, 0); - let shift_amt = std::cmp::max(0, 64 - self.ty_bits(ty)); + let shift_amt = core::cmp::max(0, 64 - self.ty_bits(ty)); Some((constant << shift_amt) >> shift_amt) } @@ -760,7 +760,7 @@ macro_rules! isle_lower_prelude_methods { &mut self, targets: &MachLabelSlice, ) -> Option<(MachLabel, BoxVecMachLabel)> { - use std::boxed::Box; + use alloc::boxed::Box; if targets.is_empty() { return None; } diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index e94d26186093..2d864e04b7c1 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -26,7 +26,7 @@ use alloc::vec::Vec; use cranelift_control::ControlPlane; use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; -use std::fmt::Debug; +use core::fmt::Debug; use super::{VCodeBuildDirection, VRegAllocator}; @@ -38,7 +38,7 @@ pub type InstOutput = SmallVec<[ValueRegs; 2]>; /// any side-effecting op (for this purpose, loads are also considered /// side-effecting, to avoid subtle questions w.r.t. the memory model), and /// furthermore, it is guaranteed that for any two instructions A and B such -/// that color(A) == color(B), either A dominates B and B postdominates A, or +/// that color(A) == color(B), either A dominates B and B pocoreominates A, or /// vice-versa. (For now, in practice, only ops in the same basic block can ever /// have the same color, trivially providing the second condition.) Intuitively, /// this means that the ops of the same color must always execute "together", as @@ -1389,7 +1389,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { /// Instruction input/output queries. impl<'func, I: VCodeInst> Lower<'func, I> { - /// Get the instdata for a given IR instruction. + /// Get the incoreata for a given IR instruction. pub fn data(&self, ir_inst: Inst) -> &InstructionData { &self.f.dfg.insts[ir_inst] } diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index f534ddb87a28..4c014f5dd0f2 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -59,7 +59,7 @@ use cranelift_control::ControlPlane; use cranelift_entity::PrimaryMap; use regalloc2::VReg; use smallvec::{SmallVec, smallvec}; -use std::string::String; +use alloc::string::String; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; @@ -444,7 +444,7 @@ impl CompiledCodeBase { params: Option<&crate::ir::function::FunctionParameters>, cs: &capstone::Capstone, ) -> Result { - use std::fmt::Write; + use core::fmt::Write; let mut buf = String::new(); diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index f60afcf7d077..dd28ee05f4c8 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -111,8 +111,8 @@ impl Reg { } } -impl std::fmt::Debug for Reg { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::Debug for Reg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { if VReg::from(self.0) == VReg::invalid() { write!(f, "") } else if let Some(spillslot) = self.to_spillslot() { @@ -153,8 +153,8 @@ impl RealReg { } } -impl std::fmt::Debug for RealReg { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::Debug for RealReg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { Reg::from(*self).fmt(f) } } @@ -179,8 +179,8 @@ impl VirtualReg { } } -impl std::fmt::Debug for VirtualReg { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::Debug for VirtualReg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { Reg::from(*self).fmt(f) } } @@ -243,20 +243,20 @@ impl cranelift_assembler_x64::AsReg for Writa // Conversions between regalloc2 types (VReg, PReg) and our types // (VirtualReg, RealReg, Reg). -impl std::convert::From for Reg { +impl core::convert::From for Reg { fn from(vreg: regalloc2::VReg) -> Reg { Reg(vreg.bits() as u32) } } -impl std::convert::From for VirtualReg { +impl core::convert::From for VirtualReg { fn from(vreg: regalloc2::VReg) -> VirtualReg { debug_assert!(pinned_vreg_to_preg(vreg).is_none()); VirtualReg(vreg) } } -impl std::convert::From for regalloc2::VReg { +impl core::convert::From for regalloc2::VReg { /// Extract the underlying `regalloc2::VReg`. Note that physical /// registers also map to particular (special) VRegs, so this /// method can be used either on virtual or physical `Reg`s. @@ -264,19 +264,19 @@ impl std::convert::From for regalloc2::VReg { reg.0.into() } } -impl std::convert::From<&Reg> for regalloc2::VReg { +impl core::convert::From<&Reg> for regalloc2::VReg { fn from(reg: &Reg) -> regalloc2::VReg { reg.0.into() } } -impl std::convert::From for regalloc2::VReg { +impl core::convert::From for regalloc2::VReg { fn from(reg: VirtualReg) -> regalloc2::VReg { reg.0 } } -impl std::convert::From for regalloc2::VReg { +impl core::convert::From for regalloc2::VReg { fn from(reg: RealReg) -> regalloc2::VReg { // This representation is redundant: the class is implied in the vreg // index as well as being in the vreg class field. @@ -284,31 +284,31 @@ impl std::convert::From for regalloc2::VReg { } } -impl std::convert::From for regalloc2::PReg { +impl core::convert::From for regalloc2::PReg { fn from(reg: RealReg) -> regalloc2::PReg { reg.0 } } -impl std::convert::From for RealReg { +impl core::convert::From for RealReg { fn from(preg: regalloc2::PReg) -> RealReg { RealReg(preg) } } -impl std::convert::From for Reg { +impl core::convert::From for Reg { fn from(preg: regalloc2::PReg) -> Reg { RealReg(preg).into() } } -impl std::convert::From for Reg { +impl core::convert::From for Reg { fn from(reg: RealReg) -> Reg { Reg(VReg::from(reg).bits() as u32) } } -impl std::convert::From for Reg { +impl core::convert::From for Reg { fn from(reg: VirtualReg) -> Reg { Reg(reg.0.bits() as u32) } @@ -317,7 +317,7 @@ impl std::convert::From for Reg { /// A spill slot. pub type SpillSlot = regalloc2::SpillSlot; -impl std::convert::From for Reg { +impl core::convert::From for Reg { fn from(spillslot: regalloc2::SpillSlot) -> Reg { Reg(REG_SPILLSLOT_BIT | spillslot.index() as u32) } diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index 53eacea5d067..8a684d868f86 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -4,7 +4,7 @@ use regalloc2::{PReg, VReg}; use super::{RealReg, Reg, VirtualReg, Writable}; -use std::fmt::Debug; +use core::fmt::Debug; const VALUE_REGS_PARTS: usize = 2; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 9bb44e43d50f..22c855584c09 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -31,13 +31,14 @@ use regalloc2::{ }; use rustc_hash::FxHashMap; +use crate::HashMap; +use crate::hash_map::Entry; + use core::cmp::Ordering; use core::fmt::{self, Write}; use core::mem::take; use core::ops::Range; use cranelift_entity::{Keys, entity_impl}; -use std::collections::HashMap; -use std::collections::hash_map::Entry; /// Index referring to an instruction in VCode. pub type InsnIndex = regalloc2::Inst; @@ -808,7 +809,7 @@ impl VCode { let mut cur_srcloc = None; let mut last_offset = None; let mut inst_offsets = vec![]; - let mut state = I::State::new(&self.abi, std::mem::take(ctrl_plane)); + let mut state = I::State::new(&self.abi, core::mem::take(ctrl_plane)); let mut disasm = String::new(); @@ -1552,7 +1553,7 @@ impl VCode { } } -impl std::ops::Index for VCode { +impl core::ops::Index for VCode { type Output = I; fn index(&self, idx: InsnIndex) -> &Self::Output { &self.insts[idx.index()] @@ -2040,7 +2041,7 @@ impl VCodeConstantData { #[cfg(test)] mod test { use super::*; - use std::mem::size_of; + use core::mem::size_of; #[test] fn size_of_constant_structs() { diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index b7a05cf4fea8..3c9dd6693edf 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -17,7 +17,7 @@ use crate::machinst::isle::*; use crate::trace; use cranelift_entity::packed_option::ReservedValue; use smallvec::{SmallVec, smallvec}; -use std::marker::PhantomData; +use core::marker::PhantomData; pub type Unit = (); pub type ValueArray2 = [Value; 2]; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index ccaa3973f875..ae9f3ad6ed24 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -227,7 +227,7 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) // info. The solver will iterate over the summaries, rather than having // to inspect each instruction in each block. let bump = - Bump::with_capacity(domtree.cfg_postorder().len() * 4 * std::mem::size_of::()); + Bump::with_capacity(domtree.cfg_postorder().len() * 4 * core::mem::size_of::()); let mut summaries = SecondaryMap::::with_capacity(domtree.cfg_postorder().len()); diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index 5e4a490073c7..c62572cd9958 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -4,7 +4,7 @@ use regalloc2::checker::CheckerErrors; use crate::ir::pcc::PccError; use crate::{ir::Function, verifier::VerifierErrors}; -use std::string::String; +use alloc::string::String; /// A compilation error. /// @@ -52,8 +52,8 @@ pub type CodegenResult = Result; // This is manually implementing Error and Display instead of using thiserror to reduce the amount // of dependencies used by Cranelift. -impl std::error::Error for CodegenError { - fn source(&self) -> Option<&(dyn std::error::Error + 'static)> { +impl core::error::Error for CodegenError { + fn source(&self) -> Option<&(dyn core::error::Error + 'static)> { match self { CodegenError::Verifier(source) => Some(source), CodegenError::ImplLimitExceeded { .. } @@ -67,8 +67,8 @@ impl std::error::Error for CodegenError { } } -impl std::fmt::Display for CodegenError { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::Display for CodegenError { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self { CodegenError::Verifier(_) => write!(f, "Verifier errors"), CodegenError::ImplLimitExceeded => write!(f, "Implementation limit exceeded"), diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index af8cbd51402c..158ba139bd42 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -290,7 +290,7 @@ pub enum SetError { BadValue(String), } -impl std::error::Error for SetError {} +impl core::error::Error for SetError {} impl fmt::Display for SetError { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index 78b8c71e827c..584d9239d0fa 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -64,7 +64,7 @@ where U: Default, { fn drop(&mut self) { - *(self.proj)(self.container) = std::mem::take(&mut self.value); + *(self.proj)(self.container) = core::mem::take(&mut self.value); } } @@ -76,7 +76,7 @@ where /// Create a new `TakeAndReplace` that temporarily takes out /// `proj(container)`. pub fn new(mut container: &'a mut T, proj: F) -> Self { - let value = std::mem::take(proj(&mut container)); + let value = core::mem::take(proj(&mut container)); TakeAndReplace { container, value, diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index a61dd21f7956..a06c6001ef41 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -118,12 +118,12 @@ pub use enabled::*; #[cfg(feature = "timing")] mod enabled { use super::{DESCRIPTIONS, DefaultProfiler, NUM_PASSES, Pass, Profiler}; - use std::any::Any; - use std::boxed::Box; - use std::cell::{Cell, RefCell}; - use std::fmt; - use std::mem; - use std::time::Duration; + use alloc::boxed::Box; + use core::any::Any; + use core::cell::{Cell, RefCell}; + use core::fmt; + use core::mem; + use core::time::Duration; use std::time::Instant; // Information about passes in a single thread. @@ -135,7 +135,7 @@ mod enabled { /// /// Returns the old profiler. pub fn set_thread_profiler(new_profiler: Box) -> Box { - PROFILER.with(|profiler| std::mem::replace(&mut *profiler.borrow_mut(), new_profiler)) + PROFILER.with(|profiler| core::mem::replace(&mut *profiler.borrow_mut(), new_profiler)) } /// Start timing `pass` as a child of the currently running pass, if any. diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 8406820d6ac0..304c3ebb202f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -99,7 +99,7 @@ pub struct VerifierError { // This is manually implementing Error and Display instead of using thiserror to reduce the amount // of dependencies used by Cranelift. -impl std::error::Error for VerifierError {} +impl core::error::Error for VerifierError {} impl Display for VerifierError { fn fmt(&self, f: &mut Formatter) -> fmt::Result { @@ -178,7 +178,7 @@ pub struct VerifierErrors(pub Vec); // This is manually implementing Error and Display instead of using thiserror to reduce the amount // of dependencies used by Cranelift. -impl std::error::Error for VerifierErrors {} +impl core::error::Error for VerifierErrors {} impl VerifierErrors { /// Return a new `VerifierErrors` struct. @@ -2130,9 +2130,9 @@ mod tests { None => panic!("Expected an error"), Some(&VerifierError { ref message, .. }) => { if !message.contains($msg) { - #[cfg(feature = "std")] + #[cfg(feature = "core")] panic!("'{}' did not contain the substring '{}'", message, $msg); - #[cfg(not(feature = "std"))] + #[cfg(not(feature = "core"))] panic!("error message did not contain the expected substring"); } } From 5301ec9654b639945111e3913e34e3316ff3e28e Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 17:58:06 +0100 Subject: [PATCH 02/61] Port assembler_x64 to no_std --- cranelift/assembler-x64/Cargo.toml | 1 + .../assembler-x64/meta/src/dsl/format.rs | 6 +++--- cranelift/assembler-x64/meta/src/generate.rs | 6 +++--- .../assembler-x64/meta/src/generate/inst.rs | 8 ++++---- cranelift/assembler-x64/src/api.rs | 9 +++++---- cranelift/assembler-x64/src/custom.rs | 5 +++-- cranelift/assembler-x64/src/features.rs | 2 +- cranelift/assembler-x64/src/fixed.rs | 1 + cranelift/assembler-x64/src/fuzz.rs | 6 +++--- cranelift/assembler-x64/src/gpr.rs | 1 + cranelift/assembler-x64/src/imm.rs | 13 ++++++++----- cranelift/assembler-x64/src/inst.rs | 3 +++ cranelift/assembler-x64/src/lib.rs | 2 ++ cranelift/assembler-x64/src/main.rs | 11 +++++++++++ cranelift/assembler-x64/src/mem.rs | 19 +++++++++++-------- cranelift/assembler-x64/src/xmm.rs | 4 ++++ 16 files changed, 64 insertions(+), 33 deletions(-) diff --git a/cranelift/assembler-x64/Cargo.toml b/cranelift/assembler-x64/Cargo.toml index 6935ec669950..424d26f206ce 100644 --- a/cranelift/assembler-x64/Cargo.toml +++ b/cranelift/assembler-x64/Cargo.toml @@ -23,3 +23,4 @@ workspace = true [features] fuzz = ['dep:arbitrary', 'dep:capstone'] +core = [] diff --git a/cranelift/assembler-x64/meta/src/dsl/format.rs b/cranelift/assembler-x64/meta/src/dsl/format.rs index fe39d1892db3..cb6b8e5a9645 100644 --- a/cranelift/assembler-x64/meta/src/dsl/format.rs +++ b/cranelift/assembler-x64/meta/src/dsl/format.rs @@ -535,7 +535,7 @@ impl Default for Mutability { } impl core::fmt::Display for Mutability { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { match self { Self::Read => write!(f, "r"), Self::ReadWrite => write!(f, "rw"), @@ -576,7 +576,7 @@ impl Default for Extension { } impl core::fmt::Display for Extension { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { match self { Extension::None => write!(f, ""), Extension::SignExtendQuad => write!(f, "sxq"), @@ -627,7 +627,7 @@ impl Default for Eflags { } impl core::fmt::Display for Eflags { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { match self { Self::None => write!(f, ""), Self::R => write!(f, "r"), diff --git a/cranelift/assembler-x64/meta/src/generate.rs b/cranelift/assembler-x64/meta/src/generate.rs index b4b13e19d33e..4191a53d6833 100644 --- a/cranelift/assembler-x64/meta/src/generate.rs +++ b/cranelift/assembler-x64/meta/src/generate.rs @@ -53,11 +53,11 @@ fn match_variants(f: &mut Formatter, insts: &[dsl::Inst], invoke: &str) { }); } -/// `impl std::fmt::Display for Inst { ... }` +/// `impl core::fmt::Display for Inst { ... }` fn generate_inst_display_impl(f: &mut Formatter, insts: &[dsl::Inst]) { - f.add_block("impl std::fmt::Display for Inst", |f| { + f.add_block("impl core::fmt::Display for Inst", |f| { f.add_block( - "fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result", + "fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result", |f| { match_variants(f, insts, "fmt(f)"); }, diff --git a/cranelift/assembler-x64/meta/src/generate/inst.rs b/cranelift/assembler-x64/meta/src/generate/inst.rs index 0991b4134be8..6d5e8b8862fe 100644 --- a/cranelift/assembler-x64/meta/src/generate/inst.rs +++ b/cranelift/assembler-x64/meta/src/generate/inst.rs @@ -107,12 +107,12 @@ impl dsl::Inst { fmtln!(f, "#[must_use]"); fmtln!(f, "#[inline]"); f.add_block( - &format!("pub fn mnemonic(&self) -> std::borrow::Cow<'static, str>"), + &format!("pub fn mnemonic(&self) -> alloc::borrow::Cow<'static, str>"), |f| { if self.custom.contains(Mnemonic) { fmtln!(f, "crate::custom::mnemonic::{}(self)", self.name()); } else { - fmtln!(f, "std::borrow::Cow::Borrowed(\"{}\")", self.mnemonic); + fmtln!(f, "alloc::borrow::Cow::Borrowed(\"{}\")", self.mnemonic); } }, ); @@ -265,10 +265,10 @@ impl dsl::Inst { let impl_block = self.generate_impl_block_start(); let struct_name = self.struct_name_with_generic(); f.add_block( - &format!("{impl_block} std::fmt::Display for {struct_name}"), + &format!("{impl_block} core::fmt::Display for {struct_name}"), |f| { f.add_block( - "fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result", + "fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result", |f| { if self.custom.contains(Display) { fmtln!(f, "crate::custom::display::{}(f, self)", self.name()); diff --git a/cranelift/assembler-x64/src/api.rs b/cranelift/assembler-x64/src/api.rs index c27101985b2c..f65cfc338045 100644 --- a/cranelift/assembler-x64/src/api.rs +++ b/cranelift/assembler-x64/src/api.rs @@ -3,9 +3,10 @@ use crate::gpr; use crate::xmm; use crate::{Amode, DeferredTarget, GprMem, XmmMem}; -use std::fmt; -use std::{num::NonZeroU8, vec::Vec}; - +use alloc::vec::Vec; +use core::fmt; +use core::num::NonZeroU8; +use alloc::string::String; /// Describe how an instruction is emitted into a code buffer. pub trait CodeSink { /// Add 1 byte to the code section. @@ -113,7 +114,7 @@ pub trait Registers { } /// Describe how to interact with an external register type. -pub trait AsReg: Copy + Clone + std::fmt::Debug + PartialEq { +pub trait AsReg: Copy + Clone + core::fmt::Debug + PartialEq { /// Create a register from its hardware encoding. /// /// This is primarily useful for fuzzing, though it is also useful for diff --git a/cranelift/assembler-x64/src/custom.rs b/cranelift/assembler-x64/src/custom.rs index adbfd2c6acc9..c2b70fecbc24 100644 --- a/cranelift/assembler-x64/src/custom.rs +++ b/cranelift/assembler-x64/src/custom.rs @@ -75,7 +75,7 @@ pub mod encode { pub mod mnemonic { use crate::inst; use crate::{Registers, XmmMem}; - use std::borrow::Cow; + use alloc::borrow::Cow; macro_rules! lock { ($name:tt => $mnemonic:expr) => { @@ -191,7 +191,8 @@ pub mod mnemonic { pub mod display { use crate::inst; use crate::{Amode, Gpr, GprMem, Registers, Size}; - use std::fmt; + use core::fmt; + use alloc::string::ToString; pub fn callq_d(f: &mut fmt::Formatter, inst: &inst::callq_d) -> fmt::Result { let inst::callq_d { imm32 } = inst; diff --git a/cranelift/assembler-x64/src/features.rs b/cranelift/assembler-x64/src/features.rs index 3559b9755662..77864e74db92 100644 --- a/cranelift/assembler-x64/src/features.rs +++ b/cranelift/assembler-x64/src/features.rs @@ -32,7 +32,7 @@ //! [`Inst::features`]: crate::inst::Inst::features use crate::inst::for_each_feature; -use std::fmt; +use core::fmt; // Helpfully generate `enum Feature`. macro_rules! create_feature_enum { diff --git a/cranelift/assembler-x64/src/fixed.rs b/cranelift/assembler-x64/src/fixed.rs index d689874c9a5a..c17ca3b944ef 100644 --- a/cranelift/assembler-x64/src/fixed.rs +++ b/cranelift/assembler-x64/src/fixed.rs @@ -1,6 +1,7 @@ //! Operands with fixed register encodings. use crate::{AsReg, Size}; +use alloc::string::String; /// A _fixed_ register. /// diff --git a/cranelift/assembler-x64/src/fuzz.rs b/cranelift/assembler-x64/src/fuzz.rs index 250e08a43e57..9bbcaf83509f 100644 --- a/cranelift/assembler-x64/src/fuzz.rs +++ b/cranelift/assembler-x64/src/fuzz.rs @@ -146,7 +146,7 @@ fn disassemble(assembled: &[u8], original: &Inst) -> String { } fn pretty_print_hexadecimal(hex: &[u8]) -> String { - use std::fmt::Write; + use core::fmt::Write; let mut s = String::with_capacity(hex.len() * 2); for b in hex { write!(&mut s, "{b:02X}").unwrap(); @@ -183,7 +183,7 @@ macro_rules! hex_print_signed_imm { /// - print negative values as `-0x...` (signed hex) instead of `0xff...` /// (normal hex) /// - print `mov` immediates as base-10 instead of base-16 (?!). -fn replace_signed_immediates(dis: &str) -> std::borrow::Cow<'_, str> { +fn replace_signed_immediates(dis: &str) -> alloc::borrow::Cow<'_, str> { match dis.find('$') { None => dis.into(), Some(idx) => { @@ -259,7 +259,7 @@ fn remove_after_parenthesis_test() { } /// Run some post-processing on the disassembly to make it match Capstone. -fn fix_up(dis: &str) -> std::borrow::Cow<'_, str> { +fn fix_up(dis: &str) -> alloc::borrow::Cow<'_, str> { let dis = remove_after_semicolon(dis); replace_signed_immediates(&dis) } diff --git a/cranelift/assembler-x64/src/gpr.rs b/cranelift/assembler-x64/src/gpr.rs index 4013c60686de..5489b513ce29 100644 --- a/cranelift/assembler-x64/src/gpr.rs +++ b/cranelift/assembler-x64/src/gpr.rs @@ -1,6 +1,7 @@ //! Pure register operands; see [`Gpr`]. use crate::AsReg; +use alloc::string::String; /// A general purpose x64 register (e.g., `%rax`). /// diff --git a/cranelift/assembler-x64/src/imm.rs b/cranelift/assembler-x64/src/imm.rs index eeb5a27d4d0d..0c129cd65d45 100644 --- a/cranelift/assembler-x64/src/imm.rs +++ b/cranelift/assembler-x64/src/imm.rs @@ -1,7 +1,10 @@ //! Immediate operands to instructions. use crate::api::CodeSink; -use std::fmt; +use core::fmt; + +#[cfg(feature = "core")] +use alloc::{format, string::String}; /// This helper function prints the unsigned hexadecimal representation of the /// immediate value: e.g., this prints `$0xfe` to represent both the signed `-2` @@ -49,7 +52,7 @@ impl From for Imm8 { } impl TryFrom for Imm8 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(u8::try_from(simm32)?)) } @@ -100,7 +103,7 @@ impl From for Simm8 { } impl TryFrom for Simm8 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(i8::try_from(simm32)?)) } @@ -134,7 +137,7 @@ impl From for Imm16 { } impl TryFrom for Imm16 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(u16::try_from(simm32)?)) } @@ -185,7 +188,7 @@ impl From for Simm16 { } impl TryFrom for Simm16 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(i16::try_from(simm32)?)) } diff --git a/cranelift/assembler-x64/src/inst.rs b/cranelift/assembler-x64/src/inst.rs index 173336a7372d..e4f23849cd12 100644 --- a/cranelift/assembler-x64/src/inst.rs +++ b/cranelift/assembler-x64/src/inst.rs @@ -14,6 +14,9 @@ use crate::rex::RexPrefix; use crate::vex::VexPrefix; use crate::xmm::{self, Xmm}; +use alloc::string::ToString; + + // Include code generated by the `meta` crate. include!(concat!(env!("OUT_DIR"), "/assembler.rs")); diff --git a/cranelift/assembler-x64/src/lib.rs b/cranelift/assembler-x64/src/lib.rs index 7b5b6db7fc3a..d28e102ffeb7 100644 --- a/cranelift/assembler-x64/src/lib.rs +++ b/cranelift/assembler-x64/src/lib.rs @@ -41,6 +41,8 @@ non_camel_case_types, reason = "all of the generated struct names use snake case" )] +#![cfg_attr(feature = "core", no_std)] +extern crate alloc; mod api; mod custom; diff --git a/cranelift/assembler-x64/src/main.rs b/cranelift/assembler-x64/src/main.rs index c50a80fea5b9..4361d85624f9 100644 --- a/cranelift/assembler-x64/src/main.rs +++ b/cranelift/assembler-x64/src/main.rs @@ -1,8 +1,19 @@ //! Print the path to the generated code. +#![cfg_attr(feature = "core", no_std)] +#[cfg(not(feature = "core"))] fn main() { let paths: Vec = include!(concat!(env!("OUT_DIR"), "/generated-files.rs")); for path in paths { println!("{}", path.display()); } } + +#[cfg(feature = "core")] +fn main() {} + +#[cfg(feature = "core")] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} \ No newline at end of file diff --git a/cranelift/assembler-x64/src/mem.rs b/cranelift/assembler-x64/src/mem.rs index 19cf06707e54..cffecf9bf18b 100644 --- a/cranelift/assembler-x64/src/mem.rs +++ b/cranelift/assembler-x64/src/mem.rs @@ -4,6 +4,9 @@ use crate::api::{AsReg, CodeSink, Constant, KnownOffset, Label, TrapCode}; use crate::gpr::{self, NonRspGpr, Size}; use crate::rex::{Disp, RexPrefix, encode_modrm, encode_sib}; +#[cfg(feature = "core")] +use alloc::string::{String, ToString}; + /// x64 memory addressing modes. #[derive(Copy, Clone, Debug, PartialEq)] #[cfg_attr(any(test, feature = "fuzz"), derive(arbitrary::Arbitrary))] @@ -99,8 +102,8 @@ impl From for AmodeOffset { } } -impl std::fmt::LowerHex for AmodeOffset { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::LowerHex for AmodeOffset { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { // This rather complex implementation is necessary to match how // `capstone` pretty-prints memory immediates. if self.0 == 0 { @@ -116,7 +119,7 @@ impl std::fmt::LowerHex for AmodeOffset { Some(i) => i, None => -2_147_483_648, }; - std::fmt::LowerHex::fmt(&abs, f) + core::fmt::LowerHex::fmt(&abs, f) } } @@ -154,12 +157,12 @@ impl AmodeOffsetPlusKnownOffset { } } -impl std::fmt::LowerHex for AmodeOffsetPlusKnownOffset { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::LowerHex for AmodeOffsetPlusKnownOffset { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { if let Some(offset) = self.offset { write!(f, "+")?; } - std::fmt::LowerHex::fmt(&self.simm32, f) + core::fmt::LowerHex::fmt(&self.simm32, f) } } @@ -172,8 +175,8 @@ pub enum DeferredTarget { None, } -impl std::fmt::Display for Amode { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { +impl core::fmt::Display for Amode { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { let pointer_width = Size::Quadword; match self { Amode::ImmReg { simm32, base, .. } => { diff --git a/cranelift/assembler-x64/src/xmm.rs b/cranelift/assembler-x64/src/xmm.rs index 9b2a00a9d489..636c887afbc7 100644 --- a/cranelift/assembler-x64/src/xmm.rs +++ b/cranelift/assembler-x64/src/xmm.rs @@ -2,6 +2,10 @@ use crate::{AsReg, CodeSink, rex::encode_modrm}; +#[cfg(feature = "core")] +use alloc::string::String; +//use core::convert::{AsMut, AsRef, From}; + /// An x64 SSE register (e.g., `%xmm0`). #[derive(Clone, Copy, Debug)] pub struct Xmm(pub(crate) R); From d064db469b1332b7088441cc589bfb6ecbad53f8 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 18:26:16 +0100 Subject: [PATCH 03/61] before adding prelude to each file --- Cargo.toml | 111 +++++++++++++++++++------ cranelift/codegen/Cargo.toml | 4 +- cranelift/codegen/shared/src/lib.rs | 3 +- cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/prelude.rs | 4 + 6 files changed, 94 insertions(+), 30 deletions(-) create mode 100644 cranelift/codegen/src/prelude.rs diff --git a/Cargo.toml b/Cargo.toml index ca68c5e23156..b82c369c620f 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -50,7 +50,10 @@ wasmtime-cranelift = { workspace = true, optional = true } wasmtime-environ = { workspace = true } wasmtime-explorer = { workspace = true, optional = true } wasmtime-wast = { workspace = true, optional = true } -wasi-common = { workspace = true, default-features = true, features = ["exit", "tokio"], optional = true } +wasi-common = { workspace = true, default-features = true, features = [ + "exit", + "tokio", +], optional = true } wasmtime-wasi = { workspace = true, default-features = true, optional = true } wasmtime-wasi-nn = { workspace = true, optional = true } wasmtime-wasi-config = { workspace = true, optional = true } @@ -59,7 +62,10 @@ wasmtime-wasi-keyvalue = { workspace = true, optional = true } wasmtime-wasi-threads = { workspace = true, optional = true } wasmtime-wasi-http = { workspace = true, optional = true } wasmtime-unwinder = { workspace = true } -wasmtime-wizer = { workspace = true, optional = true, features = ['clap', 'wasmtime'] } +wasmtime-wizer = { workspace = true, optional = true, features = [ + 'clap', + 'wasmtime', +] } clap = { workspace = true } clap_complete = { workspace = true, optional = true } anyhow = { workspace = true, features = ['std'] } @@ -84,7 +90,7 @@ smallvec = { workspace = true } async-trait = { workspace = true } bytes = { workspace = true } cfg-if = { workspace = true } -tokio = { workspace = true, optional = true, features = [ "signal", "macros" ] } +tokio = { workspace = true, optional = true, features = ["signal", "macros"] } hyper = { workspace = true, optional = true } http = { workspace = true, optional = true } http-body-util = { workspace = true, optional = true } @@ -95,12 +101,25 @@ rustix = { workspace = true, features = ["mm", "process"] } [dev-dependencies] # depend again on wasmtime to activate its default features for tests -wasmtime = { workspace = true, features = ['default', 'winch', 'pulley', 'all-arch', 'call-hook', 'memory-protection-keys', 'component-model-async'] } +wasmtime = { workspace = true, features = [ + 'default', + 'winch', + 'pulley', + 'all-arch', + 'call-hook', + 'memory-protection-keys', + 'component-model-async', +] } env_logger = { workspace = true } log = { workspace = true } filecheck = { workspace = true } tempfile = { workspace = true } -tokio = { workspace = true, features = ["rt", "time", "macros", "rt-multi-thread"] } +tokio = { workspace = true, features = [ + "rt", + "time", + "macros", + "rt-multi-thread", +] } wast = { workspace = true } criterion = { workspace = true } num_cpus = "1.17.0" @@ -110,7 +129,10 @@ wat = { workspace = true } rayon = "1.5.0" wasmtime-wast = { workspace = true, features = ['component-model'] } wasmtime-component-util = { workspace = true } -wasmtime-test-util = { workspace = true, features = ['wasmtime-wast', 'component'] } +wasmtime-test-util = { workspace = true, features = [ + 'wasmtime-wast', + 'component', +] } bstr = "1.6.0" libc = { workspace = true } serde = { workspace = true } @@ -120,7 +142,11 @@ test-programs-artifacts = { workspace = true } bytesize = "2.0.1" wit-component = { workspace = true } cranelift-filetests = { workspace = true } -cranelift-codegen = { workspace = true, features = ["disas", "trace-log", "timing"] } +cranelift-codegen = { workspace = true, features = [ + "disas", + "trace-log", + "timing", +] } cranelift-reader = { workspace = true } toml = { workspace = true } similar = { workspace = true } @@ -180,9 +206,7 @@ members = [ "fuzz", "winch/codegen", ] -exclude = [ - 'docs/rust_wasi_markdown_parser', -] +exclude = ['docs/rust_wasi_markdown_parser'] [workspace.package] version = "41.0.0" @@ -265,8 +289,8 @@ wasmtime-wmemcheck = { path = "crates/wmemcheck", version = "=41.0.0", package = wasmtime-c-api-macros = { path = "crates/c-api-macros", version = "=41.0.0", package = 'wasmtime-internal-c-api-macros' } wasmtime-cache = { path = "crates/cache", version = "=41.0.0", package = 'wasmtime-internal-cache' } wasmtime-cranelift = { path = "crates/cranelift", version = "=41.0.0", package = 'wasmtime-internal-cranelift' } -wasmtime-winch = { path = "crates/winch", version = "=41.0.0", package = 'wasmtime-internal-winch' } -wasmtime-explorer = { path = "crates/explorer", version = "=41.0.0", package = 'wasmtime-internal-explorer' } +wasmtime-winch = { path = "crates/winch", version = "=41.0.0", package = 'wasmtime-internal-winch' } +wasmtime-explorer = { path = "crates/explorer", version = "=41.0.0", package = 'wasmtime-internal-explorer' } wasmtime-fiber = { path = "crates/fiber", version = "=41.0.0", package = 'wasmtime-internal-fiber' } wasmtime-jit-debug = { path = "crates/jit-debug", version = "=41.0.0", package = 'wasmtime-internal-jit-debug' } wasmtime-component-util = { path = "crates/component-util", version = "=41.0.0", package = 'wasmtime-internal-component-util' } @@ -275,7 +299,7 @@ wasmtime-versioned-export-macros = { path = "crates/versioned-export-macros", ve wasmtime-slab = { path = "crates/slab", version = "=41.0.0", package = 'wasmtime-internal-slab' } wasmtime-jit-icache-coherence = { path = "crates/jit-icache-coherence", version = "=41.0.0", package = 'wasmtime-internal-jit-icache-coherence' } wasmtime-wit-bindgen = { path = "crates/wit-bindgen", version = "=41.0.0", package = 'wasmtime-internal-wit-bindgen' } -wasmtime-math = { path = "crates/math", version = "=41.0.0", package = 'wasmtime-internal-math' } +wasmtime-math = { path = "crates/math", version = "=41.0.0", package = 'wasmtime-internal-math' } wasmtime-unwinder = { path = "crates/unwinder", version = "=41.0.0", package = 'wasmtime-internal-unwinder' } wasmtime-debugger = { path = "crates/debugger", version = "=41.0.0", package = "wasmtime-internal-debugger" } wasmtime-wizer = { path = "crates/wizer", version = "41.0.0" } @@ -291,7 +315,10 @@ pulley-macros = { path = 'pulley/macros', version = "=41.0.0" } # Cranelift crates in this workspace cranelift-assembler-x64 = { path = "cranelift/assembler-x64", version = "0.128.0" } -cranelift-codegen = { path = "cranelift/codegen", version = "0.128.0", default-features = false, features = ["std", "unwind"] } +cranelift-codegen = { path = "cranelift/codegen", version = "0.128.0", default-features = false, features = [ + "std", + "unwind", +] } cranelift-frontend = { path = "cranelift/frontend", version = "0.128.0" } cranelift-entity = { path = "cranelift/entity", version = "0.128.0" } cranelift-native = { path = "cranelift/native", version = "0.128.0" } @@ -304,7 +331,7 @@ cranelift-jit = { path = "cranelift/jit", version = "0.128.0" } cranelift-fuzzgen = { path = "cranelift/fuzzgen" } cranelift-bforest = { path = "cranelift/bforest", version = "0.128.0" } cranelift-bitset = { path = "cranelift/bitset", version = "0.128.0" } -cranelift-control = { path = "cranelift/control", version = "0.128.0" } +cranelift-control = { path = "cranelift/control", version = "0.128.0", default-features = false } cranelift-srcgen = { path = "cranelift/srcgen", version = "0.128.0" } cranelift = { path = "cranelift/umbrella", version = "0.128.0" } @@ -322,7 +349,7 @@ component-async-tests = { path = "crates/misc/component-async-tests" } # Bytecode Alliance maintained dependencies: # --------------------------- -regalloc2 = "0.13.3" +regalloc2 = { version = "0.13.3", default-features = false } wasip1 = { version = "1.0.0", default-features = false } # cap-std family: @@ -343,7 +370,9 @@ wit-bindgen = { version = "0.50.0", default-features = false } wit-bindgen-rust-macro = { version = "0.50.0", default-features = false } # wasm-tools family: -wasmparser = { version = "0.243.0", default-features = false, features = ['simd'] } +wasmparser = { version = "0.243.0", default-features = false, features = [ + 'simd', +] } wat = "1.243.0" wast = "243.0.0" wasmprinter = "0.243.0" @@ -362,14 +391,20 @@ arbitrary = "1.4.2" backtrace = "0.3.75" mutatis = "0.3.2" cc = "1.2.41" -object = { version = "0.37.3", default-features = false, features = ['read_core', 'elf'] } +object = { version = "0.37.3", default-features = false, features = [ + 'read_core', + 'elf', +] } gimli = { version = "0.32.3", default-features = false, features = ['read'] } addr2line = { version = "0.25.1", default-features = false } anyhow = { version = "1.0.100", default-features = false } windows-sys = "0.61.2" env_logger = "0.11.5" log = { version = "0.4.28", default-features = false } -clap = { version = "4.5.48", default-features = false, features = ["std", "derive"] } +clap = { version = "4.5.48", default-features = false, features = [ + "std", + "derive", +] } clap_complete = "4.5.58" hashbrown = { version = "0.15", default-features = false } capstone = "0.13.0" @@ -398,7 +433,7 @@ tempfile = "3.23.0" filecheck = "0.5.0" libc = { version = "0.2.177", default-features = true } file-per-thread-logger = "0.2.0" -tokio = { version = "1.48.0", features = [ "rt", "time" ] } +tokio = { version = "1.48.0", features = ["rt", "time"] } hyper = "1.7.0" http = "1.3.1" http-body = "1.0.1" @@ -409,12 +444,22 @@ indexmap = { version = "2.11.4", default-features = false } syn = "2.0.106" quote = "1.0.41" proc-macro2 = "1.0.101" -test-log = { version = "0.2.18", default-features = false, features = ["trace"] } -tracing-subscriber = { version = "0.3.20", default-features = false, features = ['fmt', 'env-filter', 'ansi', 'tracing-log'] } +test-log = { version = "0.2.18", default-features = false, features = [ + "trace", +] } +tracing-subscriber = { version = "0.3.20", default-features = false, features = [ + 'fmt', + 'env-filter', + 'ansi', + 'tracing-log', +] } url = "2.5.7" postcard = { version = "1.1.3", default-features = false, features = ['alloc'] } -criterion = { version = "0.7.0", default-features = false, features = ["html_reports", "rayon"] } -rustc-hash = "2.1.1" +criterion = { version = "0.7.0", default-features = false, features = [ + "html_reports", + "rayon", +] } +rustc-hash = { version = "2.1.1", default-features = false } libtest-mimic = "0.8.1" semver = { version = "1.0.27", default-features = false } ittapi = "0.4.0" @@ -529,10 +574,19 @@ disable-logging = ["log/max_level_off", "tracing/max_level_off"] wasi-nn = ["dep:wasmtime-wasi-nn"] wasi-tls = ["dep:wasmtime-wasi-tls"] wasi-threads = ["dep:wasmtime-wasi-threads", "threads"] -wasi-http = ["component-model", "dep:wasmtime-wasi-http", "dep:tokio", "dep:hyper", "wasmtime-wasi-http/default-send-request"] +wasi-http = [ + "component-model", + "dep:wasmtime-wasi-http", + "dep:tokio", + "dep:hyper", + "wasmtime-wasi-http/default-send-request", +] wasi-config = ["dep:wasmtime-wasi-config"] wasi-keyvalue = ["dep:wasmtime-wasi-keyvalue"] -pooling-allocator = ["wasmtime/pooling-allocator", "wasmtime-cli-flags/pooling-allocator"] +pooling-allocator = [ + "wasmtime/pooling-allocator", + "wasmtime-cli-flags/pooling-allocator", +] component-model = [ "wasmtime/component-model", "wasmtime-wast?/component-model", @@ -554,7 +608,10 @@ gc = ["wasmtime-cli-flags/gc", "wasmtime/gc"] gc-drc = ["gc", "wasmtime/gc-drc", "wasmtime-cli-flags/gc-drc"] gc-null = ["gc", "wasmtime/gc-null", "wasmtime-cli-flags/gc-null"] pulley = ["wasmtime-cli-flags/pulley"] -stack-switching = ["wasmtime/stack-switching", "wasmtime-cli-flags/stack-switching"] +stack-switching = [ + "wasmtime/stack-switching", + "wasmtime-cli-flags/stack-switching", +] debug = ["wasmtime-cli-flags/debug", "wasmtime/debug"] # CLI subcommands for the `wasmtime` executable. See `wasmtime $cmd --help` diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 32112265eb68..03040f037d3c 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -30,7 +30,7 @@ cranelift-entity = { workspace = true } cranelift-bforest = { workspace = true } cranelift-bitset = { workspace = true } cranelift-control = { workspace = true } -hashbrown = { workspace = true } +hashbrown = { workspace = true, features = ["default-hasher"] } target-lexicon = { workspace = true } log = { workspace = true } serde = { workspace = true, optional = true } @@ -71,7 +71,7 @@ std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # deprecated (we (i) always use hashbrown, and (ii) don't support a # no_std build anymore). The feature remains for backward # compatibility as a no-op. -core = [] +core = ["cranelift-assembler-x64/core"] # Enable the `to_capstone` method on TargetIsa, for constructing a Capstone # context, and the `disassemble` method on `MachBufferFinalized`. diff --git a/cranelift/codegen/shared/src/lib.rs b/cranelift/codegen/shared/src/lib.rs index 2a03a8323439..8aa30263357e 100644 --- a/cranelift/codegen/shared/src/lib.rs +++ b/cranelift/codegen/shared/src/lib.rs @@ -2,9 +2,10 @@ //! `cranelift-codegen-meta` libraries. #![deny(missing_docs)] +#![no_std] pub mod constant_hash; pub mod constants; /// Version number of this crate. -pub const VERSION: &str = env!("CARGO_PKG_VERSION"); +pub const VERSION: &str = core::env!("CARGO_PKG_VERSION"); diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 79b9432960af..051f26ea451c 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1,3 +1,4 @@ + //! Immediate operands for Cranelift instructions //! //! This module defines the types of immediate operands that can appear on Cranelift instructions. diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index ada37b03ccbb..7b842ac7e4ab 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -15,6 +15,7 @@ pub mod winx64; pub mod winarm64; /// CFA-based unwind information used on SystemV. +#[cfg(feature = "unwind")] pub type CfaUnwindInfo = systemv::UnwindInfo; /// Expected unwind info type. diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs new file mode 100644 index 000000000000..b2d13852bc08 --- /dev/null +++ b/cranelift/codegen/src/prelude.rs @@ -0,0 +1,4 @@ +use alloc::format; +use alloc::string::{String, ToString}; +use alloc::vec::Vec; +use alloc::vec; From f9b41c93336b162a54aaae4519c9ba170e76e3a5 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 18:42:45 +0100 Subject: [PATCH 04/61] Most of the files now work with no_std --- cranelift/codegen/src/alias_analysis.rs | 1 + cranelift/codegen/src/binemit/mod.rs | 1 + cranelift/codegen/src/cfg_printer.rs | 1 + cranelift/codegen/src/constant_hash.rs | 1 + cranelift/codegen/src/context.rs | 1 + cranelift/codegen/src/ctxhash.rs | 1 + cranelift/codegen/src/cursor.rs | 1 + cranelift/codegen/src/data_value.rs | 1 + cranelift/codegen/src/dbg.rs | 1 + cranelift/codegen/src/dominator_tree.rs | 1 + cranelift/codegen/src/dominator_tree/simple.rs | 1 + cranelift/codegen/src/egraph.rs | 1 + cranelift/codegen/src/egraph/cost.rs | 1 + cranelift/codegen/src/egraph/elaborate.rs | 1 + cranelift/codegen/src/flowgraph.rs | 1 + cranelift/codegen/src/incremental_cache.rs | 1 + cranelift/codegen/src/inline.rs | 1 + cranelift/codegen/src/inst_predicates.rs | 1 + cranelift/codegen/src/ir/atomic_rmw_op.rs | 1 + cranelift/codegen/src/ir/builder.rs | 1 + cranelift/codegen/src/ir/condcodes.rs | 1 + cranelift/codegen/src/ir/constant.rs | 1 + cranelift/codegen/src/ir/debug_tags.rs | 1 + cranelift/codegen/src/ir/dfg.rs | 1 + cranelift/codegen/src/ir/dynamic_type.rs | 1 + cranelift/codegen/src/ir/entities.rs | 1 + cranelift/codegen/src/ir/exception_table.rs | 1 + cranelift/codegen/src/ir/extfunc.rs | 1 + cranelift/codegen/src/ir/extname.rs | 1 + cranelift/codegen/src/ir/function.rs | 1 + cranelift/codegen/src/ir/globalvalue.rs | 1 + cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/ir/instructions.rs | 1 + cranelift/codegen/src/ir/jumptable.rs | 1 + cranelift/codegen/src/ir/known_symbol.rs | 1 + cranelift/codegen/src/ir/layout.rs | 1 + cranelift/codegen/src/ir/libcall.rs | 1 + cranelift/codegen/src/ir/memflags.rs | 1 + cranelift/codegen/src/ir/memtype.rs | 1 + cranelift/codegen/src/ir/mod.rs | 1 + cranelift/codegen/src/ir/pcc.rs | 1 + cranelift/codegen/src/ir/progpoint.rs | 1 + cranelift/codegen/src/ir/sourceloc.rs | 1 + cranelift/codegen/src/ir/stackslot.rs | 1 + cranelift/codegen/src/ir/trapcode.rs | 1 + cranelift/codegen/src/ir/types.rs | 1 + cranelift/codegen/src/ir/user_stack_maps.rs | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/args.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/emit.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/unwind.rs | 1 + .../codegen/src/isa/aarch64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/aarch64/lower.rs | 1 + cranelift/codegen/src/isa/aarch64/lower/isle.rs | 1 + .../src/isa/aarch64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/pcc.rs | 1 + cranelift/codegen/src/isa/aarch64/settings.rs | 1 + cranelift/codegen/src/isa/call_conv.rs | 1 + cranelift/codegen/src/isa/mod.rs | 1 + cranelift/codegen/src/isa/pulley32.rs | 1 + cranelift/codegen/src/isa/pulley64.rs | 1 + cranelift/codegen/src/isa/pulley_shared/abi.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/args.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/emit.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/regs.rs | 1 + cranelift/codegen/src/isa/pulley_shared/lower.rs | 1 + .../codegen/src/isa/pulley_shared/lower/isle.rs | 1 + .../isa/pulley_shared/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/pulley_shared/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/settings.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/args.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/emit.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/encode.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/imms.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/regs.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/unwind.rs | 1 + .../codegen/src/isa/riscv64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 + cranelift/codegen/src/isa/riscv64/lower.rs | 1 + cranelift/codegen/src/isa/riscv64/lower/isle.rs | 1 + .../src/isa/riscv64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/settings.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 1 + cranelift/codegen/src/isa/s390x/inst/args.rs | 1 + cranelift/codegen/src/isa/s390x/inst/emit.rs | 1 + cranelift/codegen/src/isa/s390x/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 + cranelift/codegen/src/isa/s390x/inst/mod.rs | 1 + cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 + cranelift/codegen/src/isa/s390x/inst/unwind.rs | 1 + .../codegen/src/isa/s390x/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/s390x/lower.rs | 1 + cranelift/codegen/src/isa/s390x/lower/isle.rs | 1 + .../src/isa/s390x/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/s390x/mod.rs | 1 + cranelift/codegen/src/isa/s390x/settings.rs | 1 + cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/isa/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/unwind/winarm64.rs | 1 + cranelift/codegen/src/isa/unwind/winx64.rs | 1 + cranelift/codegen/src/isa/winch.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit_state.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 1 + cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/isa/x64/inst/stack_switch.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs | 1 + cranelift/codegen/src/isa/x64/lower.rs | 1 + cranelift/codegen/src/isa/x64/lower/isle.rs | 1 + .../codegen/src/isa/x64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 1 + cranelift/codegen/src/isa/x64/pcc.rs | 1 + cranelift/codegen/src/isa/x64/settings.rs | 1 + cranelift/codegen/src/isle_prelude.rs | 1 + cranelift/codegen/src/legalizer/branch_to_trap.rs | 1 + cranelift/codegen/src/legalizer/globalvalue.rs | 1 + cranelift/codegen/src/legalizer/mod.rs | 1 + cranelift/codegen/src/lib.rs | 3 +++ cranelift/codegen/src/loop_analysis.rs | 1 + cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/blockorder.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 1 + cranelift/codegen/src/machinst/compile.rs | 1 + cranelift/codegen/src/machinst/helpers.rs | 1 + cranelift/codegen/src/machinst/inst_common.rs | 1 + cranelift/codegen/src/machinst/isle.rs | 1 + cranelift/codegen/src/machinst/lower.rs | 1 + cranelift/codegen/src/machinst/mod.rs | 1 + cranelift/codegen/src/machinst/pcc.rs | 1 + cranelift/codegen/src/machinst/reg.rs | 1 + cranelift/codegen/src/machinst/valueregs.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/nan_canonicalization.rs | 1 + cranelift/codegen/src/opts.rs | 1 + cranelift/codegen/src/opts/div_const.rs | 1 + cranelift/codegen/src/opts/generated_code.rs | 1 + cranelift/codegen/src/prelude.rs | 12 ++++++++---- cranelift/codegen/src/print_errors.rs | 1 + cranelift/codegen/src/ranges.rs | 1 + cranelift/codegen/src/remove_constant_phis.rs | 1 + cranelift/codegen/src/result.rs | 1 + cranelift/codegen/src/scoped_hash_map.rs | 1 + cranelift/codegen/src/settings.rs | 1 + cranelift/codegen/src/souper_harvest.rs | 1 + cranelift/codegen/src/take_and_replace.rs | 1 + cranelift/codegen/src/timing.rs | 1 + cranelift/codegen/src/traversals.rs | 1 + cranelift/codegen/src/unreachable_code.rs | 1 + cranelift/codegen/src/value_label.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 1 + cranelift/codegen/src/write.rs | 1 + 167 files changed, 176 insertions(+), 4 deletions(-) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index 93adce052c9f..b915db0f79e7 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -400,3 +400,4 @@ fn get_ext_opcode(op: Opcode) -> Option { _ => Some(op), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs index cd34c0b3ff13..022eb7db5fca 100644 --- a/cranelift/codegen/src/binemit/mod.rs +++ b/cranelift/codegen/src/binemit/mod.rs @@ -190,3 +190,4 @@ pub struct CodeInfo { /// Number of bytes in total. pub total_size: CodeOffset, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/cfg_printer.rs b/cranelift/codegen/src/cfg_printer.rs index ef71b63ca712..8c07f0ac478b 100644 --- a/cranelift/codegen/src/cfg_printer.rs +++ b/cranelift/codegen/src/cfg_printer.rs @@ -81,3 +81,4 @@ impl<'a> Display for CFGPrinter<'a> { self.write(f) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/constant_hash.rs b/cranelift/codegen/src/constant_hash.rs index 1de2a2edb43e..be018675b5e2 100644 --- a/cranelift/codegen/src/constant_hash.rs +++ b/cranelift/codegen/src/constant_hash.rs @@ -60,3 +60,4 @@ pub fn probe + ?Sized>( idx += step; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index c37de05497bc..46267cb446d2 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -391,3 +391,4 @@ impl Context { self.verify_if(fisa) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 10fe7af5b032..f14e00cb3b6b 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -222,3 +222,4 @@ mod test { assert_eq!(*map.get(&k0, &ctx).unwrap(), 84); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/cursor.rs b/cranelift/codegen/src/cursor.rs index ae7b0ea874ad..b1bec22fa159 100644 --- a/cranelift/codegen/src/cursor.rs +++ b/cranelift/codegen/src/cursor.rs @@ -687,3 +687,4 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> { &mut self.func.dfg } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index a2e69a724e1b..26a66d53694e 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -420,3 +420,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dbg.rs b/cranelift/codegen/src/dbg.rs index 4796f3967b91..8a0da7a24aed 100644 --- a/cranelift/codegen/src/dbg.rs +++ b/cranelift/codegen/src/dbg.rs @@ -26,3 +26,4 @@ where } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 23d099a4251a..90e700d0097d 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -771,3 +771,4 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree/simple.rs b/cranelift/codegen/src/dominator_tree/simple.rs index 853158bc80b1..9abc47e4df95 100644 --- a/cranelift/codegen/src/dominator_tree/simple.rs +++ b/cranelift/codegen/src/dominator_tree/simple.rs @@ -582,3 +582,4 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph.rs index 46fdaf36985b..a8d6a80ee3b2 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph.rs @@ -1110,3 +1110,4 @@ pub(crate) struct Stats { pub(crate) elaborate_func_post_insts: u64, pub(crate) eclass_size_limit: u64, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index 062196964c96..f2f2048497b9 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -236,3 +236,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index 9328354b2dc2..ec617344b9ba 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -865,3 +865,4 @@ impl<'a> Elaborator<'a> { self.stats.elaborate_func_post_insts += self.func.dfg.num_insts() as u64; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/flowgraph.rs b/cranelift/codegen/src/flowgraph.rs index 6478dfddbf90..9358c851b4e3 100644 --- a/cranelift/codegen/src/flowgraph.rs +++ b/cranelift/codegen/src/flowgraph.rs @@ -347,3 +347,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index a597d18869ce..973cca13ece1 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -239,3 +239,4 @@ pub fn try_finish_recompile(func: &Function, bytes: &[u8]) -> Result Err(RecompileError::Deserialize(err)), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/inline.rs b/cranelift/codegen/src/inline.rs index ac150c598980..6e6756871545 100644 --- a/cranelift/codegen/src/inline.rs +++ b/cranelift/codegen/src/inline.rs @@ -1584,3 +1584,4 @@ fn create_constants(allocs: &mut InliningAllocs, func: &mut ir::Function, callee allocs.constants[*callee_constant] = Some(inlined_constant).into(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs index 7b42e1728663..91cb01ca7cf3 100644 --- a/cranelift/codegen/src/inst_predicates.rs +++ b/cranelift/codegen/src/inst_predicates.rs @@ -215,3 +215,4 @@ pub(crate) fn visit_block_succs( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/atomic_rmw_op.rs b/cranelift/codegen/src/ir/atomic_rmw_op.rs index 0317fc00d2c1..ea6a16b7d969 100644 --- a/cranelift/codegen/src/ir/atomic_rmw_op.rs +++ b/cranelift/codegen/src/ir/atomic_rmw_op.rs @@ -102,3 +102,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/builder.rs b/cranelift/codegen/src/ir/builder.rs index 24d9beaee660..c36673bd79ee 100644 --- a/cranelift/codegen/src/ir/builder.rs +++ b/cranelift/codegen/src/ir/builder.rs @@ -280,3 +280,4 @@ mod tests { .Trap(Opcode::Return, I32, TrapCode::BAD_CONVERSION_TO_INTEGER); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index 009f95bf391c..454423f7a189 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -402,3 +402,4 @@ mod tests { assert_eq!("bogus".parse::(), Err(())); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index 67310cd9462f..5612510c8f33 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -485,3 +485,4 @@ mod tests { assert_eq!(Ieee128::try_from(&constant).unwrap().bits(), value.bits()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/debug_tags.rs b/cranelift/codegen/src/ir/debug_tags.rs index 39d137c2973b..d2ca049f6c53 100644 --- a/cranelift/codegen/src/ir/debug_tags.rs +++ b/cranelift/codegen/src/ir/debug_tags.rs @@ -139,3 +139,4 @@ impl core::fmt::Display for DebugTag { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dfg.rs b/cranelift/codegen/src/ir/dfg.rs index 3dd2ad4211c3..e48cdd42d990 100644 --- a/cranelift/codegen/src/ir/dfg.rs +++ b/cranelift/codegen/src/ir/dfg.rs @@ -1882,3 +1882,4 @@ mod tests { assert_eq!(v1, func.dfg.inst_args(call_inst_dup)[0]); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dynamic_type.rs b/cranelift/codegen/src/ir/dynamic_type.rs index 53027c196945..369bcc74eeba 100644 --- a/cranelift/codegen/src/ir/dynamic_type.rs +++ b/cranelift/codegen/src/ir/dynamic_type.rs @@ -52,3 +52,4 @@ pub fn dynamic_to_fixed(ty: Type) -> Type { _ => unreachable!("unhandled type: {}", ty), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/entities.rs b/cranelift/codegen/src/ir/entities.rs index cbb8f3097aff..a1ab10662d7d 100644 --- a/cranelift/codegen/src/ir/entities.rs +++ b/cranelift/codegen/src/ir/entities.rs @@ -562,3 +562,4 @@ mod tests { assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 4130f23792b4..80730652054a 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -287,3 +287,4 @@ impl<'a> Display for DisplayExceptionTable<'a> { Ok(()) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extfunc.rs b/cranelift/codegen/src/ir/extfunc.rs index ebfaf3a8ddaf..61880e27fc84 100644 --- a/cranelift/codegen/src/ir/extfunc.rs +++ b/cranelift/codegen/src/ir/extfunc.rs @@ -418,3 +418,4 @@ mod tests { assert_eq!(sig.to_string(), "(i32, i32x4) -> f32, i8 windows_fastcall"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index d28ebcb4e7b2..e80fb4cf34b4 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -336,3 +336,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/function.rs b/cranelift/codegen/src/ir/function.rs index 80926edcdf1c..296d0c9cf938 100644 --- a/cranelift/codegen/src/ir/function.rs +++ b/cranelift/codegen/src/ir/function.rs @@ -517,3 +517,4 @@ impl<'a> fmt::Debug for DisplayFunctionSpec<'a> { write_function_spec(fmt, self.0) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/globalvalue.rs b/cranelift/codegen/src/ir/globalvalue.rs index 89120c8b8364..8ea7372c7349 100644 --- a/cranelift/codegen/src/ir/globalvalue.rs +++ b/cranelift/codegen/src/ir/globalvalue.rs @@ -145,3 +145,4 @@ impl fmt::Display for GlobalValueData { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 051f26ea451c..ce89abd2307d 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1959,3 +1959,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 80c04e48e6fb..6a95b1ce9975 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -1538,3 +1538,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 5bdad87d941f..85d6d77b1a51 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -173,3 +173,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/known_symbol.rs b/cranelift/codegen/src/ir/known_symbol.rs index c3d17501a39b..6c594b7faff3 100644 --- a/cranelift/codegen/src/ir/known_symbol.rs +++ b/cranelift/codegen/src/ir/known_symbol.rs @@ -45,3 +45,4 @@ mod tests { assert_eq!("CoffTlsIndex".parse(), Ok(KnownSymbol::CoffTlsIndex)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/layout.rs b/cranelift/codegen/src/ir/layout.rs index 1284ab65676e..2a2d139018fe 100644 --- a/cranelift/codegen/src/ir/layout.rs +++ b/cranelift/codegen/src/ir/layout.rs @@ -1193,3 +1193,4 @@ mod tests { assert_eq!(layout.pp_cmp(i3, i2), Ordering::Greater) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/libcall.rs b/cranelift/codegen/src/ir/libcall.rs index 6b60dfd07d27..3cf1ebb2d7f2 100644 --- a/cranelift/codegen/src/ir/libcall.rs +++ b/cranelift/codegen/src/ir/libcall.rs @@ -230,3 +230,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memflags.rs b/cranelift/codegen/src/ir/memflags.rs index 45f32ce85fd2..726004dcd59f 100644 --- a/cranelift/codegen/src/ir/memflags.rs +++ b/cranelift/codegen/src/ir/memflags.rs @@ -485,3 +485,4 @@ mod tests { assert!(big.set_by_name("table").is_err()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index b7b0d7e2db1e..8501c9bb73a3 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -188,3 +188,4 @@ impl MemoryTypeData { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/mod.rs b/cranelift/codegen/src/ir/mod.rs index eca17e7badda..db671b366444 100644 --- a/cranelift/codegen/src/ir/mod.rs +++ b/cranelift/codegen/src/ir/mod.rs @@ -117,3 +117,4 @@ pub enum ValueLabelAssignments { value: Value, }, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index b10f43f78d06..97cb8413bc1c 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -1678,3 +1678,4 @@ pub fn check_vcode_facts( } Ok(()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/progpoint.rs b/cranelift/codegen/src/ir/progpoint.rs index 84d394276f67..dafcd16d7c5d 100644 --- a/cranelift/codegen/src/ir/progpoint.rs +++ b/cranelift/codegen/src/ir/progpoint.rs @@ -73,3 +73,4 @@ mod tests { assert_eq!(pp2.to_string(), "block3"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/sourceloc.rs b/cranelift/codegen/src/ir/sourceloc.rs index 6704574d0d09..38efbe2939aa 100644 --- a/cranelift/codegen/src/ir/sourceloc.rs +++ b/cranelift/codegen/src/ir/sourceloc.rs @@ -115,3 +115,4 @@ mod tests { assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 1ad2a5d7d871..3c10fdc98026 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -249,3 +249,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/trapcode.rs b/cranelift/codegen/src/ir/trapcode.rs index e3fbcfbb4a50..f990f312b94f 100644 --- a/cranelift/codegen/src/ir/trapcode.rs +++ b/cranelift/codegen/src/ir/trapcode.rs @@ -145,3 +145,4 @@ mod tests { assert_eq!("users".parse::(), Err(())); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs index bc7704cf0662..48e98fd352d2 100644 --- a/cranelift/codegen/src/ir/types.rs +++ b/cranelift/codegen/src/ir/types.rs @@ -622,3 +622,4 @@ mod tests { assert_eq!(Type::int_with_byte_size(evil), None); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs index 6ad9b697cd02..92aaa198effa 100644 --- a/cranelift/codegen/src/ir/user_stack_maps.rs +++ b/cranelift/codegen/src/ir/user_stack_maps.rs @@ -197,3 +197,4 @@ impl UserStackMap { }) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index c7443cfd7c22..875afdc85f3c 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -1632,3 +1632,4 @@ fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv { env } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index a382a5ef725a..d912aee4dd79 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -724,3 +724,4 @@ impl TestBitAndBranchKind { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 06e0eb017708..b5bb377591df 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -3685,3 +3685,4 @@ fn emit_return_call_common_sequence( sink.put4(key.enc_auti_hint()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index baa42a265cb2..fdca784dd038 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -7970,3 +7970,4 @@ fn test_cond_invert() { assert_eq!(cond.invert().invert(), cond); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index fcd67deed576..69a1ca5312e7 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -1240,3 +1240,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index c47e20f94280..e8308a425840 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -3112,3 +3112,4 @@ mod tests { assert_eq!(expected, core::mem::size_of::()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 7db69df4ebe4..c625d99d964d 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -279,3 +279,4 @@ pub fn pretty_print_vreg_vector(reg: Reg, size: VectorSize) -> String { pub fn pretty_print_vreg_element(reg: Reg, idx: usize, size: ScalarSize) -> String { show_vreg_element(reg, idx as u8, size) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs index 9378c46fa53b..25a095983c42 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs @@ -175,3 +175,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs index 6d51a380433f..99c9f2f95592 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.rs +++ b/cranelift/codegen/src/isa/aarch64/lower.rs @@ -143,3 +143,4 @@ impl LowerBackend for AArch64Backend { type FactFlowState = pcc::FactFlowState; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 307414f1012b..91ee0718b776 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -858,3 +858,4 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.backend.flags.is_pic() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 2e0f7bd77dda..3867a060b7f3 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -14,3 +14,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_aarch64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 5c265aebeb0d..40bb5d9aa966 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -278,3 +278,4 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs index e5ee1919803e..3b5e31d11c0e 100644 --- a/cranelift/codegen/src/isa/aarch64/pcc.rs +++ b/cranelift/codegen/src/isa/aarch64/pcc.rs @@ -568,3 +568,4 @@ fn check_store_addr( let _output_fact = ctx.store(&fact, ty, None)?; Ok(()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/settings.rs b/cranelift/codegen/src/isa/aarch64/settings.rs index 2cda69446ff3..21031399b5eb 100644 --- a/cranelift/codegen/src/isa/aarch64/settings.rs +++ b/cranelift/codegen/src/isa/aarch64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/arm64.rs`. include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/call_conv.rs b/cranelift/codegen/src/isa/call_conv.rs index a8f6ce50203e..65e6c514c830 100644 --- a/cranelift/codegen/src/isa/call_conv.rs +++ b/cranelift/codegen/src/isa/call_conv.rs @@ -153,3 +153,4 @@ impl str::FromStr for CallConv { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2bc2033983ef..2c31830e139a 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -499,3 +499,4 @@ impl Debug for &dyn TargetIsa { ) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley32.rs b/cranelift/codegen/src/isa/pulley32.rs index b337274660d0..e3467275472e 100644 --- a/cranelift/codegen/src/isa/pulley32.rs +++ b/cranelift/codegen/src/isa/pulley32.rs @@ -11,3 +11,4 @@ impl PulleyTargetKind for Pulley32 { PointerWidth::PointerWidth32 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley64.rs b/cranelift/codegen/src/isa/pulley64.rs index 31b1d08a04b2..234840c45eb5 100644 --- a/cranelift/codegen/src/isa/pulley64.rs +++ b/cranelift/codegen/src/isa/pulley64.rs @@ -11,3 +11,4 @@ impl PulleyTargetKind for Pulley64 { PointerWidth::PointerWidth64 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 72bafa7c30d6..05952c94a4ab 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -985,3 +985,4 @@ fn create_reg_environment() -> MachineEnv { scratch_by_class: [None, None, None], } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index b53f5d3fafa6..43d1e8a82a82 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -779,3 +779,4 @@ impl fmt::Display for AddrG32Bne { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs index 74082b4260c3..25614218b03b 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs @@ -707,3 +707,4 @@ fn patch_pc_rel_offset

( assert_eq!(*chunk, [0, 0, 0, 0]); *chunk = (end - start - 4).to_le_bytes(); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index d76705a7fb9f..497ba5e2031e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -952,3 +952,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs index 90f7d36e104b..069050e7cd55 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs @@ -162,3 +162,4 @@ define_registers! { v_reg(30) => v30, writable_v30; v_reg(31) => v31, writable_v31; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.rs b/cranelift/codegen/src/isa/pulley_shared/lower.rs index 8dd5a0cea50c..b436d1d3e46e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower.rs @@ -34,3 +34,4 @@ where type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs index d72b6a023789..baa93a5eb1bc 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs @@ -327,3 +327,4 @@ where let mut isle_ctx = PulleyIsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs index 45dd7050dc3c..6b0853db8f25 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_pulley_shared.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 018c859d4e41..f86782a0a2e9 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -312,3 +312,4 @@ impl PulleyFlags { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/settings.rs b/cranelift/codegen/src/isa/pulley_shared/settings.rs index 5d4fd19ed116..d611e3a6f2a5 100644 --- a/cranelift/codegen/src/isa/pulley_shared/settings.rs +++ b/cranelift/codegen/src/isa/pulley_shared/settings.rs @@ -14,3 +14,4 @@ use core::fmt; include!(concat!(env!("OUT_DIR"), "/settings-pulley.rs")); impl IsaFlags for Flags {} +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index 70c799cd06d0..d373057ec6fa 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -1055,3 +1055,4 @@ impl Riscv64MachineDeps { insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index 918a4854b3a3..d710f4348e46 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -1946,3 +1946,4 @@ impl ZcbMemOp { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 5e631c3af1d3..714271546539 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -2885,3 +2885,4 @@ fn return_call_emit_impl( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 3b0cf59b633f..09880464c68e 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -2283,3 +2283,4 @@ fn riscv64_worst_case_instruction_size() { println!("calculate max size is {} , inst is {:?}", max.0, max.1); assert!(max.0 <= Inst::worst_case_size()); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/encode.rs b/cranelift/codegen/src/isa/riscv64/inst/encode.rs index 048fc2af05b5..b167f319ccfe 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs @@ -718,3 +718,4 @@ pub fn encode_fp_rrrr( funct7, ) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 92a8ceb60b83..5e9f0faeee45 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -371,3 +371,4 @@ mod test { assert!(Inst::imm_min() == i32::MIN as i64 - 2048); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 8db973aa426e..dc41e455c3c3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -1940,3 +1940,4 @@ mod test { assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/regs.rs b/cranelift/codegen/src/isa/riscv64/inst/regs.rs index 76493732bfe1..d1e9fa7cd00f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/regs.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/regs.rs @@ -151,3 +151,4 @@ pub const fn pf_reg(enc: usize) -> PReg { pub const fn pv_reg(enc: usize) -> PReg { PReg::new(enc, RegClass::Vector) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs index 0b2ef040b19c..0edc32ba221f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs @@ -171,3 +171,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 269e6481b506..dcbda4aa1850 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -1148,3 +1148,4 @@ pub trait VecInstOverlapInfo { self.forbids_src_dst_overlaps() || (mask.is_enabled() && self.forbids_mask_dst_overlaps()) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower.rs b/cranelift/codegen/src/isa/riscv64/lower.rs index 117778f820b3..8de92855b2f8 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.rs +++ b/cranelift/codegen/src/isa/riscv64/lower.rs @@ -33,3 +33,4 @@ impl LowerBackend for Riscv64Backend { type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index e567660def01..81d0e2061b54 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -749,3 +749,4 @@ pub(crate) fn lower_branch( let mut isle_ctx = RV64IsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs index ad8466108a3b..9fb78bfb80ca 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_riscv64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 49060989a2df..6a50953d6750 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -292,3 +292,4 @@ fn isa_constructor( let backend = Riscv64Backend::new_with_flags(triple, shared_flags, isa_flags); Ok(backend.wrapped()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/settings.rs b/cranelift/codegen/src/isa/riscv64/settings.rs index c896dd5fe911..f4ca3fb3a88a 100644 --- a/cranelift/codegen/src/isa/riscv64/settings.rs +++ b/cranelift/codegen/src/isa/riscv64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/riscv64/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-riscv64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 8174d3479106..02658acfc0f5 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -1627,3 +1627,4 @@ fn tail_create_machine_env() -> MachineEnv { scratch_by_class: [None, None, None], } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/args.rs b/cranelift/codegen/src/isa/s390x/inst/args.rs index 33e790673b61..5e114104b320 100644 --- a/cranelift/codegen/src/isa/s390x/inst/args.rs +++ b/cranelift/codegen/src/isa/s390x/inst/args.rs @@ -269,3 +269,4 @@ impl PrettyPrint for Cond { s.to_string() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index 5baef0fede8a..e218fe55454a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3559,3 +3559,4 @@ impl Inst { state.clear_post_insn(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index 569c16ac5c4d..aa4ab565eaef 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -13496,3 +13496,4 @@ fn test_s390x_binemit() { assert_eq!(expected_encoding, actual_encoding); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 9559f34ac7f8..edb66ba08196 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -200,3 +200,4 @@ impl PrettyPrint for UImm32Shifted { format!("{}", self.bits) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 7d9757bae776..f594c72c21f6 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -3550,3 +3550,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index d3985bb9d20b..eebcb36a33df 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -184,3 +184,4 @@ pub fn pretty_print_regpair_mod_lo(rd: WritableRegPair, ri: Reg) -> String { pub fn pretty_print_fpr(reg: Reg) -> (String, Option) { (show_reg(reg), maybe_show_fpr(reg)) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind.rs b/cranelift/codegen/src/isa/s390x/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs index 6ae2c7e262d9..a37ca84767d9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs @@ -216,3 +216,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index 9af0b96147e5..c111eee9c915 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -28,3 +28,4 @@ impl LowerBackend for S390xBackend { type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index 02765c8b7bbf..e93358b1a972 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -859,3 +859,4 @@ fn condcode_is_signed(cc: IntCC) -> bool { IntCC::UnsignedLessThan => false, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index a6daad546b62..c32fdefdc440 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_s390x.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 511ddf77305d..8393768c442a 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -236,3 +236,4 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/settings.rs b/cranelift/codegen/src/isa/s390x/settings.rs index 5bf89030f19d..16a717f9e7c7 100644 --- a/cranelift/codegen/src/isa/s390x/settings.rs +++ b/cranelift/codegen/src/isa/s390x/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/s390x/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index 7b842ac7e4ab..cd98fb9b8222 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -249,3 +249,4 @@ impl<'a> Writer<'a> { self.offset += 4; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index 5989e0b2a12b..0fb19d0408c7 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -286,3 +286,4 @@ impl UnwindInfo { fde } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winarm64.rs b/cranelift/codegen/src/isa/unwind/winarm64.rs index 3d3cdd8fcf48..803867af2a85 100644 --- a/cranelift/codegen/src/isa/unwind/winarm64.rs +++ b/cranelift/codegen/src/isa/unwind/winarm64.rs @@ -315,3 +315,4 @@ pub(crate) fn create_unwind_info_from_insts( Ok(UnwindInfo { unwind_codes }) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winx64.rs b/cranelift/codegen/src/isa/unwind/winx64.rs index 38cb46b83b55..e352dc6351df 100644 --- a/cranelift/codegen/src/isa/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/unwind/winx64.rs @@ -310,3 +310,4 @@ fn ensure_unwind_offset(offset: u32) -> CodegenResult { } Ok(offset as u8) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index df8fdce35223..8e9bbf0efdc3 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -20,3 +20,4 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index cd07032c2bc2..e00689769b40 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -1346,3 +1346,4 @@ fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv { env } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 35c22ca49b3c..c5e6a117ec04 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -1061,3 +1061,4 @@ impl OperandSize { self.to_bytes() * 8 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 363f9194bd6f..2374d6e63b58 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -2193,3 +2193,4 @@ fn emit_lea( _ => lea(*dst.as_ref(), addr, sink), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_state.rs b/cranelift/codegen/src/isa/x64/inst/emit_state.rs index 426a17a2803b..98ffebf3f3be 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_state.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_state.rs @@ -53,3 +53,4 @@ impl EmitState { self.user_stack_map = None; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 9e47ea081b56..7d9e7a6e7eba 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -383,3 +383,4 @@ fn test_x64_emit() { assert_eq!(expected_encoding, actual_encoding, "{expected_printing}"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index b326429501e3..0229c5ed42c9 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -562,3 +562,4 @@ mod tests { assert_eq!(pair.to_string(None), "(%v500 <- %v400)"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 4c77b2c564b1..0567b9554fb6 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -1678,3 +1678,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 2bcc23d8c426..33cb94dfd060 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -174,3 +174,4 @@ pub fn pretty_print_reg(reg: Reg, size: u8) -> String { name } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs index 4c9400df41bf..d32c59dd9fee 100644 --- a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs +++ b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs @@ -47,3 +47,4 @@ pub fn control_context_layout() -> ControlContextLayout { pub fn payload_register() -> Reg { regs::rdi() } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind.rs b/cranelift/codegen/src/isa/x64/inst/unwind.rs index cb86c3b7ccd5..56289f082012 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind.rs @@ -3,3 +3,4 @@ pub(crate) mod systemv; #[cfg(feature = "unwind")] pub(crate) mod winx64; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs index 3f46843ab4f4..ecbe379cd7da 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs @@ -202,3 +202,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs index f848a5baf76f..f6d80f5e531f 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs @@ -14,3 +14,4 @@ impl crate::isa::unwind::winx64::RegisterMapper for RegisterMapper { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index a000f8ece143..210f1d964a71 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -351,3 +351,4 @@ impl LowerBackend for X64Backend { type FactFlowState = pcc::FactFlowState; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 57bfa06ee7fd..3917b4203ca5 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -1249,3 +1249,4 @@ const I8X16_USHR_MASKS: [u8; 128] = [ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ]; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index c48996ec46d6..1bc434f23b5a 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -14,3 +14,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_x64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 37a386504347..52d1213866fe 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -264,3 +264,4 @@ fn isa_constructor( let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags)?; Ok(backend.wrapped()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs index 09b356d69958..b82eb7d5014e 100644 --- a/cranelift/codegen/src/isa/x64/pcc.rs +++ b/cranelift/codegen/src/isa/x64/pcc.rs @@ -324,3 +324,4 @@ fn compute_addr(ctx: &FactContext, vcode: &VCode, amode: &Amode, bits: u16 Amode::RipRelative { .. } => None, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/settings.rs b/cranelift/codegen/src/isa/x64/settings.rs index 12420311b34c..83faa5585cb6 100644 --- a/cranelift/codegen/src/isa/x64/settings.rs +++ b/cranelift/codegen/src/isa/x64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/x86/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-x86.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index a2b58b15431d..7e974bff3f56 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -941,3 +941,4 @@ macro_rules! isle_common_prelude_methods { } }; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/branch_to_trap.rs b/cranelift/codegen/src/legalizer/branch_to_trap.rs index 1cbb0e657ffb..330c47abc6e7 100644 --- a/cranelift/codegen/src/legalizer/branch_to_trap.rs +++ b/cranelift/codegen/src/legalizer/branch_to_trap.rs @@ -96,3 +96,4 @@ impl BranchToTrap { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index 45444d161934..85b7dee06108 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -176,3 +176,4 @@ fn symbol( WalkCommand::Continue } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs index 768afd306752..44dcd1ad4dcb 100644 --- a/cranelift/codegen/src/legalizer/mod.rs +++ b/cranelift/codegen/src/legalizer/mod.rs @@ -392,3 +392,4 @@ fn expand_stack_load( WalkCommand::Continue } +use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 425edb25e160..7cf1a47e3305 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -43,6 +43,8 @@ include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); #[macro_use] mod machinst; +mod prelude; + pub mod binemit; pub mod cfg_printer; pub mod cursor; @@ -122,3 +124,4 @@ macro_rules! trace_log_enabled { } include!(concat!(env!("OUT_DIR"), "/version.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index 5d88c519af5a..adb70bc20971 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -430,3 +430,4 @@ mod tests { assert_eq!(loop_analysis.loop_level(block5).level(), 1); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 6b8baee92330..c98093d88bf5 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -2615,3 +2615,4 @@ mod tests { assert_eq!(core::mem::size_of::(), 24); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 9e48e2c4d607..5edbc8b0b62f 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -483,3 +483,4 @@ mod test { assert!(order.lowered_order[8].out_edge().is_none()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index a9e4a8878020..6b5de1ea41b7 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -2910,3 +2910,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index cd2e7e9d6ac5..efc1f60de90f 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -95,3 +95,4 @@ pub fn compile( Ok((vcode, regalloc_result)) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 01f397c8c67f..222dc072e470 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -21,3 +21,4 @@ where let alignment_mask = alignment - 1.into(); (x + alignment_mask) & !alignment_mask } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/inst_common.rs b/cranelift/codegen/src/machinst/inst_common.rs index b077dd3b6112..1a15cde4e1fa 100644 --- a/cranelift/codegen/src/machinst/inst_common.rs +++ b/cranelift/codegen/src/machinst/inst_common.rs @@ -14,3 +14,4 @@ pub struct InsnInput { pub(crate) insn: IRInst, pub(crate) input: usize, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index f73ede5b257b..96cfe717456b 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -849,3 +849,4 @@ where &self.lower_ctx.f.dfg } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 2d864e04b7c1..6d61a37f3072 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -1797,3 +1797,4 @@ mod tests { assert_eq!(uses[v5], ValueUseState::Unused); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 4c014f5dd0f2..195903f6d0aa 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -627,3 +627,4 @@ pub trait TextSectionBuilder { /// the bytes of the text section. fn finish(&mut self, ctrl_plane: &mut ControlPlane) -> Vec; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/pcc.rs b/cranelift/codegen/src/machinst/pcc.rs index 046b2ca3b3e2..665790bad4b9 100644 --- a/cranelift/codegen/src/machinst/pcc.rs +++ b/cranelift/codegen/src/machinst/pcc.rs @@ -164,3 +164,4 @@ pub(crate) enum LoadOrStore<'a> { stored_fact: Option<&'a Fact>, }, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index dd28ee05f4c8..5d364601297d 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -563,3 +563,4 @@ pub trait PrettyPrint { self.pretty_print(0) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index 8a684d868f86..f7d3a2c0c91b 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -150,3 +150,4 @@ pub(crate) fn writable_value_regs(regs: ValueRegs) -> ValueRegs>) -> ValueRegs { regs.map(|r| r.to_reg()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 22c855584c09..a1fb9c9e12bb 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -2058,3 +2058,4 @@ mod test { // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes. } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/nan_canonicalization.rs b/cranelift/codegen/src/nan_canonicalization.rs index e6a73deaf83a..04f8ffdc0f6f 100644 --- a/cranelift/codegen/src/nan_canonicalization.rs +++ b/cranelift/codegen/src/nan_canonicalization.rs @@ -124,3 +124,4 @@ fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst, has_vector_support: bool) pos.prev_inst(); // Step backwards so the pass does not skip instructions. } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 3c9dd6693edf..9253b690a60d 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -367,3 +367,4 @@ impl<'a, 'b, 'c> generated_code::Context for IsleContext<'a, 'b, 'c> { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/div_const.rs b/cranelift/codegen/src/opts/div_const.rs index a88f0c6344f5..4ef0163a2d8b 100644 --- a/cranelift/codegen/src/opts/div_const.rs +++ b/cranelift/codegen/src/opts/div_const.rs @@ -1212,3 +1212,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/generated_code.rs b/cranelift/codegen/src/opts/generated_code.rs index 82208623362a..2ff9eaef16bc 100644 --- a/cranelift/codegen/src/opts/generated_code.rs +++ b/cranelift/codegen/src/opts/generated_code.rs @@ -16,3 +16,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_opt.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index b2d13852bc08..981d7fe27e43 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,4 +1,8 @@ -use alloc::format; -use alloc::string::{String, ToString}; -use alloc::vec::Vec; -use alloc::vec; +pub use alloc::format; +pub use alloc::string::{String, ToString}; +pub use alloc::vec::Vec; +pub use alloc::vec; +pub use alloc::slice; + +pub use core::prelude::*; +pub use core::ops; \ No newline at end of file diff --git a/cranelift/codegen/src/print_errors.rs b/cranelift/codegen/src/print_errors.rs index 21a2767267e8..348497eeb96b 100644 --- a/cranelift/codegen/src/print_errors.rs +++ b/cranelift/codegen/src/print_errors.rs @@ -221,3 +221,4 @@ pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String { err.to_string() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ranges.rs b/cranelift/codegen/src/ranges.rs index 419dee83c08f..4ea817d64457 100644 --- a/cranelift/codegen/src/ranges.rs +++ b/cranelift/codegen/src/ranges.rs @@ -129,3 +129,4 @@ impl Ranges { self.reverse_index(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index ae9f3ad6ed24..a6b2712059f0 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -418,3 +418,4 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) n_consts ); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index c62572cd9958..0f56d06772ed 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -109,3 +109,4 @@ impl<'a> core::fmt::Debug for CompileError<'a> { /// A convenient alias for a `Result` that uses `CompileError` as the error type. pub type CompileResult<'a, T> = Result>; +use crate::prelude::*; diff --git a/cranelift/codegen/src/scoped_hash_map.rs b/cranelift/codegen/src/scoped_hash_map.rs index b599d36dc205..0835af1c4368 100644 --- a/cranelift/codegen/src/scoped_hash_map.rs +++ b/cranelift/codegen/src/scoped_hash_map.rs @@ -332,3 +332,4 @@ mod tests { assert_eq!(map.get(&NullCtx, &3), Some(&4)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 158ba139bd42..39899e63480c 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -566,3 +566,4 @@ enable_incremental_compilation_cache_checks = false assert_eq!(f.opt_level(), super::OptLevel::Speed); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/souper_harvest.rs b/cranelift/codegen/src/souper_harvest.rs index 02958ed56a71..5ea25882bae3 100644 --- a/cranelift/codegen/src/souper_harvest.rs +++ b/cranelift/codegen/src/souper_harvest.rs @@ -587,3 +587,4 @@ fn post_order_dfs( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index 584d9239d0fa..e6232e901a39 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -89,3 +89,4 @@ where (&mut *self.container, &mut self.value) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index a06c6001ef41..0c02dcb790c8 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -303,3 +303,4 @@ mod tests { assert_eq!(Pass::regalloc.to_string(), "Register allocation"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/traversals.rs b/cranelift/codegen/src/traversals.rs index db57036aacd6..24e8feb38b61 100644 --- a/cranelift/codegen/src/traversals.rs +++ b/cranelift/codegen/src/traversals.rs @@ -277,3 +277,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/unreachable_code.rs b/cranelift/codegen/src/unreachable_code.rs index 68d7bd33fdeb..7af5e6d7d33c 100644 --- a/cranelift/codegen/src/unreachable_code.rs +++ b/cranelift/codegen/src/unreachable_code.rs @@ -71,3 +71,4 @@ pub fn eliminate_unreachable_code( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/value_label.rs b/cranelift/codegen/src/value_label.rs index 65b3e7d1eac9..f822e19437c8 100644 --- a/cranelift/codegen/src/value_label.rs +++ b/cranelift/codegen/src/value_label.rs @@ -30,3 +30,4 @@ pub enum LabelValueLoc { /// Resulting map of Value labels and their ranges/locations. pub type ValueLabelsRanges = HashMap>; +use crate::prelude::*; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 304c3ebb202f..a5f66efd89b7 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2314,3 +2314,4 @@ mod tests { assert_err_with_msg!(errors, "block0 cannot be empty"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index c0025aa6fca3..ab4b51effee1 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -749,3 +749,4 @@ mod tests { ); } } +use crate::prelude::*; From a04639f6e32fc48c5313a2e8d3346d9cdaf8dd29 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 19:33:44 +0100 Subject: [PATCH 05/61] update isle to use alloc and core --- cranelift/isle/isle/src/codegen.rs | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/cranelift/isle/isle/src/codegen.rs b/cranelift/isle/isle/src/codegen.rs index c215e1db74ea..e42ef1ae5a7c 100644 --- a/cranelift/isle/isle/src/codegen.rs +++ b/cranelift/isle/isle/src/codegen.rs @@ -166,7 +166,8 @@ impl<'a> Codegen<'a> { } writeln!(code, "\nuse super::*; // Pulls in all external types.").unwrap(); - writeln!(code, "use std::marker::PhantomData;").unwrap(); + writeln!(code, "use alloc::vec::Vec;").unwrap(); + writeln!(code, "use core::{{marker::PhantomData, ops}};").unwrap(); } fn generate_trait_sig(&self, code: &mut String, indent: &str, sig: &ExternalSig) { @@ -271,38 +272,38 @@ pub trait Length {{ fn len(&self) -> usize; }} -impl Length for std::vec::Vec {{ +impl Length for alloc::vec::Vec {{ fn len(&self) -> usize {{ - std::vec::Vec::len(self) + alloc::vec::Vec::len(self) }} }} pub struct ContextIterWrapper {{ iter: I, - _ctx: std::marker::PhantomData, + _ctx: core::marker::PhantomData, }} impl Default for ContextIterWrapper {{ fn default() -> Self {{ ContextIterWrapper {{ iter: I::default(), - _ctx: std::marker::PhantomData + _ctx: core::marker::PhantomData }} }} }} -impl std::ops::Deref for ContextIterWrapper {{ +impl core::ops::Deref for ContextIterWrapper {{ type Target = I; fn deref(&self) -> &I {{ &self.iter }} }} -impl std::ops::DerefMut for ContextIterWrapper {{ +impl core::ops::DerefMut for ContextIterWrapper {{ fn deref_mut(&mut self) -> &mut I {{ &mut self.iter }} }} impl From for ContextIterWrapper {{ fn from(iter: I) -> Self {{ - Self {{ iter, _ctx: std::marker::PhantomData }} + Self {{ iter, _ctx: core::marker::PhantomData }} }} }} impl ContextIter for ContextIterWrapper {{ @@ -322,7 +323,7 @@ impl IntoContextIter for ContextIterWrapper { fn into_context_iter(self) -> Self::IntoIter {{ ContextIterWrapper {{ iter: self.iter.into_iter(), - _ctx: std::marker::PhantomData + _ctx: core::marker::PhantomData }} }} }} From 610034c698fe6d3210d9500b900add8d98dffe83 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 19:50:17 +0100 Subject: [PATCH 06/61] some instances shouldn't have been renamed, fixes cargo test --- .../codegen/src/isa/s390x/inst/emit_tests.rs | 16 ++++++++-------- cranelift/codegen/src/isa/s390x/inst/mod.rs | 2 +- cranelift/codegen/src/verifier/mod.rs | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index aa4ab565eaef..9f5afa33448e 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -12039,7 +12039,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102000", - "core %f1, 0(%r2)", + "std %f1, 0(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12054,7 +12054,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102FFF", - "core %f1, 4095(%r2)", + "std %f1, 4095(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12069,7 +12069,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1020008067", - "corey %f1, -524288(%r2)", + "stdy %f1, -524288(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12084,7 +12084,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED102FFF7F67", - "corey %f1, 524287(%r2)", + "stdy %f1, 524287(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12129,7 +12129,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123000", - "core %f1, 0(%r2,%r3)", + "std %f1, 0(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12144,7 +12144,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123FFF", - "core %f1, 4095(%r2,%r3)", + "std %f1, 4095(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12159,7 +12159,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1230008067", - "corey %f1, -524288(%r2,%r3)", + "stdy %f1, -524288(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12174,7 +12174,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED123FFF7F67", - "corey %f1, 524287(%r2,%r3)", + "stdy %f1, 524287(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index f594c72c21f6..766730533764 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -2968,7 +2968,7 @@ impl Inst { (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None), (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None), (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")), - (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("core"), Some("corey")), + (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")), (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None), (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None), (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None), diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index a5f66efd89b7..0aac5d0d024f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2130,9 +2130,9 @@ mod tests { None => panic!("Expected an error"), Some(&VerifierError { ref message, .. }) => { if !message.contains($msg) { - #[cfg(feature = "core")] + #[cfg(feature = "std")] panic!("'{}' did not contain the substring '{}'", message, $msg); - #[cfg(not(feature = "core"))] + #[cfg(not(feature = "std"))] panic!("error message did not contain the expected substring"); } } From 857923504415035508be37e9839bbf88ce882bfb Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:00:47 +0100 Subject: [PATCH 07/61] add cranelift-assembler-x64 (no_std) to CI --- .github/workflows/main.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 99a6b0204d59..592cea2b3635 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,6 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && + cargo check -p cranelift-assembler-x64 --no-default-features -F core && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. From 8a5fd53deac3bfbc7af85e5ee9711810a75975f5 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:20:16 +0100 Subject: [PATCH 08/61] fix codegen_meta, missed one spot with std::slice --- cranelift/codegen/meta/src/gen_inst.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cranelift/codegen/meta/src/gen_inst.rs b/cranelift/codegen/meta/src/gen_inst.rs index ab0db7c757a8..1b4612f108d9 100644 --- a/cranelift/codegen/meta/src/gen_inst.rs +++ b/cranelift/codegen/meta/src/gen_inst.rs @@ -312,7 +312,7 @@ fn gen_instruction_data_impl(formats: &[Rc], fmt: &mut Format (Some("args.as_slice(pool)"), "args.len(pool)") } else if format.num_value_operands == 1 { members.push("ref arg"); - (Some("std::slice::from_ref(arg)"), "1") + (Some("core::slice::from_ref(arg)"), "1") } else if format.num_value_operands > 0 { members.push("ref args"); (Some("args"), "args.len()") @@ -324,7 +324,7 @@ fn gen_instruction_data_impl(formats: &[Rc], fmt: &mut Format 0 => None, 1 => { members.push("ref destination"); - Some(("std::slice::from_ref(destination)", "1")) + Some(("core::slice::from_ref(destination)", "1")) } _ => { members.push("ref blocks"); From 35ee796bdda40909d20432834b3ece78a22f58f8 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:25:58 +0100 Subject: [PATCH 09/61] automatically remove prelude with cargo fix --- cranelift/codegen/src/binemit/mod.rs | 1 - cranelift/codegen/src/cfg_printer.rs | 1 - cranelift/codegen/src/constant_hash.rs | 1 - cranelift/codegen/src/context.rs | 1 - cranelift/codegen/src/ctxhash.rs | 1 - cranelift/codegen/src/cursor.rs | 1 - cranelift/codegen/src/dbg.rs | 1 - cranelift/codegen/src/dominator_tree/simple.rs | 1 - cranelift/codegen/src/egraph/cost.rs | 1 - cranelift/codegen/src/flowgraph.rs | 1 - cranelift/codegen/src/inst_predicates.rs | 1 - cranelift/codegen/src/ir/atomic_rmw_op.rs | 1 - cranelift/codegen/src/ir/builder.rs | 1 - cranelift/codegen/src/ir/condcodes.rs | 1 - cranelift/codegen/src/ir/constant.rs | 1 - cranelift/codegen/src/ir/dfg.rs | 1 - cranelift/codegen/src/ir/dynamic_type.rs | 1 - cranelift/codegen/src/ir/extfunc.rs | 1 - cranelift/codegen/src/ir/extname.rs | 1 - cranelift/codegen/src/ir/function.rs | 1 - cranelift/codegen/src/ir/globalvalue.rs | 1 - cranelift/codegen/src/ir/instructions.rs | 1 - cranelift/codegen/src/ir/jumptable.rs | 1 - cranelift/codegen/src/ir/known_symbol.rs | 1 - cranelift/codegen/src/ir/libcall.rs | 1 - cranelift/codegen/src/ir/memflags.rs | 1 - cranelift/codegen/src/ir/memtype.rs | 1 - cranelift/codegen/src/ir/mod.rs | 1 - cranelift/codegen/src/ir/pcc.rs | 1 - cranelift/codegen/src/ir/progpoint.rs | 1 - cranelift/codegen/src/ir/sourceloc.rs | 1 - cranelift/codegen/src/ir/user_stack_maps.rs | 1 - cranelift/codegen/src/isa/call_conv.rs | 1 - cranelift/codegen/src/isa/mod.rs | 2 +- cranelift/codegen/src/isa/unwind.rs | 1 - cranelift/codegen/src/isa/winch.rs | 1 - cranelift/codegen/src/isa/x64/inst/emit.rs | 1 - cranelift/codegen/src/isa/x64/inst/emit_state.rs | 1 - cranelift/codegen/src/isa/x64/inst/stack_switch.rs | 1 - cranelift/codegen/src/isa/x64/inst/unwind.rs | 1 - cranelift/codegen/src/isa/x64/lower.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 2 +- cranelift/codegen/src/isa/x64/pcc.rs | 1 - cranelift/codegen/src/isa/x64/settings.rs | 1 - cranelift/codegen/src/isle_prelude.rs | 1 - cranelift/codegen/src/legalizer/branch_to_trap.rs | 1 - cranelift/codegen/src/legalizer/globalvalue.rs | 1 - cranelift/codegen/src/legalizer/mod.rs | 1 - cranelift/codegen/src/lib.rs | 3 +-- cranelift/codegen/src/loop_analysis.rs | 1 - cranelift/codegen/src/machinst/blockorder.rs | 1 - cranelift/codegen/src/machinst/compile.rs | 1 - cranelift/codegen/src/machinst/helpers.rs | 1 - cranelift/codegen/src/machinst/isle.rs | 1 - cranelift/codegen/src/machinst/mod.rs | 1 - cranelift/codegen/src/machinst/pcc.rs | 1 - cranelift/codegen/src/machinst/valueregs.rs | 1 - cranelift/codegen/src/nan_canonicalization.rs | 1 - cranelift/codegen/src/opts.rs | 1 - cranelift/codegen/src/opts/div_const.rs | 1 - cranelift/codegen/src/prelude.rs | 6 +----- cranelift/codegen/src/print_errors.rs | 1 - cranelift/codegen/src/ranges.rs | 1 - cranelift/codegen/src/remove_constant_phis.rs | 1 - cranelift/codegen/src/result.rs | 1 - cranelift/codegen/src/scoped_hash_map.rs | 1 - cranelift/codegen/src/take_and_replace.rs | 1 - cranelift/codegen/src/timing.rs | 1 - cranelift/codegen/src/traversals.rs | 1 - cranelift/codegen/src/unreachable_code.rs | 1 - cranelift/codegen/src/value_label.rs | 1 - 71 files changed, 4 insertions(+), 76 deletions(-) diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs index 022eb7db5fca..cd34c0b3ff13 100644 --- a/cranelift/codegen/src/binemit/mod.rs +++ b/cranelift/codegen/src/binemit/mod.rs @@ -190,4 +190,3 @@ pub struct CodeInfo { /// Number of bytes in total. pub total_size: CodeOffset, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/cfg_printer.rs b/cranelift/codegen/src/cfg_printer.rs index 8c07f0ac478b..ef71b63ca712 100644 --- a/cranelift/codegen/src/cfg_printer.rs +++ b/cranelift/codegen/src/cfg_printer.rs @@ -81,4 +81,3 @@ impl<'a> Display for CFGPrinter<'a> { self.write(f) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/constant_hash.rs b/cranelift/codegen/src/constant_hash.rs index be018675b5e2..1de2a2edb43e 100644 --- a/cranelift/codegen/src/constant_hash.rs +++ b/cranelift/codegen/src/constant_hash.rs @@ -60,4 +60,3 @@ pub fn probe + ?Sized>( idx += step; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index 46267cb446d2..c37de05497bc 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -391,4 +391,3 @@ impl Context { self.verify_if(fisa) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index f14e00cb3b6b..10fe7af5b032 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -222,4 +222,3 @@ mod test { assert_eq!(*map.get(&k0, &ctx).unwrap(), 84); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/cursor.rs b/cranelift/codegen/src/cursor.rs index b1bec22fa159..ae7b0ea874ad 100644 --- a/cranelift/codegen/src/cursor.rs +++ b/cranelift/codegen/src/cursor.rs @@ -687,4 +687,3 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> { &mut self.func.dfg } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dbg.rs b/cranelift/codegen/src/dbg.rs index 8a0da7a24aed..4796f3967b91 100644 --- a/cranelift/codegen/src/dbg.rs +++ b/cranelift/codegen/src/dbg.rs @@ -26,4 +26,3 @@ where } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree/simple.rs b/cranelift/codegen/src/dominator_tree/simple.rs index 9abc47e4df95..853158bc80b1 100644 --- a/cranelift/codegen/src/dominator_tree/simple.rs +++ b/cranelift/codegen/src/dominator_tree/simple.rs @@ -582,4 +582,3 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index f2f2048497b9..062196964c96 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -236,4 +236,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/flowgraph.rs b/cranelift/codegen/src/flowgraph.rs index 9358c851b4e3..6478dfddbf90 100644 --- a/cranelift/codegen/src/flowgraph.rs +++ b/cranelift/codegen/src/flowgraph.rs @@ -347,4 +347,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs index 91cb01ca7cf3..7b42e1728663 100644 --- a/cranelift/codegen/src/inst_predicates.rs +++ b/cranelift/codegen/src/inst_predicates.rs @@ -215,4 +215,3 @@ pub(crate) fn visit_block_succs( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/atomic_rmw_op.rs b/cranelift/codegen/src/ir/atomic_rmw_op.rs index ea6a16b7d969..0317fc00d2c1 100644 --- a/cranelift/codegen/src/ir/atomic_rmw_op.rs +++ b/cranelift/codegen/src/ir/atomic_rmw_op.rs @@ -102,4 +102,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/builder.rs b/cranelift/codegen/src/ir/builder.rs index c36673bd79ee..24d9beaee660 100644 --- a/cranelift/codegen/src/ir/builder.rs +++ b/cranelift/codegen/src/ir/builder.rs @@ -280,4 +280,3 @@ mod tests { .Trap(Opcode::Return, I32, TrapCode::BAD_CONVERSION_TO_INTEGER); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index 454423f7a189..009f95bf391c 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -402,4 +402,3 @@ mod tests { assert_eq!("bogus".parse::(), Err(())); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index 5612510c8f33..67310cd9462f 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -485,4 +485,3 @@ mod tests { assert_eq!(Ieee128::try_from(&constant).unwrap().bits(), value.bits()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dfg.rs b/cranelift/codegen/src/ir/dfg.rs index e48cdd42d990..3dd2ad4211c3 100644 --- a/cranelift/codegen/src/ir/dfg.rs +++ b/cranelift/codegen/src/ir/dfg.rs @@ -1882,4 +1882,3 @@ mod tests { assert_eq!(v1, func.dfg.inst_args(call_inst_dup)[0]); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dynamic_type.rs b/cranelift/codegen/src/ir/dynamic_type.rs index 369bcc74eeba..53027c196945 100644 --- a/cranelift/codegen/src/ir/dynamic_type.rs +++ b/cranelift/codegen/src/ir/dynamic_type.rs @@ -52,4 +52,3 @@ pub fn dynamic_to_fixed(ty: Type) -> Type { _ => unreachable!("unhandled type: {}", ty), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extfunc.rs b/cranelift/codegen/src/ir/extfunc.rs index 61880e27fc84..ebfaf3a8ddaf 100644 --- a/cranelift/codegen/src/ir/extfunc.rs +++ b/cranelift/codegen/src/ir/extfunc.rs @@ -418,4 +418,3 @@ mod tests { assert_eq!(sig.to_string(), "(i32, i32x4) -> f32, i8 windows_fastcall"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index e80fb4cf34b4..d28ebcb4e7b2 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -336,4 +336,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/function.rs b/cranelift/codegen/src/ir/function.rs index 296d0c9cf938..80926edcdf1c 100644 --- a/cranelift/codegen/src/ir/function.rs +++ b/cranelift/codegen/src/ir/function.rs @@ -517,4 +517,3 @@ impl<'a> fmt::Debug for DisplayFunctionSpec<'a> { write_function_spec(fmt, self.0) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/globalvalue.rs b/cranelift/codegen/src/ir/globalvalue.rs index 8ea7372c7349..89120c8b8364 100644 --- a/cranelift/codegen/src/ir/globalvalue.rs +++ b/cranelift/codegen/src/ir/globalvalue.rs @@ -145,4 +145,3 @@ impl fmt::Display for GlobalValueData { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 6a95b1ce9975..80c04e48e6fb 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -1538,4 +1538,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 85d6d77b1a51..5bdad87d941f 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -173,4 +173,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/known_symbol.rs b/cranelift/codegen/src/ir/known_symbol.rs index 6c594b7faff3..c3d17501a39b 100644 --- a/cranelift/codegen/src/ir/known_symbol.rs +++ b/cranelift/codegen/src/ir/known_symbol.rs @@ -45,4 +45,3 @@ mod tests { assert_eq!("CoffTlsIndex".parse(), Ok(KnownSymbol::CoffTlsIndex)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/libcall.rs b/cranelift/codegen/src/ir/libcall.rs index 3cf1ebb2d7f2..6b60dfd07d27 100644 --- a/cranelift/codegen/src/ir/libcall.rs +++ b/cranelift/codegen/src/ir/libcall.rs @@ -230,4 +230,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memflags.rs b/cranelift/codegen/src/ir/memflags.rs index 726004dcd59f..45f32ce85fd2 100644 --- a/cranelift/codegen/src/ir/memflags.rs +++ b/cranelift/codegen/src/ir/memflags.rs @@ -485,4 +485,3 @@ mod tests { assert!(big.set_by_name("table").is_err()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index 8501c9bb73a3..b7b0d7e2db1e 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -188,4 +188,3 @@ impl MemoryTypeData { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/mod.rs b/cranelift/codegen/src/ir/mod.rs index db671b366444..eca17e7badda 100644 --- a/cranelift/codegen/src/ir/mod.rs +++ b/cranelift/codegen/src/ir/mod.rs @@ -117,4 +117,3 @@ pub enum ValueLabelAssignments { value: Value, }, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index 97cb8413bc1c..b10f43f78d06 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -1678,4 +1678,3 @@ pub fn check_vcode_facts( } Ok(()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/progpoint.rs b/cranelift/codegen/src/ir/progpoint.rs index dafcd16d7c5d..84d394276f67 100644 --- a/cranelift/codegen/src/ir/progpoint.rs +++ b/cranelift/codegen/src/ir/progpoint.rs @@ -73,4 +73,3 @@ mod tests { assert_eq!(pp2.to_string(), "block3"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/sourceloc.rs b/cranelift/codegen/src/ir/sourceloc.rs index 38efbe2939aa..6704574d0d09 100644 --- a/cranelift/codegen/src/ir/sourceloc.rs +++ b/cranelift/codegen/src/ir/sourceloc.rs @@ -115,4 +115,3 @@ mod tests { assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs index 92aaa198effa..6ad9b697cd02 100644 --- a/cranelift/codegen/src/ir/user_stack_maps.rs +++ b/cranelift/codegen/src/ir/user_stack_maps.rs @@ -197,4 +197,3 @@ impl UserStackMap { }) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/call_conv.rs b/cranelift/codegen/src/isa/call_conv.rs index 65e6c514c830..a8f6ce50203e 100644 --- a/cranelift/codegen/src/isa/call_conv.rs +++ b/cranelift/codegen/src/isa/call_conv.rs @@ -153,4 +153,3 @@ impl str::FromStr for CallConv { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2c31830e139a..2c44409de892 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -50,7 +50,7 @@ use crate::CodegenResult; use crate::ir::{self, Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::{UnwindInfoKind, systemv::RegisterMappingError}; -use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder}; +use crate::machinst::{CompiledCodeStencil, TextSectionBuilder}; use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index cd98fb9b8222..7b842ac7e4ab 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -249,4 +249,3 @@ impl<'a> Writer<'a> { self.offset += 4; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index 8e9bbf0efdc3..df8fdce35223 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -20,4 +20,3 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 2374d6e63b58..363f9194bd6f 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -2193,4 +2193,3 @@ fn emit_lea( _ => lea(*dst.as_ref(), addr, sink), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_state.rs b/cranelift/codegen/src/isa/x64/inst/emit_state.rs index 98ffebf3f3be..426a17a2803b 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_state.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_state.rs @@ -53,4 +53,3 @@ impl EmitState { self.user_stack_map = None; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs index d32c59dd9fee..4c9400df41bf 100644 --- a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs +++ b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs @@ -47,4 +47,3 @@ pub fn control_context_layout() -> ControlContextLayout { pub fn payload_register() -> Reg { regs::rdi() } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind.rs b/cranelift/codegen/src/isa/x64/inst/unwind.rs index 56289f082012..cb86c3b7ccd5 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind.rs @@ -3,4 +3,3 @@ pub(crate) mod systemv; #[cfg(feature = "unwind")] pub(crate) mod winx64; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 210f1d964a71..a000f8ece143 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -351,4 +351,3 @@ impl LowerBackend for X64Backend { type FactFlowState = pcc::FactFlowState; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 52d1213866fe..c67ccc5b654b 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -10,7 +10,7 @@ use crate::isa::unwind::systemv; use crate::isa::x64::settings as x64_settings; use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey}; use crate::machinst::{ - CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, + CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; use crate::result::{CodegenError, CodegenResult}; diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs index b82eb7d5014e..09b356d69958 100644 --- a/cranelift/codegen/src/isa/x64/pcc.rs +++ b/cranelift/codegen/src/isa/x64/pcc.rs @@ -324,4 +324,3 @@ fn compute_addr(ctx: &FactContext, vcode: &VCode, amode: &Amode, bits: u16 Amode::RipRelative { .. } => None, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/settings.rs b/cranelift/codegen/src/isa/x64/settings.rs index 83faa5585cb6..12420311b34c 100644 --- a/cranelift/codegen/src/isa/x64/settings.rs +++ b/cranelift/codegen/src/isa/x64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/x86/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-x86.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index 7e974bff3f56..a2b58b15431d 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -941,4 +941,3 @@ macro_rules! isle_common_prelude_methods { } }; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/branch_to_trap.rs b/cranelift/codegen/src/legalizer/branch_to_trap.rs index 330c47abc6e7..1cbb0e657ffb 100644 --- a/cranelift/codegen/src/legalizer/branch_to_trap.rs +++ b/cranelift/codegen/src/legalizer/branch_to_trap.rs @@ -96,4 +96,3 @@ impl BranchToTrap { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index 85b7dee06108..45444d161934 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -176,4 +176,3 @@ fn symbol( WalkCommand::Continue } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs index 44dcd1ad4dcb..768afd306752 100644 --- a/cranelift/codegen/src/legalizer/mod.rs +++ b/cranelift/codegen/src/legalizer/mod.rs @@ -392,4 +392,3 @@ fn expand_stack_load( WalkCommand::Continue } -use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 7cf1a47e3305..fe017ca4468e 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -21,7 +21,7 @@ extern crate alloc; extern crate std; #[cfg(not(feature = "std"))] -use hashbrown::{HashMap, HashSet, hash_map}; +use hashbrown::{HashMap, hash_map}; #[cfg(feature = "std")] use std::collections::{HashMap, hash_map}; @@ -124,4 +124,3 @@ macro_rules! trace_log_enabled { } include!(concat!(env!("OUT_DIR"), "/version.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index adb70bc20971..5d88c519af5a 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -430,4 +430,3 @@ mod tests { assert_eq!(loop_analysis.loop_level(block5).level(), 1); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 5edbc8b0b62f..9e48e2c4d607 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -483,4 +483,3 @@ mod test { assert!(order.lowered_order[8].out_edge().is_none()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index efc1f60de90f..cd2e7e9d6ac5 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -95,4 +95,3 @@ pub fn compile( Ok((vcode, regalloc_result)) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 222dc072e470..01f397c8c67f 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -21,4 +21,3 @@ where let alignment_mask = alignment - 1.into(); (x + alignment_mask) & !alignment_mask } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index 96cfe717456b..f73ede5b257b 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -849,4 +849,3 @@ where &self.lower_ctx.f.dfg } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 195903f6d0aa..4c014f5dd0f2 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -627,4 +627,3 @@ pub trait TextSectionBuilder { /// the bytes of the text section. fn finish(&mut self, ctrl_plane: &mut ControlPlane) -> Vec; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/pcc.rs b/cranelift/codegen/src/machinst/pcc.rs index 665790bad4b9..046b2ca3b3e2 100644 --- a/cranelift/codegen/src/machinst/pcc.rs +++ b/cranelift/codegen/src/machinst/pcc.rs @@ -164,4 +164,3 @@ pub(crate) enum LoadOrStore<'a> { stored_fact: Option<&'a Fact>, }, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index f7d3a2c0c91b..8a684d868f86 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -150,4 +150,3 @@ pub(crate) fn writable_value_regs(regs: ValueRegs) -> ValueRegs>) -> ValueRegs { regs.map(|r| r.to_reg()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/nan_canonicalization.rs b/cranelift/codegen/src/nan_canonicalization.rs index 04f8ffdc0f6f..e6a73deaf83a 100644 --- a/cranelift/codegen/src/nan_canonicalization.rs +++ b/cranelift/codegen/src/nan_canonicalization.rs @@ -124,4 +124,3 @@ fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst, has_vector_support: bool) pos.prev_inst(); // Step backwards so the pass does not skip instructions. } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 9253b690a60d..3c9dd6693edf 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -367,4 +367,3 @@ impl<'a, 'b, 'c> generated_code::Context for IsleContext<'a, 'b, 'c> { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/div_const.rs b/cranelift/codegen/src/opts/div_const.rs index 4ef0163a2d8b..a88f0c6344f5 100644 --- a/cranelift/codegen/src/opts/div_const.rs +++ b/cranelift/codegen/src/opts/div_const.rs @@ -1212,4 +1212,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index 981d7fe27e43..5dd5950bdf86 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,8 +1,4 @@ pub use alloc::format; -pub use alloc::string::{String, ToString}; -pub use alloc::vec::Vec; +pub use alloc::string::ToString; pub use alloc::vec; -pub use alloc::slice; -pub use core::prelude::*; -pub use core::ops; \ No newline at end of file diff --git a/cranelift/codegen/src/print_errors.rs b/cranelift/codegen/src/print_errors.rs index 348497eeb96b..21a2767267e8 100644 --- a/cranelift/codegen/src/print_errors.rs +++ b/cranelift/codegen/src/print_errors.rs @@ -221,4 +221,3 @@ pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String { err.to_string() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ranges.rs b/cranelift/codegen/src/ranges.rs index 4ea817d64457..419dee83c08f 100644 --- a/cranelift/codegen/src/ranges.rs +++ b/cranelift/codegen/src/ranges.rs @@ -129,4 +129,3 @@ impl Ranges { self.reverse_index(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index a6b2712059f0..ae9f3ad6ed24 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -418,4 +418,3 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) n_consts ); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index 0f56d06772ed..c62572cd9958 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -109,4 +109,3 @@ impl<'a> core::fmt::Debug for CompileError<'a> { /// A convenient alias for a `Result` that uses `CompileError` as the error type. pub type CompileResult<'a, T> = Result>; -use crate::prelude::*; diff --git a/cranelift/codegen/src/scoped_hash_map.rs b/cranelift/codegen/src/scoped_hash_map.rs index 0835af1c4368..b599d36dc205 100644 --- a/cranelift/codegen/src/scoped_hash_map.rs +++ b/cranelift/codegen/src/scoped_hash_map.rs @@ -332,4 +332,3 @@ mod tests { assert_eq!(map.get(&NullCtx, &3), Some(&4)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index e6232e901a39..584d9239d0fa 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -89,4 +89,3 @@ where (&mut *self.container, &mut self.value) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index 0c02dcb790c8..a06c6001ef41 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -303,4 +303,3 @@ mod tests { assert_eq!(Pass::regalloc.to_string(), "Register allocation"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/traversals.rs b/cranelift/codegen/src/traversals.rs index 24e8feb38b61..db57036aacd6 100644 --- a/cranelift/codegen/src/traversals.rs +++ b/cranelift/codegen/src/traversals.rs @@ -277,4 +277,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/unreachable_code.rs b/cranelift/codegen/src/unreachable_code.rs index 7af5e6d7d33c..68d7bd33fdeb 100644 --- a/cranelift/codegen/src/unreachable_code.rs +++ b/cranelift/codegen/src/unreachable_code.rs @@ -71,4 +71,3 @@ pub fn eliminate_unreachable_code( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/value_label.rs b/cranelift/codegen/src/value_label.rs index f822e19437c8..65b3e7d1eac9 100644 --- a/cranelift/codegen/src/value_label.rs +++ b/cranelift/codegen/src/value_label.rs @@ -30,4 +30,3 @@ pub enum LabelValueLoc { /// Resulting map of Value labels and their ranges/locations. pub type ValueLabelsRanges = HashMap>; -use crate::prelude::*; From 3ca13bb0ae8225f0c909b9a79182ca935b0f07ee Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 00:16:09 +0100 Subject: [PATCH 10/61] update isle changes --- cranelift/isle/isle/isle_examples/link/borrows_main.rs | 3 +++ cranelift/isle/isle/isle_examples/link/iflets_main.rs | 3 +++ .../isle/isle/isle_examples/link/multi_constructor_main.rs | 3 +++ cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs | 3 +++ cranelift/isle/isle/isle_examples/link/test_main.rs | 3 +++ cranelift/isle/isle/isle_examples/run/iconst_main.rs | 3 +++ cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs | 3 +++ cranelift/isle/isle/src/codegen.rs | 3 +-- 8 files changed, 22 insertions(+), 2 deletions(-) diff --git a/cranelift/isle/isle/isle_examples/link/borrows_main.rs b/cranelift/isle/isle/isle_examples/link/borrows_main.rs index 9de7d4ddded8..eaff4d9f918e 100644 --- a/cranelift/isle/isle/isle_examples/link/borrows_main.rs +++ b/cranelift/isle/isle/isle_examples/link/borrows_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod borrows; #[derive(Clone)] diff --git a/cranelift/isle/isle/isle_examples/link/iflets_main.rs b/cranelift/isle/isle/isle_examples/link/iflets_main.rs index 4c5717cbf407..ee974818f991 100644 --- a/cranelift/isle/isle/isle_examples/link/iflets_main.rs +++ b/cranelift/isle/isle/isle_examples/link/iflets_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod iflets; struct Context; diff --git a/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs b/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs index 3c05532ce077..c7bd08fd5bd1 100644 --- a/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs +++ b/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod multi_constructor; use multi_constructor::{ContextIter, IntoContextIter}; diff --git a/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs b/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs index ebfa38e30fdf..0554dd582976 100644 --- a/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs +++ b/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod multi_extractor; use multi_extractor::{ContextIter, IntoContextIter}; diff --git a/cranelift/isle/isle/isle_examples/link/test_main.rs b/cranelift/isle/isle/isle_examples/link/test_main.rs index 733e2a20193b..87f633e2ec6f 100644 --- a/cranelift/isle/isle/isle_examples/link/test_main.rs +++ b/cranelift/isle/isle/isle_examples/link/test_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod test; struct Context; diff --git a/cranelift/isle/isle/isle_examples/run/iconst_main.rs b/cranelift/isle/isle/isle_examples/run/iconst_main.rs index d53edea43831..275054993780 100644 --- a/cranelift/isle/isle/isle_examples/run/iconst_main.rs +++ b/cranelift/isle/isle/isle_examples/run/iconst_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod iconst; struct Context; diff --git a/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs b/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs index 37ddb0bcc50b..ec57de3383e1 100644 --- a/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs +++ b/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod let_shadowing; struct Context; diff --git a/cranelift/isle/isle/src/codegen.rs b/cranelift/isle/isle/src/codegen.rs index e42ef1ae5a7c..78a8fee729e7 100644 --- a/cranelift/isle/isle/src/codegen.rs +++ b/cranelift/isle/isle/src/codegen.rs @@ -166,8 +166,7 @@ impl<'a> Codegen<'a> { } writeln!(code, "\nuse super::*; // Pulls in all external types.").unwrap(); - writeln!(code, "use alloc::vec::Vec;").unwrap(); - writeln!(code, "use core::{{marker::PhantomData, ops}};").unwrap(); + writeln!(code, "use core::marker::PhantomData;").unwrap(); } fn generate_trait_sig(&self, code: &mut String, indent: &str, sig: &ExternalSig) { From cfb750112a025bd642945ced0cbb147e1f91247a Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 00:16:50 +0100 Subject: [PATCH 11/61] update assembler changes --- cranelift/assembler-x64/Cargo.toml | 1 - cranelift/assembler-x64/src/api.rs | 3 ++- cranelift/assembler-x64/src/custom.rs | 2 +- cranelift/assembler-x64/src/fuzz.rs | 4 ++++ cranelift/assembler-x64/src/imm.rs | 4 +--- cranelift/assembler-x64/src/inst.rs | 1 - cranelift/assembler-x64/src/lib.rs | 4 +++- cranelift/assembler-x64/src/main.rs | 12 ------------ cranelift/assembler-x64/src/mem.rs | 5 ++--- cranelift/assembler-x64/src/xmm.rs | 2 -- 10 files changed, 13 insertions(+), 25 deletions(-) diff --git a/cranelift/assembler-x64/Cargo.toml b/cranelift/assembler-x64/Cargo.toml index 424d26f206ce..6935ec669950 100644 --- a/cranelift/assembler-x64/Cargo.toml +++ b/cranelift/assembler-x64/Cargo.toml @@ -23,4 +23,3 @@ workspace = true [features] fuzz = ['dep:arbitrary', 'dep:capstone'] -core = [] diff --git a/cranelift/assembler-x64/src/api.rs b/cranelift/assembler-x64/src/api.rs index f65cfc338045..f861b7726822 100644 --- a/cranelift/assembler-x64/src/api.rs +++ b/cranelift/assembler-x64/src/api.rs @@ -3,10 +3,11 @@ use crate::gpr; use crate::xmm; use crate::{Amode, DeferredTarget, GprMem, XmmMem}; +use alloc::string::String; use alloc::vec::Vec; use core::fmt; use core::num::NonZeroU8; -use alloc::string::String; + /// Describe how an instruction is emitted into a code buffer. pub trait CodeSink { /// Add 1 byte to the code section. diff --git a/cranelift/assembler-x64/src/custom.rs b/cranelift/assembler-x64/src/custom.rs index c2b70fecbc24..25c63e239cf4 100644 --- a/cranelift/assembler-x64/src/custom.rs +++ b/cranelift/assembler-x64/src/custom.rs @@ -191,8 +191,8 @@ pub mod mnemonic { pub mod display { use crate::inst; use crate::{Amode, Gpr, GprMem, Registers, Size}; - use core::fmt; use alloc::string::ToString; + use core::fmt; pub fn callq_d(f: &mut fmt::Formatter, inst: &inst::callq_d) -> fmt::Result { let inst::callq_d { imm32 } = inst; diff --git a/cranelift/assembler-x64/src/fuzz.rs b/cranelift/assembler-x64/src/fuzz.rs index 9bbcaf83509f..290d888f5a00 100644 --- a/cranelift/assembler-x64/src/fuzz.rs +++ b/cranelift/assembler-x64/src/fuzz.rs @@ -4,6 +4,10 @@ //! throughout this crate to avoid depending on the `arbitrary` crate //! unconditionally (use the `fuzz` feature instead). +use std::string::{String, ToString}; +use std::vec::Vec; +use std::{format, println}; + use crate::{ AmodeOffset, AmodeOffsetPlusKnownOffset, AsReg, CodeSink, DeferredTarget, Fixed, Gpr, Inst, KnownOffset, NonRspGpr, Registers, TrapCode, Xmm, diff --git a/cranelift/assembler-x64/src/imm.rs b/cranelift/assembler-x64/src/imm.rs index 0c129cd65d45..f350952dd23f 100644 --- a/cranelift/assembler-x64/src/imm.rs +++ b/cranelift/assembler-x64/src/imm.rs @@ -1,10 +1,8 @@ //! Immediate operands to instructions. use crate::api::CodeSink; -use core::fmt; - -#[cfg(feature = "core")] use alloc::{format, string::String}; +use core::fmt; /// This helper function prints the unsigned hexadecimal representation of the /// immediate value: e.g., this prints `$0xfe` to represent both the signed `-2` diff --git a/cranelift/assembler-x64/src/inst.rs b/cranelift/assembler-x64/src/inst.rs index e4f23849cd12..c9073401b040 100644 --- a/cranelift/assembler-x64/src/inst.rs +++ b/cranelift/assembler-x64/src/inst.rs @@ -16,7 +16,6 @@ use crate::xmm::{self, Xmm}; use alloc::string::ToString; - // Include code generated by the `meta` crate. include!(concat!(env!("OUT_DIR"), "/assembler.rs")); diff --git a/cranelift/assembler-x64/src/lib.rs b/cranelift/assembler-x64/src/lib.rs index d28e102ffeb7..bf781a50de44 100644 --- a/cranelift/assembler-x64/src/lib.rs +++ b/cranelift/assembler-x64/src/lib.rs @@ -41,8 +41,10 @@ non_camel_case_types, reason = "all of the generated struct names use snake case" )] -#![cfg_attr(feature = "core", no_std)] +#![no_std] extern crate alloc; +#[cfg(any(test, feature = "fuzz"))] +extern crate std; mod api; mod custom; diff --git a/cranelift/assembler-x64/src/main.rs b/cranelift/assembler-x64/src/main.rs index 4361d85624f9..31ae7a7d55c5 100644 --- a/cranelift/assembler-x64/src/main.rs +++ b/cranelift/assembler-x64/src/main.rs @@ -1,19 +1,7 @@ //! Print the path to the generated code. -#![cfg_attr(feature = "core", no_std)] - -#[cfg(not(feature = "core"))] fn main() { let paths: Vec = include!(concat!(env!("OUT_DIR"), "/generated-files.rs")); for path in paths { println!("{}", path.display()); } } - -#[cfg(feature = "core")] -fn main() {} - -#[cfg(feature = "core")] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} \ No newline at end of file diff --git a/cranelift/assembler-x64/src/mem.rs b/cranelift/assembler-x64/src/mem.rs index cffecf9bf18b..8235f9b5bfa9 100644 --- a/cranelift/assembler-x64/src/mem.rs +++ b/cranelift/assembler-x64/src/mem.rs @@ -1,12 +1,11 @@ //! Memory operands to instructions. +use alloc::string::{String, ToString}; + use crate::api::{AsReg, CodeSink, Constant, KnownOffset, Label, TrapCode}; use crate::gpr::{self, NonRspGpr, Size}; use crate::rex::{Disp, RexPrefix, encode_modrm, encode_sib}; -#[cfg(feature = "core")] -use alloc::string::{String, ToString}; - /// x64 memory addressing modes. #[derive(Copy, Clone, Debug, PartialEq)] #[cfg_attr(any(test, feature = "fuzz"), derive(arbitrary::Arbitrary))] diff --git a/cranelift/assembler-x64/src/xmm.rs b/cranelift/assembler-x64/src/xmm.rs index 636c887afbc7..d016e270b8e9 100644 --- a/cranelift/assembler-x64/src/xmm.rs +++ b/cranelift/assembler-x64/src/xmm.rs @@ -2,9 +2,7 @@ use crate::{AsReg, CodeSink, rex::encode_modrm}; -#[cfg(feature = "core")] use alloc::string::String; -//use core::convert::{AsMut, AsRef, From}; /// An x64 SSE register (e.g., `%xmm0`). #[derive(Clone, Copy, Debug)] From 339093c3e679961b14a2f8d80cace469f19b724d Mon Sep 17 00:00:00 2001 From: SSD <96286755+the-ssd@users.noreply.github.com> Date: Fri, 2 Jan 2026 00:18:23 +0100 Subject: [PATCH 12/61] update assembler changes --- .github/workflows/main.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 592cea2b3635..39e6898c6b38 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,7 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && - cargo check -p cranelift-assembler-x64 --no-default-features -F core && + cargo check -p cranelift-assembler-x64 && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. From 4e3c723f899d7030142f979067ab85f1f7736956 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 08:25:44 +0100 Subject: [PATCH 13/61] use latest codegen changes + fix FxHash problem --- .github/workflows/main.yml | 2 +- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/alias_analysis.rs | 3 +-- cranelift/codegen/src/ctxhash.rs | 2 +- cranelift/codegen/src/data_value.rs | 1 - cranelift/codegen/src/dominator_tree.rs | 1 - cranelift/codegen/src/egraph.rs | 3 +-- cranelift/codegen/src/egraph/elaborate.rs | 3 +-- cranelift/codegen/src/incremental_cache.rs | 1 - cranelift/codegen/src/inline.rs | 1 - cranelift/codegen/src/ir/debug_tags.rs | 1 - cranelift/codegen/src/ir/entities.rs | 1 - cranelift/codegen/src/ir/exception_table.rs | 1 - cranelift/codegen/src/ir/immediates.rs | 2 -- cranelift/codegen/src/ir/layout.rs | 1 - cranelift/codegen/src/ir/pcc.rs | 2 +- cranelift/codegen/src/ir/stackslot.rs | 1 - cranelift/codegen/src/ir/trapcode.rs | 1 - cranelift/codegen/src/ir/types.rs | 1 - cranelift/codegen/src/isa/aarch64/abi.rs | 3 +-- cranelift/codegen/src/isa/aarch64/inst/args.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/emit.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs | 3 +-- cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/mod.rs | 5 ++--- cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/unwind.rs | 1 - .../codegen/src/isa/aarch64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/aarch64/lower.rs | 1 - cranelift/codegen/src/isa/aarch64/lower/isle.rs | 5 ++--- .../src/isa/aarch64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/aarch64/mod.rs | 3 +-- cranelift/codegen/src/isa/aarch64/pcc.rs | 1 - cranelift/codegen/src/isa/aarch64/settings.rs | 1 - cranelift/codegen/src/isa/mod.rs | 3 +-- cranelift/codegen/src/isa/pulley32.rs | 1 - cranelift/codegen/src/isa/pulley64.rs | 1 - cranelift/codegen/src/isa/pulley_shared/abi.rs | 3 +-- cranelift/codegen/src/isa/pulley_shared/inst/args.rs | 3 +-- cranelift/codegen/src/isa/pulley_shared/inst/emit.rs | 1 - cranelift/codegen/src/isa/pulley_shared/inst/mod.rs | 1 - cranelift/codegen/src/isa/pulley_shared/inst/regs.rs | 1 - cranelift/codegen/src/isa/pulley_shared/lower.rs | 1 - cranelift/codegen/src/isa/pulley_shared/lower/isle.rs | 1 - .../isa/pulley_shared/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/pulley_shared/mod.rs | 3 +-- cranelift/codegen/src/isa/pulley_shared/settings.rs | 1 - cranelift/codegen/src/isa/riscv64/abi.rs | 3 +-- cranelift/codegen/src/isa/riscv64/inst/args.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/emit.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/encode.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/imms.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/mod.rs | 7 +++---- cranelift/codegen/src/isa/riscv64/inst/regs.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/unwind.rs | 1 - .../codegen/src/isa/riscv64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 - cranelift/codegen/src/isa/riscv64/lower.rs | 1 - cranelift/codegen/src/isa/riscv64/lower/isle.rs | 3 +-- .../src/isa/riscv64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/riscv64/mod.rs | 3 +-- cranelift/codegen/src/isa/riscv64/settings.rs | 1 - cranelift/codegen/src/isa/s390x/abi.rs | 3 +-- cranelift/codegen/src/isa/s390x/inst/args.rs | 1 - cranelift/codegen/src/isa/s390x/inst/emit.rs | 1 - cranelift/codegen/src/isa/s390x/inst/emit_tests.rs | 1 - cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 - cranelift/codegen/src/isa/s390x/inst/mod.rs | 5 ++--- cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 - cranelift/codegen/src/isa/s390x/inst/unwind.rs | 1 - .../codegen/src/isa/s390x/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/s390x/lower.rs | 1 - cranelift/codegen/src/isa/s390x/lower/isle.rs | 5 ++--- .../src/isa/s390x/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/s390x/mod.rs | 3 +-- cranelift/codegen/src/isa/s390x/settings.rs | 1 - cranelift/codegen/src/isa/unwind.rs | 1 - cranelift/codegen/src/isa/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/unwind/winarm64.rs | 1 - cranelift/codegen/src/isa/unwind/winx64.rs | 1 - cranelift/codegen/src/isa/x64/abi.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/args.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/external.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/mod.rs | 5 ++--- cranelift/codegen/src/isa/x64/inst/regs.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs | 1 - cranelift/codegen/src/isa/x64/lower/isle.rs | 1 - .../codegen/src/isa/x64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 3 +-- cranelift/codegen/src/lib.rs | 11 +++++++---- cranelift/codegen/src/machinst/abi.rs | 5 ++--- cranelift/codegen/src/machinst/blockorder.rs | 2 +- cranelift/codegen/src/machinst/buffer.rs | 11 +++++------ cranelift/codegen/src/machinst/inst_common.rs | 1 - cranelift/codegen/src/machinst/lower.rs | 9 ++++----- cranelift/codegen/src/machinst/mod.rs | 2 +- cranelift/codegen/src/machinst/reg.rs | 1 - cranelift/codegen/src/machinst/vcode.rs | 4 +--- cranelift/codegen/src/opts.rs | 2 +- cranelift/codegen/src/opts/generated_code.rs | 1 - cranelift/codegen/src/remove_constant_phis.rs | 2 +- cranelift/codegen/src/settings.rs | 1 - cranelift/codegen/src/souper_harvest.rs | 1 - cranelift/codegen/src/verifier/mod.rs | 1 - cranelift/codegen/src/write.rs | 1 - 108 files changed, 61 insertions(+), 159 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 39e6898c6b38..fe35d822d676 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,7 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && - cargo check -p cranelift-assembler-x64 && + cargo check -p cranelift-assembler-x64 --lib && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 03040f037d3c..9376b79ddd2c 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -71,7 +71,7 @@ std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # deprecated (we (i) always use hashbrown, and (ii) don't support a # no_std build anymore). The feature remains for backward # compatibility as a no-op. -core = ["cranelift-assembler-x64/core"] +core = [] # Enable the `to_capstone` method on TargetIsa, for constructing a Capstone # context, and the `disassemble` method on `MachBufferFinalized`. diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index b915db0f79e7..eecb38096d1b 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,6 +61,7 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. +use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, dominator_tree::DominatorTree, @@ -71,7 +72,6 @@ use crate::{ trace, }; use cranelift_entity::{EntityRef, packed_option::PackedOption}; -use rustc_hash::{FxHashMap, FxHashSet}; /// For a given program point, the vector of last-store instruction /// indices for each disjoint category of abstract state. @@ -400,4 +400,3 @@ fn get_ext_opcode(op: Opcode) -> Option { _ => Some(op), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 10fe7af5b032..ea7de766006e 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -4,8 +4,8 @@ //! node-internal data references some other storage (e.g., offsets into //! an array or pool of shared data). -use hashbrown::hash_table::HashTable; use core::hash::{Hash, Hasher}; +use hashbrown::hash_table::HashTable; /// Trait that allows for equality comparison given some external /// context. diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index 26a66d53694e..a2e69a724e1b 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -420,4 +420,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 90e700d0097d..23d099a4251a 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -771,4 +771,3 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph.rs index a8d6a80ee3b2..280109470d01 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph.rs @@ -1,5 +1,6 @@ //! Support for egraphs represented in the DataFlowGraph. +use crate::FxHashSet; use crate::alias_analysis::{AliasAnalysis, LastStores}; use crate::ctxhash::{CtxEq, CtxHash, NullCtx}; use crate::cursor::{Cursor, CursorPosition, FuncCursor}; @@ -24,7 +25,6 @@ use core::hash::Hasher; use cranelift_control::ControlPlane; use cranelift_entity::SecondaryMap; use cranelift_entity::packed_option::ReservedValue; -use rustc_hash::FxHashSet; use smallvec::SmallVec; mod cost; @@ -1110,4 +1110,3 @@ pub(crate) struct Stats { pub(crate) elaborate_func_post_insts: u64, pub(crate) eclass_size_limit: u64, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index ec617344b9ba..86443e5cb126 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -11,10 +11,10 @@ use crate::ir::{Block, Function, Inst, Value, ValueDef}; use crate::loop_analysis::{Loop, LoopAnalysis}; use crate::scoped_hash_map::ScopedHashMap; use crate::trace; +use crate::{FxHashMap, FxHashSet}; use alloc::vec::Vec; use cranelift_control::ControlPlane; use cranelift_entity::{EntitySet, SecondaryMap, packed_option::ReservedValue}; -use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; pub(crate) struct Elaborator<'a> { @@ -865,4 +865,3 @@ impl<'a> Elaborator<'a> { self.stats.elaborate_func_post_insts += self.func.dfg.num_insts() as u64; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index 973cca13ece1..a597d18869ce 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -239,4 +239,3 @@ pub fn try_finish_recompile(func: &Function, bytes: &[u8]) -> Result Err(RecompileError::Deserialize(err)), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/inline.rs b/cranelift/codegen/src/inline.rs index 6e6756871545..ac150c598980 100644 --- a/cranelift/codegen/src/inline.rs +++ b/cranelift/codegen/src/inline.rs @@ -1584,4 +1584,3 @@ fn create_constants(allocs: &mut InliningAllocs, func: &mut ir::Function, callee allocs.constants[*callee_constant] = Some(inlined_constant).into(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/debug_tags.rs b/cranelift/codegen/src/ir/debug_tags.rs index d2ca049f6c53..39d137c2973b 100644 --- a/cranelift/codegen/src/ir/debug_tags.rs +++ b/cranelift/codegen/src/ir/debug_tags.rs @@ -139,4 +139,3 @@ impl core::fmt::Display for DebugTag { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/entities.rs b/cranelift/codegen/src/ir/entities.rs index a1ab10662d7d..cbb8f3097aff 100644 --- a/cranelift/codegen/src/ir/entities.rs +++ b/cranelift/codegen/src/ir/entities.rs @@ -562,4 +562,3 @@ mod tests { assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 80730652054a..4130f23792b4 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -287,4 +287,3 @@ impl<'a> Display for DisplayExceptionTable<'a> { Ok(()) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index ce89abd2307d..79b9432960af 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1,4 +1,3 @@ - //! Immediate operands for Cranelift instructions //! //! This module defines the types of immediate operands that can appear on Cranelift instructions. @@ -1959,4 +1958,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/layout.rs b/cranelift/codegen/src/ir/layout.rs index 2a2d139018fe..1284ab65676e 100644 --- a/cranelift/codegen/src/ir/layout.rs +++ b/cranelift/codegen/src/ir/layout.rs @@ -1193,4 +1193,3 @@ mod tests { assert_eq!(layout.pp_cmp(i3, i2), Ordering::Greater) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index b10f43f78d06..8b9a3cc6bb6e 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -77,8 +77,8 @@ use crate::ir::types::*; use crate::isa::TargetIsa; use crate::machinst::{BlockIndex, LowerBackend, VCode}; use crate::trace; -use regalloc2::Function as _; use core::fmt; +use regalloc2::Function as _; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 3c10fdc98026..1ad2a5d7d871 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -249,4 +249,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/trapcode.rs b/cranelift/codegen/src/ir/trapcode.rs index f990f312b94f..e3fbcfbb4a50 100644 --- a/cranelift/codegen/src/ir/trapcode.rs +++ b/cranelift/codegen/src/ir/trapcode.rs @@ -145,4 +145,3 @@ mod tests { assert_eq!("users".parse::(), Err(())); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs index 48e98fd352d2..bc7704cf0662 100644 --- a/cranelift/codegen/src/ir/types.rs +++ b/cranelift/codegen/src/ir/types.rs @@ -622,4 +622,3 @@ mod tests { assert_eq!(Type::int_with_byte_size(evil), None); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 875afdc85f3c..8f1afce63a87 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -12,11 +12,11 @@ use crate::isa::unwind::UnwindInst; use crate::isa::winch; use crate::machinst::*; use crate::settings; +use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because @@ -1632,4 +1632,3 @@ fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv { env } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index d912aee4dd79..a382a5ef725a 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -724,4 +724,3 @@ impl TestBitAndBranchKind { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index b5bb377591df..06e0eb017708 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -3685,4 +3685,3 @@ fn emit_return_call_common_sequence( sink.put4(key.enc_auti_hint()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index fdca784dd038..d8e6cd6a2083 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -27,7 +27,7 @@ fn test_aarch64_binemit() { // // #!/bin/sh // tmp=`mktemp /tmp/XXXXXXXX.o` - // aarch64-linux-gnu-as /dev/corein -o $tmp + // aarch64-linux-gnu-as /dev/stdin -o $tmp // aarch64-linux-gnu-objdump -d $tmp // rm -f $tmp // @@ -7970,4 +7970,3 @@ fn test_cond_invert() { assert_eq!(cond.invert().invert(), cond); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index 69a1ca5312e7..fcd67deed576 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -1240,4 +1240,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index e8308a425840..90ba2ef0c75d 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -9,11 +9,11 @@ use crate::{CodegenError, CodegenResult, settings}; use crate::machinst::{PrettyPrint, Reg, RegClass, Writable}; +use alloc::string::{String, ToString}; use alloc::vec::Vec; +use core::fmt::Write; use core::slice; use smallvec::{SmallVec, smallvec}; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub(crate) mod regs; pub(crate) use self::regs::*; @@ -3112,4 +3112,3 @@ mod tests { assert_eq!(expected, core::mem::size_of::()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index c625d99d964d..7db69df4ebe4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -279,4 +279,3 @@ pub fn pretty_print_vreg_vector(reg: Reg, size: VectorSize) -> String { pub fn pretty_print_vreg_element(reg: Reg, idx: usize, size: ScalarSize) -> String { show_vreg_element(reg, idx as u8, size) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs index 25a095983c42..9378c46fa53b 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs @@ -175,4 +175,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs index 99c9f2f95592..6d51a380433f 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.rs +++ b/cranelift/codegen/src/isa/aarch64/lower.rs @@ -143,4 +143,3 @@ impl LowerBackend for AArch64Backend { type FactFlowState = pcc::FactFlowState; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 91ee0718b776..3e82af2a9c8e 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -31,10 +31,10 @@ use crate::{ abi::ArgPair, ty_bits, }, }; -use core::u32; -use regalloc2::PReg; use alloc::boxed::Box; use alloc::vec::Vec; +use core::u32; +use regalloc2::PReg; type BoxCallInfo = Box>; type BoxCallIndInfo = Box>; @@ -858,4 +858,3 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.backend.flags.is_pic() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 3867a060b7f3..2e0f7bd77dda 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -14,4 +14,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_aarch64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 40bb5d9aa966..2f80ad9fa29b 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -12,10 +12,10 @@ use crate::machinst::{ }; use crate::result::CodegenResult; use crate::settings as shared_settings; +use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Aarch64Architecture, Architecture, OperatingSystem, Triple}; // New backend: @@ -278,4 +278,3 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs index 3b5e31d11c0e..e5ee1919803e 100644 --- a/cranelift/codegen/src/isa/aarch64/pcc.rs +++ b/cranelift/codegen/src/isa/aarch64/pcc.rs @@ -568,4 +568,3 @@ fn check_store_addr( let _output_fact = ctx.store(&fact, ty, None)?; Ok(()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/settings.rs b/cranelift/codegen/src/isa/aarch64/settings.rs index 21031399b5eb..2cda69446ff3 100644 --- a/cranelift/codegen/src/isa/aarch64/settings.rs +++ b/cranelift/codegen/src/isa/aarch64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/arm64.rs`. include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2c44409de892..2bc2033983ef 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -50,7 +50,7 @@ use crate::CodegenResult; use crate::ir::{self, Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::{UnwindInfoKind, systemv::RegisterMappingError}; -use crate::machinst::{CompiledCodeStencil, TextSectionBuilder}; +use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder}; use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; @@ -499,4 +499,3 @@ impl Debug for &dyn TargetIsa { ) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley32.rs b/cranelift/codegen/src/isa/pulley32.rs index e3467275472e..b337274660d0 100644 --- a/cranelift/codegen/src/isa/pulley32.rs +++ b/cranelift/codegen/src/isa/pulley32.rs @@ -11,4 +11,3 @@ impl PulleyTargetKind for Pulley32 { PointerWidth::PointerWidth32 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley64.rs b/cranelift/codegen/src/isa/pulley64.rs index 234840c45eb5..31b1d08a04b2 100644 --- a/cranelift/codegen/src/isa/pulley64.rs +++ b/cranelift/codegen/src/isa/pulley64.rs @@ -11,4 +11,3 @@ impl PulleyTargetKind for Pulley64 { PointerWidth::PointerWidth64 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 05952c94a4ab..de32099a14a7 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -9,12 +9,12 @@ use crate::{ machinst::*, settings, }; +use alloc::borrow::ToOwned; use alloc::vec::Vec; use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). @@ -985,4 +985,3 @@ fn create_reg_environment() -> MachineEnv { scratch_by_class: [None, None, None], } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index 43d1e8a82a82..e97e3303ef99 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -3,9 +3,9 @@ use super::*; use crate::ir::ExternalName; use crate::machinst::abi::StackAMode; +use core::fmt; use pulley_interpreter::encode; use pulley_interpreter::regs::Reg as _; -use core::fmt; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). @@ -779,4 +779,3 @@ impl fmt::Display for AddrG32Bne { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs index 25614218b03b..74082b4260c3 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs @@ -707,4 +707,3 @@ fn patch_pc_rel_offset

( assert_eq!(*chunk, [0, 0, 0, 0]); *chunk = (end - start - 4).to_le_bytes(); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index 497ba5e2031e..d76705a7fb9f 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -952,4 +952,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs index 069050e7cd55..90f7d36e104b 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs @@ -162,4 +162,3 @@ define_registers! { v_reg(30) => v30, writable_v30; v_reg(31) => v31, writable_v31; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.rs b/cranelift/codegen/src/isa/pulley_shared/lower.rs index b436d1d3e46e..8dd5a0cea50c 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower.rs @@ -34,4 +34,3 @@ where type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs index baa93a5eb1bc..d72b6a023789 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs @@ -327,4 +327,3 @@ where let mut isle_ctx = PulleyIsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs index 6b0853db8f25..45dd7050dc3c 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_pulley_shared.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index f86782a0a2e9..0b781e467a08 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -17,11 +17,11 @@ use crate::{ settings::{self as shared_settings, Flags}, }; use alloc::boxed::Box; +use alloc::string::String; use alloc::vec::Vec; use core::fmt::Debug; use core::marker::PhantomData; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; pub use settings::Flags as PulleyFlags; @@ -312,4 +312,3 @@ impl PulleyFlags { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/settings.rs b/cranelift/codegen/src/isa/pulley_shared/settings.rs index d611e3a6f2a5..5d4fd19ed116 100644 --- a/cranelift/codegen/src/isa/pulley_shared/settings.rs +++ b/cranelift/codegen/src/isa/pulley_shared/settings.rs @@ -14,4 +14,3 @@ use core::fmt; include!(concat!(env!("OUT_DIR"), "/settings-pulley.rs")); impl IsaFlags for Flags {} -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index d373057ec6fa..f53eee9a53a0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -19,8 +19,8 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; -use smallvec::{SmallVec, smallvec}; use alloc::borrow::ToOwned; +use smallvec::{SmallVec, smallvec}; use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). @@ -1055,4 +1055,3 @@ impl Riscv64MachineDeps { insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index d710f4348e46..918a4854b3a3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -1946,4 +1946,3 @@ impl ZcbMemOp { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 714271546539..5e631c3af1d3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -2885,4 +2885,3 @@ fn return_call_emit_impl( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 09880464c68e..3b0cf59b633f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -2283,4 +2283,3 @@ fn riscv64_worst_case_instruction_size() { println!("calculate max size is {} , inst is {:?}", max.0, max.1); assert!(max.0 <= Inst::worst_case_size()); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/encode.rs b/cranelift/codegen/src/isa/riscv64/inst/encode.rs index b167f319ccfe..048fc2af05b5 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs @@ -718,4 +718,3 @@ pub fn encode_fp_rrrr( funct7, ) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 5e9f0faeee45..92a8ceb60b83 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -371,4 +371,3 @@ mod test { assert!(Inst::imm_min() == i32::MIN as i64 - 2048); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index dc41e455c3c3..9349d64cd08f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -12,12 +12,12 @@ use crate::{CodegenError, CodegenResult, settings}; pub use crate::ir::condcodes::FloatCC; +use alloc::boxed::Box; +use alloc::string::{String, ToString}; use alloc::vec::Vec; +use core::fmt::Write; use regalloc2::RegClass; use smallvec::{SmallVec, smallvec}; -use alloc::boxed::Box; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; @@ -1940,4 +1940,3 @@ mod test { assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/regs.rs b/cranelift/codegen/src/isa/riscv64/inst/regs.rs index d1e9fa7cd00f..76493732bfe1 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/regs.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/regs.rs @@ -151,4 +151,3 @@ pub const fn pf_reg(enc: usize) -> PReg { pub const fn pv_reg(enc: usize) -> PReg { PReg::new(enc, RegClass::Vector) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs index 0edc32ba221f..0b2ef040b19c 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs @@ -171,4 +171,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index dcbda4aa1850..269e6481b506 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -1148,4 +1148,3 @@ pub trait VecInstOverlapInfo { self.forbids_src_dst_overlaps() || (mask.is_enabled() && self.forbids_mask_dst_overlaps()) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower.rs b/cranelift/codegen/src/isa/riscv64/lower.rs index 8de92855b2f8..117778f820b3 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.rs +++ b/cranelift/codegen/src/isa/riscv64/lower.rs @@ -33,4 +33,3 @@ impl LowerBackend for Riscv64Backend { type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index 81d0e2061b54..a2a7d0c196e6 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -21,9 +21,9 @@ use crate::{ isa::riscv64::inst::*, machinst::{ArgPair, CallArgList, CallRetList, InstOutput}, }; -use regalloc2::PReg; use alloc::boxed::Box; use alloc::vec::Vec; +use regalloc2::PReg; use wasmtime_math::{f32_cvt_to_int_bounds, f64_cvt_to_int_bounds}; type BoxCallInfo = Box>; @@ -749,4 +749,3 @@ pub(crate) fn lower_branch( let mut isle_ctx = RV64IsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs index 9fb78bfb80ca..ad8466108a3b 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_riscv64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 6a50953d6750..ca0a1a13e2e9 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -13,10 +13,10 @@ use crate::machinst::{ use crate::result::CodegenResult; use crate::settings::{self as shared_settings, Flags}; use crate::{CodegenError, ir}; +use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; mod abi; pub(crate) mod inst; @@ -292,4 +292,3 @@ fn isa_constructor( let backend = Riscv64Backend::new_with_flags(triple, shared_flags, isa_flags); Ok(backend.wrapped()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/settings.rs b/cranelift/codegen/src/isa/riscv64/settings.rs index f4ca3fb3a88a..c896dd5fe911 100644 --- a/cranelift/codegen/src/isa/riscv64/settings.rs +++ b/cranelift/codegen/src/isa/riscv64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/riscv64/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-riscv64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 02658acfc0f5..738e037047d3 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -144,10 +144,10 @@ use crate::isa::s390x::{inst::*, settings as s390x_settings}; use crate::isa::unwind::UnwindInst; use crate::machinst::*; use crate::settings; +use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -1627,4 +1627,3 @@ fn tail_create_machine_env() -> MachineEnv { scratch_by_class: [None, None, None], } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/args.rs b/cranelift/codegen/src/isa/s390x/inst/args.rs index 5e114104b320..33e790673b61 100644 --- a/cranelift/codegen/src/isa/s390x/inst/args.rs +++ b/cranelift/codegen/src/isa/s390x/inst/args.rs @@ -269,4 +269,3 @@ impl PrettyPrint for Cond { s.to_string() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index e218fe55454a..5baef0fede8a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3559,4 +3559,3 @@ impl Inst { state.clear_post_insn(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index 9f5afa33448e..aa6f9e6b19c9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -13496,4 +13496,3 @@ fn test_s390x_binemit() { assert_eq!(expected_encoding, actual_encoding); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index edb66ba08196..9559f34ac7f8 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -200,4 +200,3 @@ impl PrettyPrint for UImm32Shifted { format!("{}", self.bits) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 766730533764..762f6c58d27e 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -7,10 +7,10 @@ use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; use crate::{CodegenError, CodegenResult, settings}; use alloc::boxed::Box; +use alloc::string::{String, ToString}; use alloc::vec::Vec; -use smallvec::SmallVec; use core::fmt::Write; -use alloc::string::{String, ToString}; +use smallvec::SmallVec; pub mod regs; pub use self::regs::*; pub mod imms; @@ -3550,4 +3550,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index eebcb36a33df..d3985bb9d20b 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -184,4 +184,3 @@ pub fn pretty_print_regpair_mod_lo(rd: WritableRegPair, ri: Reg) -> String { pub fn pretty_print_fpr(reg: Reg) -> (String, Option) { (show_reg(reg), maybe_show_fpr(reg)) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind.rs b/cranelift/codegen/src/isa/s390x/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs index a37ca84767d9..6ae2c7e262d9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs @@ -216,4 +216,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index c111eee9c915..9af0b96147e5 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -28,4 +28,3 @@ impl LowerBackend for S390xBackend { type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index e93358b1a972..561fabd9561e 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -23,10 +23,10 @@ use crate::{ ArgPair, CallArgList, CallRetList, InstOutput, MachInst, VCodeConstant, VCodeConstantData, }, }; -use regalloc2::PReg; use alloc::boxed::Box; -use core::cell::Cell; use alloc::vec::Vec; +use core::cell::Cell; +use regalloc2::PReg; type BoxCallInfo = Box>; type BoxReturnCallInfo = Box>; @@ -859,4 +859,3 @@ fn condcode_is_signed(cc: IntCC) -> bool { IntCC::UnsignedLessThan => false, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index c32fdefdc440..a6daad546b62 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_s390x.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 8393768c442a..6bc40484153d 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -12,10 +12,10 @@ use crate::machinst::{ }; use crate::result::CodegenResult; use crate::settings as shared_settings; +use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; // New backend: @@ -236,4 +236,3 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/settings.rs b/cranelift/codegen/src/isa/s390x/settings.rs index 16a717f9e7c7..5bf89030f19d 100644 --- a/cranelift/codegen/src/isa/s390x/settings.rs +++ b/cranelift/codegen/src/isa/s390x/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/s390x/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index 7b842ac7e4ab..ada37b03ccbb 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -15,7 +15,6 @@ pub mod winx64; pub mod winarm64; /// CFA-based unwind information used on SystemV. -#[cfg(feature = "unwind")] pub type CfaUnwindInfo = systemv::UnwindInfo; /// Expected unwind info type. diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index 0fb19d0408c7..5989e0b2a12b 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -286,4 +286,3 @@ impl UnwindInfo { fde } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winarm64.rs b/cranelift/codegen/src/isa/unwind/winarm64.rs index 803867af2a85..3d3cdd8fcf48 100644 --- a/cranelift/codegen/src/isa/unwind/winarm64.rs +++ b/cranelift/codegen/src/isa/unwind/winarm64.rs @@ -315,4 +315,3 @@ pub(crate) fn create_unwind_info_from_insts( Ok(UnwindInfo { unwind_codes }) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winx64.rs b/cranelift/codegen/src/isa/unwind/winx64.rs index e352dc6351df..38cb46b83b55 100644 --- a/cranelift/codegen/src/isa/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/unwind/winx64.rs @@ -310,4 +310,3 @@ fn ensure_unwind_offset(offset: u32) -> CodegenResult { } Ok(offset as u8) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index e00689769b40..b3a8dfed44a0 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -13,10 +13,10 @@ use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use args::*; -use std::sync::OnceLock; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -1346,4 +1346,3 @@ fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv { env } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index c5e6a117ec04..233299966a16 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,8 +7,8 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use core::fmt; use alloc::string::String; +use core::fmt; /// An extension trait for converting `Writable{Xmm,Gpr}` to `Writable`. pub trait ToWritableReg { @@ -1061,4 +1061,3 @@ impl OperandSize { self.to_bytes() * 8 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 7d9e7a6e7eba..1bd8b0f6b28e 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -2,7 +2,7 @@ //! //! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases. //! -//! to see coreout: cargo test -- --nocapture +//! to see stdout: cargo test -- --nocapture //! //! for this specific case, as of 24 Aug 2020: //! @@ -383,4 +383,3 @@ fn test_x64_emit() { assert_eq!(expected_encoding, actual_encoding, "{expected_printing}"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 0229c5ed42c9..8d41f2e6d484 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -5,9 +5,9 @@ use super::{ SyntheticAmode, VCodeConstant, WritableGpr, WritableXmm, Xmm, args::FromWritableReg, }; use crate::{Reg, Writable, ir::TrapCode}; +use alloc::string::String; use cranelift_assembler_x64 as asm; use regalloc2::{PReg, RegClass}; -use alloc::string::String; /// Define the types of registers Cranelift will use. #[derive(Clone, Debug)] @@ -562,4 +562,3 @@ mod tests { assert_eq!(pair.to_string(None), "(%v500 <- %v400)"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 0567b9554fb6..8bff031e3fc4 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -11,13 +11,13 @@ use crate::isa::{CallConv, FunctionAlignment}; use crate::{CodegenError, CodegenResult, settings}; use crate::{machinst::*, trace}; use alloc::boxed::Box; +use alloc::string::{String, ToString}; use alloc::vec; use alloc::vec::Vec; +use core::fmt::{self, Write}; use core::slice; use cranelift_assembler_x64 as asm; use smallvec::{SmallVec, smallvec}; -use core::fmt::{self, Write}; -use alloc::string::{String, ToString}; pub mod args; mod emit; @@ -1678,4 +1678,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 33cb94dfd060..b1416e88df5c 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,10 +6,10 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; +use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; use regalloc2::{PReg, RegClass, VReg}; -use alloc::string::String; // Constructors for Regs. @@ -174,4 +174,3 @@ pub fn pretty_print_reg(reg: Reg, size: u8) -> String { name } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs index ecbe379cd7da..3f46843ab4f4 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs @@ -202,4 +202,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs index f6d80f5e531f..f848a5baf76f 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs @@ -14,4 +14,3 @@ impl crate::isa::unwind::winx64::RegisterMapper for RegisterMapper { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 3917b4203ca5..57bfa06ee7fd 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -1249,4 +1249,3 @@ const I8X16_USHR_MASKS: [u8; 128] = [ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ]; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index 1bc434f23b5a..c48996ec46d6 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -14,4 +14,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_x64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index c67ccc5b654b..37a386504347 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -10,7 +10,7 @@ use crate::isa::unwind::systemv; use crate::isa::x64::settings as x64_settings; use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey}; use crate::machinst::{ - CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, + CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; use crate::result::{CodegenError, CodegenResult}; @@ -264,4 +264,3 @@ fn isa_constructor( let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags)?; Ok(backend.wrapped()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index fe017ca4468e..7e006e41014a 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -21,9 +21,14 @@ extern crate alloc; extern crate std; #[cfg(not(feature = "std"))] -use hashbrown::{HashMap, hash_map}; +use hashbrown::{HashMap, HashSet, hash_map}; #[cfg(feature = "std")] -use std::collections::{HashMap, hash_map}; +use std::collections::{HashMap, HashSet, hash_map}; + +/// Type alias for a hash map that uses the Fx hashing algorithm. +pub type FxHashMap = HashMap; +/// Type alias for a hash set that uses the Fx hashing algorithm. +pub type FxHashSet = HashSet; pub use crate::context::Context; pub use crate::value_label::{LabelValueLoc, ValueLabelsRanges, ValueLocRange}; @@ -43,8 +48,6 @@ include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); #[macro_use] mod machinst; -mod prelude; - pub mod binemit; pub mod cfg_printer; pub mod cursor; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index c98093d88bf5..08f275ccca76 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -99,6 +99,8 @@ //! ABI. See each platform's `abi.rs` implementation for details. use crate::CodegenError; +use crate::FxHashMap; +use crate::HashMap; use crate::entity::SecondaryMap; use crate::ir::{ArgumentExtension, ArgumentPurpose, ExceptionTag, Signature}; use crate::ir::{StackSlotKey, types::*}; @@ -108,9 +110,7 @@ use crate::{ir, isa}; use crate::{machinst::*, trace}; use alloc::boxed::Box; use core::marker::PhantomData; -use hashbrown::HashMap; use regalloc2::{MachineEnv, PReg, PRegSet}; -use rustc_hash::FxHashMap; use smallvec::smallvec; /// A small vector of instructions (with some reasonable size); appropriate for @@ -2615,4 +2615,3 @@ mod tests { assert_eq!(core::mem::size_of::(), 24); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 9e48e2c4d607..671426e600b2 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -64,8 +64,8 @@ use crate::dominator_tree::DominatorTree; use crate::entity::SecondaryMap; use crate::inst_predicates::visit_block_succs; use crate::ir::{Block, Function, Inst, Opcode}; +use crate::{FxHashMap, FxHashSet}; use crate::{machinst::*, trace}; -use rustc_hash::{FxHashMap, FxHashSet}; /// Mapping from CLIF BBs to VCode BBs. #[derive(Debug)] diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index 6b5de1ea41b7..abd5396178db 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -180,15 +180,15 @@ use crate::machinst::{ use crate::trace; use crate::{MachInstEmitState, ir}; use crate::{VCodeConstantData, timing}; +use alloc::collections::BinaryHeap; +use alloc::string::String; +use alloc::vec::Vec; +use core::cmp::Ordering; +use core::mem; use core::ops::Range; use cranelift_control::ControlPlane; use cranelift_entity::{PrimaryMap, SecondaryMap, entity_impl}; use smallvec::SmallVec; -use core::cmp::Ordering; -use alloc::collections::BinaryHeap; -use core::mem; -use alloc::string::String; -use alloc::vec::Vec; #[cfg(feature = "enable-serde")] use serde::{Deserialize, Serialize}; @@ -2910,4 +2910,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/inst_common.rs b/cranelift/codegen/src/machinst/inst_common.rs index 1a15cde4e1fa..b077dd3b6112 100644 --- a/cranelift/codegen/src/machinst/inst_common.rs +++ b/cranelift/codegen/src/machinst/inst_common.rs @@ -14,4 +14,3 @@ pub struct InsnInput { pub(crate) insn: IRInst, pub(crate) input: usize, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 6d61a37f3072..c3ce9fa9c96c 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -22,11 +22,11 @@ use crate::machinst::{ }; use crate::settings::Flags; use crate::{CodegenError, CodegenResult, trace}; +use crate::{FxHashMap, FxHashSet}; use alloc::vec::Vec; +use core::fmt::Debug; use cranelift_control::ControlPlane; -use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; -use core::fmt::Debug; use super::{VCodeBuildDirection, VRegAllocator}; @@ -38,7 +38,7 @@ pub type InstOutput = SmallVec<[ValueRegs; 2]>; /// any side-effecting op (for this purpose, loads are also considered /// side-effecting, to avoid subtle questions w.r.t. the memory model), and /// furthermore, it is guaranteed that for any two instructions A and B such -/// that color(A) == color(B), either A dominates B and B pocoreominates A, or +/// that color(A) == color(B), either A dominates B and B postdominates A, or /// vice-versa. (For now, in practice, only ops in the same basic block can ever /// have the same color, trivially providing the second condition.) Intuitively, /// this means that the ops of the same color must always execute "together", as @@ -1389,7 +1389,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { /// Instruction input/output queries. impl<'func, I: VCodeInst> Lower<'func, I> { - /// Get the incoreata for a given IR instruction. + /// Get the instdata for a given IR instruction. pub fn data(&self, ir_inst: Inst) -> &InstructionData { &self.f.dfg.insts[ir_inst] } @@ -1797,4 +1797,3 @@ mod tests { assert_eq!(uses[v5], ValueUseState::Unused); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 4c014f5dd0f2..c327803d5fb3 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -53,13 +53,13 @@ use crate::result::CodegenResult; use crate::settings; use crate::settings::Flags; use crate::value_label::ValueLabelsRanges; +use alloc::string::String; use alloc::vec::Vec; use core::fmt::Debug; use cranelift_control::ControlPlane; use cranelift_entity::PrimaryMap; use regalloc2::VReg; use smallvec::{SmallVec, smallvec}; -use alloc::string::String; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index 5d364601297d..dd28ee05f4c8 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -563,4 +563,3 @@ pub trait PrettyPrint { self.pretty_print(0) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index a1fb9c9e12bb..abf575f8847a 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -18,6 +18,7 @@ //! backend pipeline. use crate::CodegenError; +use crate::FxHashMap; use crate::ir::pcc::*; use crate::ir::{self, Constant, ConstantData, ValueLabel, types}; use crate::ranges::Ranges; @@ -29,11 +30,9 @@ use regalloc2::{ Edit, Function as RegallocFunction, InstOrEdit, InstPosition, InstRange, Operand, OperandConstraint, OperandKind, PRegSet, ProgPoint, RegClass, }; -use rustc_hash::FxHashMap; use crate::HashMap; use crate::hash_map::Entry; - use core::cmp::Ordering; use core::fmt::{self, Write}; use core::mem::take; @@ -2058,4 +2057,3 @@ mod test { // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes. } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 3c9dd6693edf..fc360913b1d9 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -15,9 +15,9 @@ pub use crate::ir::{ use crate::isle_common_prelude_methods; use crate::machinst::isle::*; use crate::trace; +use core::marker::PhantomData; use cranelift_entity::packed_option::ReservedValue; use smallvec::{SmallVec, smallvec}; -use core::marker::PhantomData; pub type Unit = (); pub type ValueArray2 = [Value; 2]; diff --git a/cranelift/codegen/src/opts/generated_code.rs b/cranelift/codegen/src/opts/generated_code.rs index 2ff9eaef16bc..82208623362a 100644 --- a/cranelift/codegen/src/opts/generated_code.rs +++ b/cranelift/codegen/src/opts/generated_code.rs @@ -16,4 +16,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_opt.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index ae9f3ad6ed24..ab5def4f75b4 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -5,9 +5,9 @@ use crate::ir; use crate::ir::Function; use crate::ir::{Block, BlockArg, BlockCall, Inst, Value}; use crate::timing; +use crate::{FxHashMap, FxHashSet}; use bumpalo::Bump; use cranelift_entity::SecondaryMap; -use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::SmallVec; // A note on notation. For the sake of clarity, this file uses the phrase diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 39899e63480c..158ba139bd42 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -566,4 +566,3 @@ enable_incremental_compilation_cache_checks = false assert_eq!(f.opt_level(), super::OptLevel::Speed); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/souper_harvest.rs b/cranelift/codegen/src/souper_harvest.rs index 5ea25882bae3..02958ed56a71 100644 --- a/cranelift/codegen/src/souper_harvest.rs +++ b/cranelift/codegen/src/souper_harvest.rs @@ -587,4 +587,3 @@ fn post_order_dfs( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 0aac5d0d024f..c57846c59c1f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2314,4 +2314,3 @@ mod tests { assert_err_with_msg!(errors, "block0 cannot be empty"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index ab4b51effee1..c0025aa6fca3 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -749,4 +749,3 @@ mod tests { ); } } -use crate::prelude::*; From 273766faf89d6cfa481751c2c11856a39815969f Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 08:56:34 +0100 Subject: [PATCH 14/61] add imports --- cranelift/codegen/src/alias_analysis.rs | 1 + cranelift/codegen/src/dominator_tree.rs | 1 + cranelift/codegen/src/egraph/elaborate.rs | 1 + cranelift/codegen/src/{egraph.rs => egraph/mod.rs} | 1 + cranelift/codegen/src/ir/exception_table.rs | 1 + cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/ir/stackslot.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 1 + cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 1 + cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 1 + cranelift/codegen/src/lib.rs | 2 ++ cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 1 + cranelift/codegen/src/machinst/isle.rs | 2 +- cranelift/codegen/src/machinst/lower.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/settings.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 1 + cranelift/codegen/src/write.rs | 1 + 22 files changed, 23 insertions(+), 1 deletion(-) rename cranelift/codegen/src/{egraph.rs => egraph/mod.rs} (99%) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index eecb38096d1b..ba141d235001 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,6 +61,7 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. +use crate::prelude::*; use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 23d099a4251a..29e65a9ae806 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -4,6 +4,7 @@ use crate::entity::SecondaryMap; use crate::flowgraph::{BlockPredecessor, ControlFlowGraph}; use crate::ir::{Block, Function, Layout, ProgramPoint}; use crate::packed_option::PackedOption; +use crate::prelude::*; use crate::timing; use alloc::vec::Vec; use core::cmp; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index 86443e5cb126..b717fc32df4e 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -9,6 +9,7 @@ use crate::hash_map::Entry as HashEntry; use crate::inst_predicates::is_pure_for_egraph; use crate::ir::{Block, Function, Inst, Value, ValueDef}; use crate::loop_analysis::{Loop, LoopAnalysis}; +use crate::prelude::*; use crate::scoped_hash_map::ScopedHashMap; use crate::trace; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph/mod.rs similarity index 99% rename from cranelift/codegen/src/egraph.rs rename to cranelift/codegen/src/egraph/mod.rs index 280109470d01..938f632bf892 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph/mod.rs @@ -15,6 +15,7 @@ use crate::ir::{ use crate::loop_analysis::LoopAnalysis; use crate::opts::IsleContext; use crate::opts::generated_code::SkeletonInstSimplification; +use crate::prelude::*; use crate::scoped_hash_map::{Entry as ScopedEntry, ScopedHashMap}; use crate::settings::Flags; use crate::take_and_replace::TakeAndReplace; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 4130f23792b4..f92ad688e565 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -19,6 +19,7 @@ use crate::ir::entities::{ExceptionTag, SigRef}; use crate::ir::instructions::ValueListPool; use crate::ir::{BlockCall, Value}; +use crate::prelude::*; use alloc::vec::Vec; use core::fmt::{self, Display, Formatter}; #[cfg(feature = "enable-serde")] diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 79b9432960af..d6f1deb65015 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -4,6 +4,7 @@ //! Each type here should have a corresponding definition in the //! `cranelift-codegen/meta/src/shared/immediates` crate in the meta language. +use crate::prelude::*; use alloc::vec::Vec; use core::cmp::Ordering; use core::fmt::{self, Display, Formatter}; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 1ad2a5d7d871..01bf2ff1a6ab 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -6,6 +6,7 @@ use crate::entity::PrimaryMap; use crate::ir::StackSlot; use crate::ir::entities::{DynamicStackSlot, DynamicType}; +use crate::prelude::*; use core::fmt; use core::str::FromStr; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index b3a8dfed44a0..76eeb9e4a16b 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -8,6 +8,7 @@ use crate::isa::winch; use crate::isa::{CallConv, unwind::UnwindInst, x64::inst::*, x64::settings as x64_settings}; use crate::machinst::abi::*; use crate::machinst::*; +use crate::prelude::*; use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 233299966a16..1ac58c5f8872 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,6 +7,7 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; +use crate::prelude::*; use alloc::string::String; use core::fmt; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 8d41f2e6d484..783f33414cb2 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -4,6 +4,7 @@ use super::{ Amode, Gpr, Inst, LabelUse, MachBuffer, MachLabel, OperandVisitor, OperandVisitorImpl, SyntheticAmode, VCodeConstant, WritableGpr, WritableXmm, Xmm, args::FromWritableReg, }; +use crate::prelude::*; use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 8bff031e3fc4..f6e0b02cb38a 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -8,6 +8,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::isa::x64::settings as x64_settings; use crate::isa::{CallConv, FunctionAlignment}; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; use crate::{machinst::*, trace}; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index b1416e88df5c..62a81a6dd722 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,6 +6,7 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; +use crate::prelude::*; use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 37a386504347..bf41f40c2af5 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -13,6 +13,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::{CodegenError, CodegenResult}; use crate::settings::{self as shared_settings, Flags}; use crate::{Final, MachBufferFinalized}; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 7e006e41014a..2ba4a4db5a4c 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -45,6 +45,8 @@ pub use gimli; // Pull in generated the `isle_numerics_methods` macro. include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); +mod prelude; + #[macro_use] mod machinst; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 08f275ccca76..b885a0275c10 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -105,6 +105,7 @@ use crate::entity::SecondaryMap; use crate::ir::{ArgumentExtension, ArgumentPurpose, ExceptionTag, Signature}; use crate::ir::{StackSlotKey, types::*}; use crate::isa::TargetIsa; +use crate::prelude::*; use crate::settings::ProbestackStrategy; use crate::{ir, isa}; use crate::{machinst::*, trace}; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index abd5396178db..da95e541ff6b 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -177,6 +177,7 @@ use crate::isa::unwind::UnwindInst; use crate::machinst::{ BlockIndex, MachInstLabelUse, TextSectionBuilder, VCodeConstant, VCodeConstants, VCodeInst, }; +use crate::prelude::*; use crate::trace; use crate::{MachInstEmitState, ir}; use crate::{VCodeConstantData, timing}; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index f73ede5b257b..8a64fab294f3 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -641,7 +641,7 @@ macro_rules! isle_lower_prelude_methods { et: ExceptionTable, labels: &MachLabelSlice, ) -> OptionTryCallInfo { - let mut exception_handlers = vec![]; + let mut exception_handlers = alloc::vec![]; let mut labels = labels.iter().cloned(); for item in self.lower_ctx.dfg().exception_tables[et].clone().items() { match item { diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index c3ce9fa9c96c..0dcc5170a97a 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -20,6 +20,7 @@ use crate::machinst::{ VCodeBuilder, VCodeConstant, VCodeConstantData, VCodeConstants, VCodeInst, ValueRegs, Writable, writable_value_regs, }; +use crate::prelude::*; use crate::settings::Flags; use crate::{CodegenError, CodegenResult, trace}; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index abf575f8847a..4cb6b0992cbd 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -21,6 +21,7 @@ use crate::CodegenError; use crate::FxHashMap; use crate::ir::pcc::*; use crate::ir::{self, Constant, ConstantData, ValueLabel, types}; +use crate::prelude::*; use crate::ranges::Ranges; use crate::timing; use crate::trace; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 158ba139bd42..90b835c0965a 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -22,6 +22,7 @@ use crate::constant_hash::{probe, simple_hash}; use crate::isa::TargetIsa; +use crate::prelude::*; use alloc::boxed::Box; use alloc::string::{String, ToString}; use core::fmt; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index c57846c59c1f..64079b289d83 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -77,6 +77,7 @@ use crate::ir::{ ValueList, types, }; use crate::isa::TargetIsa; +use crate::prelude::*; use crate::print_errors::pretty_verifier_error; use crate::settings::FlagsOrIsa; use crate::timing; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index c0025aa6fca3..1961a57dfd9a 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -9,6 +9,7 @@ use crate::ir::immediates::Ieee128; use crate::ir::pcc::Fact; use crate::ir::{Block, DataFlowGraph, Function, Inst, Opcode, SigRef, Type, Value, ValueDef}; use crate::packed_option::ReservedValue; +use crate::prelude::*; use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::{self, Write}; From 97db7e262b6fe10e8a96a3250e52fdd44a36e766 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 09:47:49 +0100 Subject: [PATCH 15/61] fix floating issues with libm --- Cargo.lock | 1 + cranelift/codegen/Cargo.toml | 5 +++-- cranelift/codegen/src/ir/immediates.rs | 11 ++++++----- cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 3 +++ cranelift/codegen/src/machinst/vcode.rs | 3 +++ 6 files changed, 17 insertions(+), 7 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 5adfd6c34940..dca90fc5af31 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -766,6 +766,7 @@ dependencies = [ "env_logger 0.11.5", "gimli 0.32.3", "hashbrown 0.15.2", + "libm", "log", "postcard", "proptest", diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 9376b79ddd2c..bc86d1b8d8d6 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -37,13 +37,14 @@ serde = { workspace = true, optional = true } serde_derive = { workspace = true, optional = true } pulley-interpreter = { workspace = true, optional = true } postcard = { workspace = true, optional = true } -gimli = { workspace = true, features = ["write", "std"], optional = true } +gimli = { workspace = true, features = ["write"], optional = true } smallvec = { workspace = true } regalloc2 = { workspace = true, features = ["checker"] } souper-ir = { version = "2.1.0", optional = true } sha2 = { version = "0.10.2", optional = true } rustc-hash = { workspace = true } wasmtime-math = { workspace = true } +libm = { workspace = true, features = ["unstable-public-internals"] } # It is a goal of the cranelift-codegen crate to have minimal external dependencies. # Please don't add any unless they are essential to the task of creating binary # machine code. Integration tests that need external dependencies can be @@ -65,7 +66,7 @@ default = ["std", "unwind", "host-arch", "timing"] # The "std" feature enables use of libstd. The "core" feature enables use # of some minimal std-like replacement libraries. At least one of these two # features need to be enabled. -std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] +std = ["serde?/std", "rustc-hash/std", "gimli/std", "cranelift-control/fuzz"] # The "core" feature used to enable a hashmap workaround, but is now # deprecated (we (i) always use hashbrown, and (ii) don't support a diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index d6f1deb65015..15af5a5ec20f 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -11,6 +11,7 @@ use core::fmt::{self, Display, Formatter}; use core::ops::{Add, BitAnd, BitOr, BitXor, Div, Mul, Neg, Not, Sub}; use core::str::FromStr; use core::{i32, u32}; +use libm::Libm; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; @@ -683,28 +684,28 @@ macro_rules! ieee_float { $( /// Returns the square root of `self`. pub fn sqrt(self) -> Self { - Self::with_float(self.$as_float().sqrt()) + Self::with_float(Libm::<$float_ty>::sqrt(self.$as_float())) } /// Returns the smallest integer greater than or equal to `self`. pub fn ceil(self) -> Self { - Self::with_float(self.$as_float().ceil()) + Self::with_float(Libm::<$float_ty>::ceil(self.$as_float())) } /// Returns the largest integer less than or equal to `self`. pub fn floor(self) -> Self { - Self::with_float(self.$as_float().floor()) + Self::with_float(Libm::<$float_ty>::floor(self.$as_float())) } /// Returns the integer part of `self`. This means that non-integer numbers are always truncated towards zero. pub fn trunc(self) -> Self { - Self::with_float(self.$as_float().trunc()) + Self::with_float(Libm::<$float_ty>::trunc(self.$as_float())) } /// Returns the nearest integer to `self`. Rounds half-way cases to the number /// with an even least significant digit. pub fn round_ties_even(self) -> Self { - Self::with_float(self.$as_float().round_ties_even()) + Self::with_float(libm::generic::rint_round(self.$as_float(), libm::support::Round::Nearest).val) } )? } diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index ada37b03ccbb..c9ea050fb28a 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -14,6 +14,7 @@ pub mod winx64; #[cfg(feature = "unwind")] pub mod winarm64; +#[cfg(feature = "unwind")] /// CFA-based unwind information used on SystemV. pub type CfaUnwindInfo = systemv::UnwindInfo; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index bf41f40c2af5..b4cc5467536a 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -29,6 +29,7 @@ mod lower; mod pcc; pub mod settings; +#[cfg(feature = "unwind")] pub use inst::unwind::systemv::create_cie; /// An X64 backend. @@ -218,6 +219,7 @@ pub fn emit_unwind_info( ) -> CodegenResult> { use crate::isa::unwind::{UnwindInfo, UnwindInfoKind}; Ok(match kind { + #[cfg(feature = "unwind")] UnwindInfoKind::SystemV => { let mapper = self::inst::unwind::systemv::RegisterMapper; Some(UnwindInfo::SystemV( @@ -228,6 +230,7 @@ pub fn emit_unwind_info( )?, )) } + #[cfg(feature = "unwind")] UnwindInfoKind::Windows => Some(UnwindInfo::WindowsX64( crate::isa::unwind::winx64::create_unwind_info_from_insts::< self::inst::unwind::winx64::RegisterMapper, diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 4cb6b0992cbd..8ffebaba177e 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -1278,6 +1278,9 @@ impl VCode { let slot = alloc.as_stack().unwrap(); let slot_offset = self.abi.get_spillslot_offset(slot); let slot_base_to_caller_sp_offset = self.abi.slot_base_to_caller_sp_offset(); + #[cfg(not(feature = "unwind"))] + let caller_sp_to_cfa_offset = 0; + #[cfg(feature = "unwind")] let caller_sp_to_cfa_offset = crate::isa::unwind::systemv::caller_sp_to_cfa_offset(); // NOTE: this is a negative offset because it's relative to the caller's SP From 56f9077be6b93d5fd30994d883415425e271ae31 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 10:15:01 +0100 Subject: [PATCH 16/61] remove unused import --- cranelift/codegen/src/prelude.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index 5dd5950bdf86..6a3c99912572 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,4 +1,2 @@ pub use alloc::format; -pub use alloc::string::ToString; pub use alloc::vec; - From 57f8847e1981cd8e81ee4ce26e7a496409e0884f Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 12:16:25 +0100 Subject: [PATCH 17/61] temporarily remove OnceLock --- cranelift/codegen/src/isa/aarch64/abi.rs | 9 +++------ cranelift/codegen/src/isa/pulley_shared/abi.rs | 6 ++---- cranelift/codegen/src/isa/riscv64/abi.rs | 6 ++---- cranelift/codegen/src/isa/s390x/abi.rs | 13 +++---------- cranelift/codegen/src/isa/x64/abi.rs | 9 +++------ cranelift/codegen/src/machinst/abi.rs | 4 ++-- cranelift/codegen/src/machinst/compile.rs | 5 +++-- cranelift/codegen/src/machinst/vcode.rs | 2 +- 8 files changed, 19 insertions(+), 35 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 8f1afce63a87..68e23a6054d9 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -17,7 +17,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because // these ABIs are very similar. @@ -1087,13 +1086,11 @@ impl ABIMachineSpec for AArch64MachineDeps { } } - fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { + fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { if flags.enable_pinned_reg() { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env(true)) + create_reg_env(true) } else { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env(false)) + create_reg_env(false) } } diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index de32099a14a7..07a537b94127 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,7 +15,6 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). pub(crate) type PulleyCallee

= Callee>; @@ -474,9 +473,8 @@ where } } - fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(create_reg_environment) + fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { + create_reg_environment() } fn get_regs_clobbered_by_call( diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index f53eee9a53a0..d8646010d2d0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -21,7 +21,6 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). pub(crate) type Riscv64Callee = Callee; @@ -612,9 +611,8 @@ impl ABIMachineSpec for Riscv64MachineDeps { } } - fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(create_reg_environment) + fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { + create_reg_environment() } fn get_regs_clobbered_by_call( diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 738e037047d3..2c4c281d8051 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -148,7 +148,6 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -904,16 +903,10 @@ impl ABIMachineSpec for S390xMachineDeps { } } - fn get_machine_env(_flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv { + fn get_machine_env(_flags: &settings::Flags, call_conv: isa::CallConv) -> MachineEnv { match call_conv { - isa::CallConv::Tail => { - static TAIL_MACHINE_ENV: OnceLock = OnceLock::new(); - TAIL_MACHINE_ENV.get_or_init(tail_create_machine_env) - } - _ => { - static SYSV_MACHINE_ENV: OnceLock = OnceLock::new(); - SYSV_MACHINE_ENV.get_or_init(sysv_create_machine_env) - } + isa::CallConv::Tail => tail_create_machine_env(), + _ => sysv_create_machine_env(), } } diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 76eeb9e4a16b..2563083f917e 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -17,7 +17,6 @@ use args::*; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -874,13 +873,11 @@ impl ABIMachineSpec for X64ABIMachineSpec { } } - fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { + fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { if flags.enable_pinned_reg() { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env_systemv(true)) + create_reg_env_systemv(true) } else { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env_systemv(false)) + create_reg_env_systemv(false) } } diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index b885a0275c10..1474eac342a2 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -575,7 +575,7 @@ pub trait ABIMachineSpec { ) -> u32; /// Get the ABI-dependent MachineEnv for managing register allocation. - fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv; + fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> MachineEnv; /// Get all caller-save registers, that is, registers that we expect /// not to be saved across a call to a callee with the given ABI. @@ -1540,7 +1540,7 @@ impl Callee { } /// Get the ABI-dependent MachineEnv for managing register allocation. - pub fn machine_env(&self) -> &MachineEnv { + pub fn machine_env(&self) -> MachineEnv { M::get_machine_env(&self.flags, self.call_conv) } diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index cd2e7e9d6ac5..9c7d2d55bd26 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -69,7 +69,7 @@ pub fn compile( RegallocAlgorithm::SinglePass => Algorithm::Fastalloc, }; - regalloc2::run(&vcode, vcode.abi.machine_env(), &options) + regalloc2::run(&vcode, &vcode.abi.machine_env(), &options) .map_err(|err| { log::error!( "Register allocation error for vcode\n{vcode:?}\nError: {err:?}\nCLIF for error:\n{f:?}", @@ -82,7 +82,8 @@ pub fn compile( // Run the regalloc checker, if requested. if b.flags().regalloc_checker() { let _tt = timing::regalloc_checker(); - let mut checker = regalloc2::checker::Checker::new(&vcode, vcode.abi.machine_env()); + let machine_env = vcode.abi.machine_env(); + let mut checker = regalloc2::checker::Checker::new(&vcode, &machine_env); checker.prepare(®alloc_result); checker .run() diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 8ffebaba177e..97c467ce212f 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -516,7 +516,7 @@ impl VCodeBuilder { } fn collect_operands(&mut self, vregs: &VRegAllocator) { - let allocatable = PRegSet::from(self.vcode.abi.machine_env()); + let allocatable = PRegSet::from(&self.vcode.abi.machine_env()); for (i, insn) in self.vcode.insts.iter_mut().enumerate() { // Push operands from the instruction onto the operand list. // From 04a592c40a27cfe866a02b6005aab51595481ab8 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 12:44:44 +0100 Subject: [PATCH 18/61] add no_std arm support and add it into CI --- .github/workflows/main.yml | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 + cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 + cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 1 + cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 + cranelift/codegen/src/isa/s390x/inst/mod.rs | 1 + cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 + cranelift/codegen/src/isa/s390x/mod.rs | 1 + 15 files changed, 15 insertions(+) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index fe35d822d676..50e7d5bd599c 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -551,6 +551,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && cargo check -p cranelift-assembler-x64 --lib && + cargo check -p cranelift-codegen --no-default-features -F x86,arm64 && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 68e23a6054d9..cb75d3082fb0 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -11,6 +11,7 @@ use crate::isa::aarch64::{inst::*, settings as aarch64_settings}; use crate::isa::unwind::UnwindInst; use crate::isa::winch; use crate::machinst::*; +use crate::prelude::*; use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index fcd67deed576..09aa838b8e82 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -3,6 +3,7 @@ use crate::ir::types::*; use crate::isa::aarch64::inst::{OperandSize, ScalarSize}; use crate::machinst::PrettyPrint; +use crate::prelude::*; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 90ba2ef0c75d..ead759b93028 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -5,6 +5,7 @@ use crate::ir::types::{F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128}; use crate::ir::{MemFlags, Type, types}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; use crate::machinst::{PrettyPrint, Reg, RegClass, Writable}; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 7db69df4ebe4..c9468f46e932 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -5,6 +5,7 @@ use crate::isa::aarch64::inst::ScalarSize; use crate::isa::aarch64::inst::VectorSize; use crate::machinst::RealReg; use crate::machinst::{Reg, RegClass, Writable}; +use crate::prelude::*; use regalloc2::PReg; use regalloc2::VReg; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 2f80ad9fa29b..dafb6364f38d 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -10,6 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index d8646010d2d0..d1d12621dd5c 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -14,6 +14,7 @@ use crate::ir::LibCall; use crate::ir::Signature; use crate::isa::riscv64::settings::Flags as RiscvFlags; use crate::isa::unwind::UnwindInst; +use crate::prelude::*; use crate::settings; use alloc::boxed::Box; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 9349d64cd08f..2addfd65b63a 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -8,6 +8,7 @@ use crate::ir::types::{self, F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128 pub use crate::ir::{ExternalName, MemFlags, Type}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; pub use crate::ir::condcodes::FloatCC; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 269e6481b506..0c8c49f8544b 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -5,6 +5,7 @@ use crate::isa::riscv64::lower::isle::generated_code::{ VecElementWidth, VecLmul, VecMaskMode, VecOpCategory, VecOpMasking, VecTailMode, }; use crate::machinst::{OperandVisitor, RegClass}; +use crate::prelude::*; use core::fmt; use super::{Type, UImm5}; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index ca0a1a13e2e9..5affb19a8a65 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -10,6 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::CodegenResult; use crate::settings::{self as shared_settings, Flags}; use crate::{CodegenError, ir}; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 2c4c281d8051..8c566ff24756 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -143,6 +143,7 @@ use crate::isa; use crate::isa::s390x::{inst::*, settings as s390x_settings}; use crate::isa::unwind::UnwindInst; use crate::machinst::*; +use crate::prelude::*; use crate::settings; use alloc::borrow::ToOwned; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 9559f34ac7f8..e114d9b022b0 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,6 +1,7 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; +use crate::prelude::*; use alloc::string::String; /// An unsigned 12-bit immediate. diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 762f6c58d27e..b61bb215c187 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -5,6 +5,7 @@ use crate::ir::{ExternalName, Type, types}; use crate::isa::s390x::abi::S390xMachineDeps; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; use alloc::boxed::Box; use alloc::string::{String, ToString}; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index d3985bb9d20b..8b0205569b80 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -5,6 +5,7 @@ use regalloc2::PReg; use crate::isa::s390x::inst::{RegPair, WritableRegPair}; use crate::machinst::*; +use crate::prelude::*; //============================================================================= // Registers, the Universe thereof, and printing diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 6bc40484153d..b3f7986b9e8b 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -10,6 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; From 8a6fcfd80fd663f0233bb9a8df75fef5c9e57679 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 16:45:24 +0100 Subject: [PATCH 19/61] Move most things from std to core and alloc --- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/ctxhash.rs | 1 + cranelift/codegen/src/ir/pcc.rs | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 1 + .../codegen/src/isa/aarch64/inst/emit_tests.rs | 2 +- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 2 ++ cranelift/codegen/src/isa/aarch64/lower/isle.rs | 2 ++ cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/abi.rs | 1 + .../codegen/src/isa/pulley_shared/inst/args.rs | 1 + cranelift/codegen/src/isa/pulley_shared/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/mod.rs | 3 +++ cranelift/codegen/src/isa/riscv64/lower/isle.rs | 2 ++ cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 1 + .../codegen/src/isa/s390x/inst/emit_tests.rs | 16 ++++++++-------- cranelift/codegen/src/isa/s390x/inst/mod.rs | 4 +++- cranelift/codegen/src/isa/s390x/lower/isle.rs | 3 +++ cranelift/codegen/src/isa/s390x/mod.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 2 +- cranelift/codegen/src/isa/x64/inst/args.rs | 2 +- cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 2 +- cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 2 ++ cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 5 +++++ cranelift/codegen/src/machinst/lower.rs | 5 +++-- cranelift/codegen/src/machinst/mod.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/opts.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 4 ++-- 33 files changed, 57 insertions(+), 18 deletions(-) diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 56d90b18975c..32112265eb68 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -65,7 +65,7 @@ default = ["std", "unwind", "host-arch", "timing"] # The "std" feature enables use of libstd. The "core" feature enables use # of some minimal std-like replacement libraries. At least one of these two # features need to be enabled. -std = ["serde?/std"] +std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # The "core" feature used to enable a hashmap workaround, but is now # deprecated (we (i) always use hashbrown, and (ii) don't support a diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index ea7de766006e..7148046ae9c1 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -6,6 +6,7 @@ use core::hash::{Hash, Hasher}; use hashbrown::hash_table::HashTable; +use core::hash::{Hash, Hasher}; /// Trait that allows for equality comparison given some external /// context. diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index 8b9a3cc6bb6e..d1bf7ea62dba 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -79,6 +79,7 @@ use crate::machinst::{BlockIndex, LowerBackend, VCode}; use crate::trace; use core::fmt; use regalloc2::Function as _; +use core::fmt; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 8f1afce63a87..33e986347018 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -17,6 +17,7 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index d8e6cd6a2083..baa42a265cb2 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -27,7 +27,7 @@ fn test_aarch64_binemit() { // // #!/bin/sh // tmp=`mktemp /tmp/XXXXXXXX.o` - // aarch64-linux-gnu-as /dev/stdin -o $tmp + // aarch64-linux-gnu-as /dev/corein -o $tmp // aarch64-linux-gnu-objdump -d $tmp // rm -f $tmp // diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 90ba2ef0c75d..9ccfb7ad985c 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -14,6 +14,8 @@ use alloc::vec::Vec; use core::fmt::Write; use core::slice; use smallvec::{SmallVec, smallvec}; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub(crate) mod regs; pub(crate) use self::regs::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 3e82af2a9c8e..31800f10dafb 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -35,6 +35,8 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::u32; use regalloc2::PReg; +use alloc::boxed::Box; +use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxCallIndInfo = Box>; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 2f80ad9fa29b..dc3ab2c92c3d 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -16,6 +16,7 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Aarch64Architecture, Architecture, OperatingSystem, Triple}; // New backend: diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index de32099a14a7..cd7427a4e345 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,6 +15,7 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index e97e3303ef99..440699490b8e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -6,6 +6,7 @@ use crate::machinst::abi::StackAMode; use core::fmt; use pulley_interpreter::encode; use pulley_interpreter::regs::Reg as _; +use core::fmt; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 0b781e467a08..1c0b736c15f3 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -22,6 +22,7 @@ use alloc::vec::Vec; use core::fmt::Debug; use core::marker::PhantomData; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; pub use settings::Flags as PulleyFlags; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index f53eee9a53a0..ca08f1c0b58a 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -21,6 +21,7 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 9349d64cd08f..119ff1fd48d2 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -18,6 +18,9 @@ use alloc::vec::Vec; use core::fmt::Write; use regalloc2::RegClass; use smallvec::{SmallVec, smallvec}; +use alloc::boxed::Box; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index a2a7d0c196e6..e0ef1971bdf3 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -24,6 +24,8 @@ use crate::{ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::PReg; +use alloc::boxed::Box; +use alloc::vec::Vec; use wasmtime_math::{f32_cvt_to_int_bounds, f64_cvt_to_int_bounds}; type BoxCallInfo = Box>; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index ca0a1a13e2e9..a2c1ffe5691e 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -17,6 +17,7 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; mod abi; pub(crate) mod inst; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 738e037047d3..4ca965cba2b5 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -148,6 +148,7 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index aa6f9e6b19c9..569c16ac5c4d 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -12039,7 +12039,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102000", - "std %f1, 0(%r2)", + "core %f1, 0(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12054,7 +12054,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102FFF", - "std %f1, 4095(%r2)", + "core %f1, 4095(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12069,7 +12069,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1020008067", - "stdy %f1, -524288(%r2)", + "corey %f1, -524288(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12084,7 +12084,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED102FFF7F67", - "stdy %f1, 524287(%r2)", + "corey %f1, 524287(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12129,7 +12129,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123000", - "std %f1, 0(%r2,%r3)", + "core %f1, 0(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12144,7 +12144,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123FFF", - "std %f1, 4095(%r2,%r3)", + "core %f1, 4095(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12159,7 +12159,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1230008067", - "stdy %f1, -524288(%r2,%r3)", + "corey %f1, -524288(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12174,7 +12174,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED123FFF7F67", - "stdy %f1, 524287(%r2,%r3)", + "corey %f1, 524287(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 762f6c58d27e..26dc83d16bff 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -11,6 +11,8 @@ use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::Write; use smallvec::SmallVec; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; pub mod imms; @@ -2968,7 +2970,7 @@ impl Inst { (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None), (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None), (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")), - (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")), + (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("core"), Some("corey")), (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None), (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None), (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None), diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index 561fabd9561e..b3115fd7229e 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -27,6 +27,9 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::cell::Cell; use regalloc2::PReg; +use alloc::boxed::Box; +use core::cell::Cell; +use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxReturnCallInfo = Box>; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 6bc40484153d..674e179d4459 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -16,6 +16,7 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; // New backend: diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index b3a8dfed44a0..cd07032c2bc2 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -13,10 +13,10 @@ use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use args::*; +use std::sync::OnceLock; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 233299966a16..35c22ca49b3c 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,8 +7,8 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use alloc::string::String; use core::fmt; +use alloc::string::String; /// An extension trait for converting `Writable{Xmm,Gpr}` to `Writable`. pub trait ToWritableReg { diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 1bd8b0f6b28e..9e47ea081b56 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -2,7 +2,7 @@ //! //! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases. //! -//! to see stdout: cargo test -- --nocapture +//! to see coreout: cargo test -- --nocapture //! //! for this specific case, as of 24 Aug 2020: //! diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 8d41f2e6d484..434eee65a63a 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -8,6 +8,7 @@ use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; use regalloc2::{PReg, RegClass}; +use alloc::string::String; /// Define the types of registers Cranelift will use. #[derive(Clone, Debug)] diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 8bff031e3fc4..d2ef4c40949f 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -18,6 +18,8 @@ use core::fmt::{self, Write}; use core::slice; use cranelift_assembler_x64 as asm; use smallvec::{SmallVec, smallvec}; +use core::fmt::{self, Write}; +use alloc::string::{String, ToString}; pub mod args; mod emit; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index b1416e88df5c..03671acfbc8f 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -10,6 +10,7 @@ use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; use regalloc2::{PReg, RegClass, VReg}; +use alloc::string::String; // Constructors for Regs. diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 60ea23445e1f..951d74959703 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -109,6 +109,7 @@ use crate::{ir, isa}; use crate::{machinst::*, trace}; use alloc::boxed::Box; use core::marker::PhantomData; +use hashbrown::HashMap; use regalloc2::{MachineEnv, PReg, PRegSet}; use rustc_hash::FxHashMap; use smallvec::smallvec; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index abd5396178db..fb7241d01c65 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -189,6 +189,11 @@ use core::ops::Range; use cranelift_control::ControlPlane; use cranelift_entity::{PrimaryMap, SecondaryMap, entity_impl}; use smallvec::SmallVec; +use core::cmp::Ordering; +use alloc::collections::BinaryHeap; +use core::mem; +use alloc::string::String; +use alloc::vec::Vec; #[cfg(feature = "enable-serde")] use serde::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 4c55b018c841..18ee7643f231 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -27,6 +27,7 @@ use core::fmt::Debug; use cranelift_control::ControlPlane; use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; +use core::fmt::Debug; use super::{VCodeBuildDirection, VRegAllocator}; @@ -38,7 +39,7 @@ pub type InstOutput = SmallVec<[ValueRegs; 2]>; /// any side-effecting op (for this purpose, loads are also considered /// side-effecting, to avoid subtle questions w.r.t. the memory model), and /// furthermore, it is guaranteed that for any two instructions A and B such -/// that color(A) == color(B), either A dominates B and B postdominates A, or +/// that color(A) == color(B), either A dominates B and B pocoreominates A, or /// vice-versa. (For now, in practice, only ops in the same basic block can ever /// have the same color, trivially providing the second condition.) Intuitively, /// this means that the ops of the same color must always execute "together", as @@ -1389,7 +1390,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { /// Instruction input/output queries. impl<'func, I: VCodeInst> Lower<'func, I> { - /// Get the instdata for a given IR instruction. + /// Get the incoreata for a given IR instruction. pub fn data(&self, ir_inst: Inst) -> &InstructionData { &self.f.dfg.insts[ir_inst] } diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index c327803d5fb3..61ebb9bc0800 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -60,6 +60,7 @@ use cranelift_control::ControlPlane; use cranelift_entity::PrimaryMap; use regalloc2::VReg; use smallvec::{SmallVec, smallvec}; +use alloc::string::String; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 596d720e4e82..22c855584c09 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -33,6 +33,7 @@ use rustc_hash::FxHashMap; use crate::HashMap; use crate::hash_map::Entry; + use core::cmp::Ordering; use core::fmt::{self, Write}; use core::mem::take; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index fc360913b1d9..4ec9728f1e35 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -18,6 +18,7 @@ use crate::trace; use core::marker::PhantomData; use cranelift_entity::packed_option::ReservedValue; use smallvec::{SmallVec, smallvec}; +use core::marker::PhantomData; pub type Unit = (); pub type ValueArray2 = [Value; 2]; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index c57846c59c1f..304c3ebb202f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2130,9 +2130,9 @@ mod tests { None => panic!("Expected an error"), Some(&VerifierError { ref message, .. }) => { if !message.contains($msg) { - #[cfg(feature = "std")] + #[cfg(feature = "core")] panic!("'{}' did not contain the substring '{}'", message, $msg); - #[cfg(not(feature = "std"))] + #[cfg(not(feature = "core"))] panic!("error message did not contain the expected substring"); } } From e1bf66f470215e9a646daff355492d5883cc9bc9 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 17:58:06 +0100 Subject: [PATCH 20/61] Port assembler_x64 to no_std --- cranelift/assembler-x64/Cargo.toml | 1 + .../assembler-x64/meta/src/dsl/format.rs | 6 +++--- cranelift/assembler-x64/meta/src/generate.rs | 6 +++--- .../assembler-x64/meta/src/generate/inst.rs | 8 ++++---- cranelift/assembler-x64/src/api.rs | 9 +++++---- cranelift/assembler-x64/src/custom.rs | 5 +++-- cranelift/assembler-x64/src/features.rs | 2 +- cranelift/assembler-x64/src/fixed.rs | 1 + cranelift/assembler-x64/src/fuzz.rs | 6 +++--- cranelift/assembler-x64/src/gpr.rs | 1 + cranelift/assembler-x64/src/imm.rs | 13 ++++++++----- cranelift/assembler-x64/src/inst.rs | 3 +++ cranelift/assembler-x64/src/lib.rs | 2 ++ cranelift/assembler-x64/src/main.rs | 11 +++++++++++ cranelift/assembler-x64/src/mem.rs | 19 +++++++++++-------- cranelift/assembler-x64/src/xmm.rs | 4 ++++ 16 files changed, 64 insertions(+), 33 deletions(-) diff --git a/cranelift/assembler-x64/Cargo.toml b/cranelift/assembler-x64/Cargo.toml index 6935ec669950..424d26f206ce 100644 --- a/cranelift/assembler-x64/Cargo.toml +++ b/cranelift/assembler-x64/Cargo.toml @@ -23,3 +23,4 @@ workspace = true [features] fuzz = ['dep:arbitrary', 'dep:capstone'] +core = [] diff --git a/cranelift/assembler-x64/meta/src/dsl/format.rs b/cranelift/assembler-x64/meta/src/dsl/format.rs index fe39d1892db3..cb6b8e5a9645 100644 --- a/cranelift/assembler-x64/meta/src/dsl/format.rs +++ b/cranelift/assembler-x64/meta/src/dsl/format.rs @@ -535,7 +535,7 @@ impl Default for Mutability { } impl core::fmt::Display for Mutability { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { match self { Self::Read => write!(f, "r"), Self::ReadWrite => write!(f, "rw"), @@ -576,7 +576,7 @@ impl Default for Extension { } impl core::fmt::Display for Extension { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { match self { Extension::None => write!(f, ""), Extension::SignExtendQuad => write!(f, "sxq"), @@ -627,7 +627,7 @@ impl Default for Eflags { } impl core::fmt::Display for Eflags { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { match self { Self::None => write!(f, ""), Self::R => write!(f, "r"), diff --git a/cranelift/assembler-x64/meta/src/generate.rs b/cranelift/assembler-x64/meta/src/generate.rs index b4b13e19d33e..4191a53d6833 100644 --- a/cranelift/assembler-x64/meta/src/generate.rs +++ b/cranelift/assembler-x64/meta/src/generate.rs @@ -53,11 +53,11 @@ fn match_variants(f: &mut Formatter, insts: &[dsl::Inst], invoke: &str) { }); } -/// `impl std::fmt::Display for Inst { ... }` +/// `impl core::fmt::Display for Inst { ... }` fn generate_inst_display_impl(f: &mut Formatter, insts: &[dsl::Inst]) { - f.add_block("impl std::fmt::Display for Inst", |f| { + f.add_block("impl core::fmt::Display for Inst", |f| { f.add_block( - "fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result", + "fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result", |f| { match_variants(f, insts, "fmt(f)"); }, diff --git a/cranelift/assembler-x64/meta/src/generate/inst.rs b/cranelift/assembler-x64/meta/src/generate/inst.rs index 0991b4134be8..6d5e8b8862fe 100644 --- a/cranelift/assembler-x64/meta/src/generate/inst.rs +++ b/cranelift/assembler-x64/meta/src/generate/inst.rs @@ -107,12 +107,12 @@ impl dsl::Inst { fmtln!(f, "#[must_use]"); fmtln!(f, "#[inline]"); f.add_block( - &format!("pub fn mnemonic(&self) -> std::borrow::Cow<'static, str>"), + &format!("pub fn mnemonic(&self) -> alloc::borrow::Cow<'static, str>"), |f| { if self.custom.contains(Mnemonic) { fmtln!(f, "crate::custom::mnemonic::{}(self)", self.name()); } else { - fmtln!(f, "std::borrow::Cow::Borrowed(\"{}\")", self.mnemonic); + fmtln!(f, "alloc::borrow::Cow::Borrowed(\"{}\")", self.mnemonic); } }, ); @@ -265,10 +265,10 @@ impl dsl::Inst { let impl_block = self.generate_impl_block_start(); let struct_name = self.struct_name_with_generic(); f.add_block( - &format!("{impl_block} std::fmt::Display for {struct_name}"), + &format!("{impl_block} core::fmt::Display for {struct_name}"), |f| { f.add_block( - "fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result", + "fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result", |f| { if self.custom.contains(Display) { fmtln!(f, "crate::custom::display::{}(f, self)", self.name()); diff --git a/cranelift/assembler-x64/src/api.rs b/cranelift/assembler-x64/src/api.rs index c27101985b2c..f65cfc338045 100644 --- a/cranelift/assembler-x64/src/api.rs +++ b/cranelift/assembler-x64/src/api.rs @@ -3,9 +3,10 @@ use crate::gpr; use crate::xmm; use crate::{Amode, DeferredTarget, GprMem, XmmMem}; -use std::fmt; -use std::{num::NonZeroU8, vec::Vec}; - +use alloc::vec::Vec; +use core::fmt; +use core::num::NonZeroU8; +use alloc::string::String; /// Describe how an instruction is emitted into a code buffer. pub trait CodeSink { /// Add 1 byte to the code section. @@ -113,7 +114,7 @@ pub trait Registers { } /// Describe how to interact with an external register type. -pub trait AsReg: Copy + Clone + std::fmt::Debug + PartialEq { +pub trait AsReg: Copy + Clone + core::fmt::Debug + PartialEq { /// Create a register from its hardware encoding. /// /// This is primarily useful for fuzzing, though it is also useful for diff --git a/cranelift/assembler-x64/src/custom.rs b/cranelift/assembler-x64/src/custom.rs index adbfd2c6acc9..c2b70fecbc24 100644 --- a/cranelift/assembler-x64/src/custom.rs +++ b/cranelift/assembler-x64/src/custom.rs @@ -75,7 +75,7 @@ pub mod encode { pub mod mnemonic { use crate::inst; use crate::{Registers, XmmMem}; - use std::borrow::Cow; + use alloc::borrow::Cow; macro_rules! lock { ($name:tt => $mnemonic:expr) => { @@ -191,7 +191,8 @@ pub mod mnemonic { pub mod display { use crate::inst; use crate::{Amode, Gpr, GprMem, Registers, Size}; - use std::fmt; + use core::fmt; + use alloc::string::ToString; pub fn callq_d(f: &mut fmt::Formatter, inst: &inst::callq_d) -> fmt::Result { let inst::callq_d { imm32 } = inst; diff --git a/cranelift/assembler-x64/src/features.rs b/cranelift/assembler-x64/src/features.rs index 3559b9755662..77864e74db92 100644 --- a/cranelift/assembler-x64/src/features.rs +++ b/cranelift/assembler-x64/src/features.rs @@ -32,7 +32,7 @@ //! [`Inst::features`]: crate::inst::Inst::features use crate::inst::for_each_feature; -use std::fmt; +use core::fmt; // Helpfully generate `enum Feature`. macro_rules! create_feature_enum { diff --git a/cranelift/assembler-x64/src/fixed.rs b/cranelift/assembler-x64/src/fixed.rs index d689874c9a5a..c17ca3b944ef 100644 --- a/cranelift/assembler-x64/src/fixed.rs +++ b/cranelift/assembler-x64/src/fixed.rs @@ -1,6 +1,7 @@ //! Operands with fixed register encodings. use crate::{AsReg, Size}; +use alloc::string::String; /// A _fixed_ register. /// diff --git a/cranelift/assembler-x64/src/fuzz.rs b/cranelift/assembler-x64/src/fuzz.rs index 250e08a43e57..9bbcaf83509f 100644 --- a/cranelift/assembler-x64/src/fuzz.rs +++ b/cranelift/assembler-x64/src/fuzz.rs @@ -146,7 +146,7 @@ fn disassemble(assembled: &[u8], original: &Inst) -> String { } fn pretty_print_hexadecimal(hex: &[u8]) -> String { - use std::fmt::Write; + use core::fmt::Write; let mut s = String::with_capacity(hex.len() * 2); for b in hex { write!(&mut s, "{b:02X}").unwrap(); @@ -183,7 +183,7 @@ macro_rules! hex_print_signed_imm { /// - print negative values as `-0x...` (signed hex) instead of `0xff...` /// (normal hex) /// - print `mov` immediates as base-10 instead of base-16 (?!). -fn replace_signed_immediates(dis: &str) -> std::borrow::Cow<'_, str> { +fn replace_signed_immediates(dis: &str) -> alloc::borrow::Cow<'_, str> { match dis.find('$') { None => dis.into(), Some(idx) => { @@ -259,7 +259,7 @@ fn remove_after_parenthesis_test() { } /// Run some post-processing on the disassembly to make it match Capstone. -fn fix_up(dis: &str) -> std::borrow::Cow<'_, str> { +fn fix_up(dis: &str) -> alloc::borrow::Cow<'_, str> { let dis = remove_after_semicolon(dis); replace_signed_immediates(&dis) } diff --git a/cranelift/assembler-x64/src/gpr.rs b/cranelift/assembler-x64/src/gpr.rs index 4013c60686de..5489b513ce29 100644 --- a/cranelift/assembler-x64/src/gpr.rs +++ b/cranelift/assembler-x64/src/gpr.rs @@ -1,6 +1,7 @@ //! Pure register operands; see [`Gpr`]. use crate::AsReg; +use alloc::string::String; /// A general purpose x64 register (e.g., `%rax`). /// diff --git a/cranelift/assembler-x64/src/imm.rs b/cranelift/assembler-x64/src/imm.rs index eeb5a27d4d0d..0c129cd65d45 100644 --- a/cranelift/assembler-x64/src/imm.rs +++ b/cranelift/assembler-x64/src/imm.rs @@ -1,7 +1,10 @@ //! Immediate operands to instructions. use crate::api::CodeSink; -use std::fmt; +use core::fmt; + +#[cfg(feature = "core")] +use alloc::{format, string::String}; /// This helper function prints the unsigned hexadecimal representation of the /// immediate value: e.g., this prints `$0xfe` to represent both the signed `-2` @@ -49,7 +52,7 @@ impl From for Imm8 { } impl TryFrom for Imm8 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(u8::try_from(simm32)?)) } @@ -100,7 +103,7 @@ impl From for Simm8 { } impl TryFrom for Simm8 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(i8::try_from(simm32)?)) } @@ -134,7 +137,7 @@ impl From for Imm16 { } impl TryFrom for Imm16 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(u16::try_from(simm32)?)) } @@ -185,7 +188,7 @@ impl From for Simm16 { } impl TryFrom for Simm16 { - type Error = std::num::TryFromIntError; + type Error = core::num::TryFromIntError; fn try_from(simm32: i32) -> Result { Ok(Self(i16::try_from(simm32)?)) } diff --git a/cranelift/assembler-x64/src/inst.rs b/cranelift/assembler-x64/src/inst.rs index 173336a7372d..e4f23849cd12 100644 --- a/cranelift/assembler-x64/src/inst.rs +++ b/cranelift/assembler-x64/src/inst.rs @@ -14,6 +14,9 @@ use crate::rex::RexPrefix; use crate::vex::VexPrefix; use crate::xmm::{self, Xmm}; +use alloc::string::ToString; + + // Include code generated by the `meta` crate. include!(concat!(env!("OUT_DIR"), "/assembler.rs")); diff --git a/cranelift/assembler-x64/src/lib.rs b/cranelift/assembler-x64/src/lib.rs index 7b5b6db7fc3a..d28e102ffeb7 100644 --- a/cranelift/assembler-x64/src/lib.rs +++ b/cranelift/assembler-x64/src/lib.rs @@ -41,6 +41,8 @@ non_camel_case_types, reason = "all of the generated struct names use snake case" )] +#![cfg_attr(feature = "core", no_std)] +extern crate alloc; mod api; mod custom; diff --git a/cranelift/assembler-x64/src/main.rs b/cranelift/assembler-x64/src/main.rs index c50a80fea5b9..4361d85624f9 100644 --- a/cranelift/assembler-x64/src/main.rs +++ b/cranelift/assembler-x64/src/main.rs @@ -1,8 +1,19 @@ //! Print the path to the generated code. +#![cfg_attr(feature = "core", no_std)] +#[cfg(not(feature = "core"))] fn main() { let paths: Vec = include!(concat!(env!("OUT_DIR"), "/generated-files.rs")); for path in paths { println!("{}", path.display()); } } + +#[cfg(feature = "core")] +fn main() {} + +#[cfg(feature = "core")] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} \ No newline at end of file diff --git a/cranelift/assembler-x64/src/mem.rs b/cranelift/assembler-x64/src/mem.rs index 19cf06707e54..cffecf9bf18b 100644 --- a/cranelift/assembler-x64/src/mem.rs +++ b/cranelift/assembler-x64/src/mem.rs @@ -4,6 +4,9 @@ use crate::api::{AsReg, CodeSink, Constant, KnownOffset, Label, TrapCode}; use crate::gpr::{self, NonRspGpr, Size}; use crate::rex::{Disp, RexPrefix, encode_modrm, encode_sib}; +#[cfg(feature = "core")] +use alloc::string::{String, ToString}; + /// x64 memory addressing modes. #[derive(Copy, Clone, Debug, PartialEq)] #[cfg_attr(any(test, feature = "fuzz"), derive(arbitrary::Arbitrary))] @@ -99,8 +102,8 @@ impl From for AmodeOffset { } } -impl std::fmt::LowerHex for AmodeOffset { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::LowerHex for AmodeOffset { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { // This rather complex implementation is necessary to match how // `capstone` pretty-prints memory immediates. if self.0 == 0 { @@ -116,7 +119,7 @@ impl std::fmt::LowerHex for AmodeOffset { Some(i) => i, None => -2_147_483_648, }; - std::fmt::LowerHex::fmt(&abs, f) + core::fmt::LowerHex::fmt(&abs, f) } } @@ -154,12 +157,12 @@ impl AmodeOffsetPlusKnownOffset { } } -impl std::fmt::LowerHex for AmodeOffsetPlusKnownOffset { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { +impl core::fmt::LowerHex for AmodeOffsetPlusKnownOffset { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { if let Some(offset) = self.offset { write!(f, "+")?; } - std::fmt::LowerHex::fmt(&self.simm32, f) + core::fmt::LowerHex::fmt(&self.simm32, f) } } @@ -172,8 +175,8 @@ pub enum DeferredTarget { None, } -impl std::fmt::Display for Amode { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { +impl core::fmt::Display for Amode { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { let pointer_width = Size::Quadword; match self { Amode::ImmReg { simm32, base, .. } => { diff --git a/cranelift/assembler-x64/src/xmm.rs b/cranelift/assembler-x64/src/xmm.rs index 9b2a00a9d489..636c887afbc7 100644 --- a/cranelift/assembler-x64/src/xmm.rs +++ b/cranelift/assembler-x64/src/xmm.rs @@ -2,6 +2,10 @@ use crate::{AsReg, CodeSink, rex::encode_modrm}; +#[cfg(feature = "core")] +use alloc::string::String; +//use core::convert::{AsMut, AsRef, From}; + /// An x64 SSE register (e.g., `%xmm0`). #[derive(Clone, Copy, Debug)] pub struct Xmm(pub(crate) R); From b027b8e17e1423e57405fc05989a72644b3ce95b Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 18:26:16 +0100 Subject: [PATCH 21/61] before adding prelude to each file --- Cargo.toml | 111 +++++++++++++++++++------ cranelift/codegen/Cargo.toml | 4 +- cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/prelude.rs | 4 + 5 files changed, 92 insertions(+), 29 deletions(-) create mode 100644 cranelift/codegen/src/prelude.rs diff --git a/Cargo.toml b/Cargo.toml index ca68c5e23156..b82c369c620f 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -50,7 +50,10 @@ wasmtime-cranelift = { workspace = true, optional = true } wasmtime-environ = { workspace = true } wasmtime-explorer = { workspace = true, optional = true } wasmtime-wast = { workspace = true, optional = true } -wasi-common = { workspace = true, default-features = true, features = ["exit", "tokio"], optional = true } +wasi-common = { workspace = true, default-features = true, features = [ + "exit", + "tokio", +], optional = true } wasmtime-wasi = { workspace = true, default-features = true, optional = true } wasmtime-wasi-nn = { workspace = true, optional = true } wasmtime-wasi-config = { workspace = true, optional = true } @@ -59,7 +62,10 @@ wasmtime-wasi-keyvalue = { workspace = true, optional = true } wasmtime-wasi-threads = { workspace = true, optional = true } wasmtime-wasi-http = { workspace = true, optional = true } wasmtime-unwinder = { workspace = true } -wasmtime-wizer = { workspace = true, optional = true, features = ['clap', 'wasmtime'] } +wasmtime-wizer = { workspace = true, optional = true, features = [ + 'clap', + 'wasmtime', +] } clap = { workspace = true } clap_complete = { workspace = true, optional = true } anyhow = { workspace = true, features = ['std'] } @@ -84,7 +90,7 @@ smallvec = { workspace = true } async-trait = { workspace = true } bytes = { workspace = true } cfg-if = { workspace = true } -tokio = { workspace = true, optional = true, features = [ "signal", "macros" ] } +tokio = { workspace = true, optional = true, features = ["signal", "macros"] } hyper = { workspace = true, optional = true } http = { workspace = true, optional = true } http-body-util = { workspace = true, optional = true } @@ -95,12 +101,25 @@ rustix = { workspace = true, features = ["mm", "process"] } [dev-dependencies] # depend again on wasmtime to activate its default features for tests -wasmtime = { workspace = true, features = ['default', 'winch', 'pulley', 'all-arch', 'call-hook', 'memory-protection-keys', 'component-model-async'] } +wasmtime = { workspace = true, features = [ + 'default', + 'winch', + 'pulley', + 'all-arch', + 'call-hook', + 'memory-protection-keys', + 'component-model-async', +] } env_logger = { workspace = true } log = { workspace = true } filecheck = { workspace = true } tempfile = { workspace = true } -tokio = { workspace = true, features = ["rt", "time", "macros", "rt-multi-thread"] } +tokio = { workspace = true, features = [ + "rt", + "time", + "macros", + "rt-multi-thread", +] } wast = { workspace = true } criterion = { workspace = true } num_cpus = "1.17.0" @@ -110,7 +129,10 @@ wat = { workspace = true } rayon = "1.5.0" wasmtime-wast = { workspace = true, features = ['component-model'] } wasmtime-component-util = { workspace = true } -wasmtime-test-util = { workspace = true, features = ['wasmtime-wast', 'component'] } +wasmtime-test-util = { workspace = true, features = [ + 'wasmtime-wast', + 'component', +] } bstr = "1.6.0" libc = { workspace = true } serde = { workspace = true } @@ -120,7 +142,11 @@ test-programs-artifacts = { workspace = true } bytesize = "2.0.1" wit-component = { workspace = true } cranelift-filetests = { workspace = true } -cranelift-codegen = { workspace = true, features = ["disas", "trace-log", "timing"] } +cranelift-codegen = { workspace = true, features = [ + "disas", + "trace-log", + "timing", +] } cranelift-reader = { workspace = true } toml = { workspace = true } similar = { workspace = true } @@ -180,9 +206,7 @@ members = [ "fuzz", "winch/codegen", ] -exclude = [ - 'docs/rust_wasi_markdown_parser', -] +exclude = ['docs/rust_wasi_markdown_parser'] [workspace.package] version = "41.0.0" @@ -265,8 +289,8 @@ wasmtime-wmemcheck = { path = "crates/wmemcheck", version = "=41.0.0", package = wasmtime-c-api-macros = { path = "crates/c-api-macros", version = "=41.0.0", package = 'wasmtime-internal-c-api-macros' } wasmtime-cache = { path = "crates/cache", version = "=41.0.0", package = 'wasmtime-internal-cache' } wasmtime-cranelift = { path = "crates/cranelift", version = "=41.0.0", package = 'wasmtime-internal-cranelift' } -wasmtime-winch = { path = "crates/winch", version = "=41.0.0", package = 'wasmtime-internal-winch' } -wasmtime-explorer = { path = "crates/explorer", version = "=41.0.0", package = 'wasmtime-internal-explorer' } +wasmtime-winch = { path = "crates/winch", version = "=41.0.0", package = 'wasmtime-internal-winch' } +wasmtime-explorer = { path = "crates/explorer", version = "=41.0.0", package = 'wasmtime-internal-explorer' } wasmtime-fiber = { path = "crates/fiber", version = "=41.0.0", package = 'wasmtime-internal-fiber' } wasmtime-jit-debug = { path = "crates/jit-debug", version = "=41.0.0", package = 'wasmtime-internal-jit-debug' } wasmtime-component-util = { path = "crates/component-util", version = "=41.0.0", package = 'wasmtime-internal-component-util' } @@ -275,7 +299,7 @@ wasmtime-versioned-export-macros = { path = "crates/versioned-export-macros", ve wasmtime-slab = { path = "crates/slab", version = "=41.0.0", package = 'wasmtime-internal-slab' } wasmtime-jit-icache-coherence = { path = "crates/jit-icache-coherence", version = "=41.0.0", package = 'wasmtime-internal-jit-icache-coherence' } wasmtime-wit-bindgen = { path = "crates/wit-bindgen", version = "=41.0.0", package = 'wasmtime-internal-wit-bindgen' } -wasmtime-math = { path = "crates/math", version = "=41.0.0", package = 'wasmtime-internal-math' } +wasmtime-math = { path = "crates/math", version = "=41.0.0", package = 'wasmtime-internal-math' } wasmtime-unwinder = { path = "crates/unwinder", version = "=41.0.0", package = 'wasmtime-internal-unwinder' } wasmtime-debugger = { path = "crates/debugger", version = "=41.0.0", package = "wasmtime-internal-debugger" } wasmtime-wizer = { path = "crates/wizer", version = "41.0.0" } @@ -291,7 +315,10 @@ pulley-macros = { path = 'pulley/macros', version = "=41.0.0" } # Cranelift crates in this workspace cranelift-assembler-x64 = { path = "cranelift/assembler-x64", version = "0.128.0" } -cranelift-codegen = { path = "cranelift/codegen", version = "0.128.0", default-features = false, features = ["std", "unwind"] } +cranelift-codegen = { path = "cranelift/codegen", version = "0.128.0", default-features = false, features = [ + "std", + "unwind", +] } cranelift-frontend = { path = "cranelift/frontend", version = "0.128.0" } cranelift-entity = { path = "cranelift/entity", version = "0.128.0" } cranelift-native = { path = "cranelift/native", version = "0.128.0" } @@ -304,7 +331,7 @@ cranelift-jit = { path = "cranelift/jit", version = "0.128.0" } cranelift-fuzzgen = { path = "cranelift/fuzzgen" } cranelift-bforest = { path = "cranelift/bforest", version = "0.128.0" } cranelift-bitset = { path = "cranelift/bitset", version = "0.128.0" } -cranelift-control = { path = "cranelift/control", version = "0.128.0" } +cranelift-control = { path = "cranelift/control", version = "0.128.0", default-features = false } cranelift-srcgen = { path = "cranelift/srcgen", version = "0.128.0" } cranelift = { path = "cranelift/umbrella", version = "0.128.0" } @@ -322,7 +349,7 @@ component-async-tests = { path = "crates/misc/component-async-tests" } # Bytecode Alliance maintained dependencies: # --------------------------- -regalloc2 = "0.13.3" +regalloc2 = { version = "0.13.3", default-features = false } wasip1 = { version = "1.0.0", default-features = false } # cap-std family: @@ -343,7 +370,9 @@ wit-bindgen = { version = "0.50.0", default-features = false } wit-bindgen-rust-macro = { version = "0.50.0", default-features = false } # wasm-tools family: -wasmparser = { version = "0.243.0", default-features = false, features = ['simd'] } +wasmparser = { version = "0.243.0", default-features = false, features = [ + 'simd', +] } wat = "1.243.0" wast = "243.0.0" wasmprinter = "0.243.0" @@ -362,14 +391,20 @@ arbitrary = "1.4.2" backtrace = "0.3.75" mutatis = "0.3.2" cc = "1.2.41" -object = { version = "0.37.3", default-features = false, features = ['read_core', 'elf'] } +object = { version = "0.37.3", default-features = false, features = [ + 'read_core', + 'elf', +] } gimli = { version = "0.32.3", default-features = false, features = ['read'] } addr2line = { version = "0.25.1", default-features = false } anyhow = { version = "1.0.100", default-features = false } windows-sys = "0.61.2" env_logger = "0.11.5" log = { version = "0.4.28", default-features = false } -clap = { version = "4.5.48", default-features = false, features = ["std", "derive"] } +clap = { version = "4.5.48", default-features = false, features = [ + "std", + "derive", +] } clap_complete = "4.5.58" hashbrown = { version = "0.15", default-features = false } capstone = "0.13.0" @@ -398,7 +433,7 @@ tempfile = "3.23.0" filecheck = "0.5.0" libc = { version = "0.2.177", default-features = true } file-per-thread-logger = "0.2.0" -tokio = { version = "1.48.0", features = [ "rt", "time" ] } +tokio = { version = "1.48.0", features = ["rt", "time"] } hyper = "1.7.0" http = "1.3.1" http-body = "1.0.1" @@ -409,12 +444,22 @@ indexmap = { version = "2.11.4", default-features = false } syn = "2.0.106" quote = "1.0.41" proc-macro2 = "1.0.101" -test-log = { version = "0.2.18", default-features = false, features = ["trace"] } -tracing-subscriber = { version = "0.3.20", default-features = false, features = ['fmt', 'env-filter', 'ansi', 'tracing-log'] } +test-log = { version = "0.2.18", default-features = false, features = [ + "trace", +] } +tracing-subscriber = { version = "0.3.20", default-features = false, features = [ + 'fmt', + 'env-filter', + 'ansi', + 'tracing-log', +] } url = "2.5.7" postcard = { version = "1.1.3", default-features = false, features = ['alloc'] } -criterion = { version = "0.7.0", default-features = false, features = ["html_reports", "rayon"] } -rustc-hash = "2.1.1" +criterion = { version = "0.7.0", default-features = false, features = [ + "html_reports", + "rayon", +] } +rustc-hash = { version = "2.1.1", default-features = false } libtest-mimic = "0.8.1" semver = { version = "1.0.27", default-features = false } ittapi = "0.4.0" @@ -529,10 +574,19 @@ disable-logging = ["log/max_level_off", "tracing/max_level_off"] wasi-nn = ["dep:wasmtime-wasi-nn"] wasi-tls = ["dep:wasmtime-wasi-tls"] wasi-threads = ["dep:wasmtime-wasi-threads", "threads"] -wasi-http = ["component-model", "dep:wasmtime-wasi-http", "dep:tokio", "dep:hyper", "wasmtime-wasi-http/default-send-request"] +wasi-http = [ + "component-model", + "dep:wasmtime-wasi-http", + "dep:tokio", + "dep:hyper", + "wasmtime-wasi-http/default-send-request", +] wasi-config = ["dep:wasmtime-wasi-config"] wasi-keyvalue = ["dep:wasmtime-wasi-keyvalue"] -pooling-allocator = ["wasmtime/pooling-allocator", "wasmtime-cli-flags/pooling-allocator"] +pooling-allocator = [ + "wasmtime/pooling-allocator", + "wasmtime-cli-flags/pooling-allocator", +] component-model = [ "wasmtime/component-model", "wasmtime-wast?/component-model", @@ -554,7 +608,10 @@ gc = ["wasmtime-cli-flags/gc", "wasmtime/gc"] gc-drc = ["gc", "wasmtime/gc-drc", "wasmtime-cli-flags/gc-drc"] gc-null = ["gc", "wasmtime/gc-null", "wasmtime-cli-flags/gc-null"] pulley = ["wasmtime-cli-flags/pulley"] -stack-switching = ["wasmtime/stack-switching", "wasmtime-cli-flags/stack-switching"] +stack-switching = [ + "wasmtime/stack-switching", + "wasmtime-cli-flags/stack-switching", +] debug = ["wasmtime-cli-flags/debug", "wasmtime/debug"] # CLI subcommands for the `wasmtime` executable. See `wasmtime $cmd --help` diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 32112265eb68..03040f037d3c 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -30,7 +30,7 @@ cranelift-entity = { workspace = true } cranelift-bforest = { workspace = true } cranelift-bitset = { workspace = true } cranelift-control = { workspace = true } -hashbrown = { workspace = true } +hashbrown = { workspace = true, features = ["default-hasher"] } target-lexicon = { workspace = true } log = { workspace = true } serde = { workspace = true, optional = true } @@ -71,7 +71,7 @@ std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # deprecated (we (i) always use hashbrown, and (ii) don't support a # no_std build anymore). The feature remains for backward # compatibility as a no-op. -core = [] +core = ["cranelift-assembler-x64/core"] # Enable the `to_capstone` method on TargetIsa, for constructing a Capstone # context, and the `disassemble` method on `MachBufferFinalized`. diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 79b9432960af..051f26ea451c 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1,3 +1,4 @@ + //! Immediate operands for Cranelift instructions //! //! This module defines the types of immediate operands that can appear on Cranelift instructions. diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index ada37b03ccbb..7b842ac7e4ab 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -15,6 +15,7 @@ pub mod winx64; pub mod winarm64; /// CFA-based unwind information used on SystemV. +#[cfg(feature = "unwind")] pub type CfaUnwindInfo = systemv::UnwindInfo; /// Expected unwind info type. diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs new file mode 100644 index 000000000000..b2d13852bc08 --- /dev/null +++ b/cranelift/codegen/src/prelude.rs @@ -0,0 +1,4 @@ +use alloc::format; +use alloc::string::{String, ToString}; +use alloc::vec::Vec; +use alloc::vec; From cf49e28be239a29eb0b43afeb591f45a28dccea6 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 18:42:45 +0100 Subject: [PATCH 22/61] Most of the files now work with no_std --- cranelift/codegen/src/alias_analysis.rs | 1 + cranelift/codegen/src/binemit/mod.rs | 1 + cranelift/codegen/src/cfg_printer.rs | 1 + cranelift/codegen/src/constant_hash.rs | 1 + cranelift/codegen/src/context.rs | 1 + cranelift/codegen/src/ctxhash.rs | 1 + cranelift/codegen/src/cursor.rs | 1 + cranelift/codegen/src/data_value.rs | 1 + cranelift/codegen/src/dbg.rs | 1 + cranelift/codegen/src/dominator_tree.rs | 1 + cranelift/codegen/src/dominator_tree/simple.rs | 1 + cranelift/codegen/src/egraph.rs | 1 + cranelift/codegen/src/egraph/cost.rs | 1 + cranelift/codegen/src/egraph/elaborate.rs | 1 + cranelift/codegen/src/flowgraph.rs | 1 + cranelift/codegen/src/incremental_cache.rs | 1 + cranelift/codegen/src/inline.rs | 1 + cranelift/codegen/src/inst_predicates.rs | 1 + cranelift/codegen/src/ir/atomic_rmw_op.rs | 1 + cranelift/codegen/src/ir/builder.rs | 1 + cranelift/codegen/src/ir/condcodes.rs | 1 + cranelift/codegen/src/ir/constant.rs | 1 + cranelift/codegen/src/ir/debug_tags.rs | 1 + cranelift/codegen/src/ir/dfg.rs | 1 + cranelift/codegen/src/ir/dynamic_type.rs | 1 + cranelift/codegen/src/ir/entities.rs | 1 + cranelift/codegen/src/ir/exception_table.rs | 1 + cranelift/codegen/src/ir/extfunc.rs | 1 + cranelift/codegen/src/ir/extname.rs | 1 + cranelift/codegen/src/ir/function.rs | 1 + cranelift/codegen/src/ir/globalvalue.rs | 1 + cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/ir/instructions.rs | 1 + cranelift/codegen/src/ir/jumptable.rs | 1 + cranelift/codegen/src/ir/known_symbol.rs | 1 + cranelift/codegen/src/ir/layout.rs | 1 + cranelift/codegen/src/ir/libcall.rs | 1 + cranelift/codegen/src/ir/memflags.rs | 1 + cranelift/codegen/src/ir/memtype.rs | 1 + cranelift/codegen/src/ir/mod.rs | 1 + cranelift/codegen/src/ir/pcc.rs | 1 + cranelift/codegen/src/ir/progpoint.rs | 1 + cranelift/codegen/src/ir/sourceloc.rs | 1 + cranelift/codegen/src/ir/stackslot.rs | 1 + cranelift/codegen/src/ir/trapcode.rs | 1 + cranelift/codegen/src/ir/types.rs | 1 + cranelift/codegen/src/ir/user_stack_maps.rs | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/args.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/emit.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/unwind.rs | 1 + .../codegen/src/isa/aarch64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/aarch64/lower.rs | 1 + cranelift/codegen/src/isa/aarch64/lower/isle.rs | 1 + .../src/isa/aarch64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/pcc.rs | 1 + cranelift/codegen/src/isa/aarch64/settings.rs | 1 + cranelift/codegen/src/isa/call_conv.rs | 1 + cranelift/codegen/src/isa/mod.rs | 1 + cranelift/codegen/src/isa/pulley32.rs | 1 + cranelift/codegen/src/isa/pulley64.rs | 1 + cranelift/codegen/src/isa/pulley_shared/abi.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/args.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/emit.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/regs.rs | 1 + cranelift/codegen/src/isa/pulley_shared/lower.rs | 1 + .../codegen/src/isa/pulley_shared/lower/isle.rs | 1 + .../isa/pulley_shared/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/pulley_shared/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/settings.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/args.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/emit.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/encode.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/imms.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/regs.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/unwind.rs | 1 + .../codegen/src/isa/riscv64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 + cranelift/codegen/src/isa/riscv64/lower.rs | 1 + cranelift/codegen/src/isa/riscv64/lower/isle.rs | 1 + .../src/isa/riscv64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/settings.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 1 + cranelift/codegen/src/isa/s390x/inst/args.rs | 1 + cranelift/codegen/src/isa/s390x/inst/emit.rs | 1 + cranelift/codegen/src/isa/s390x/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 + cranelift/codegen/src/isa/s390x/inst/mod.rs | 1 + cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 + cranelift/codegen/src/isa/s390x/inst/unwind.rs | 1 + .../codegen/src/isa/s390x/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/s390x/lower.rs | 1 + cranelift/codegen/src/isa/s390x/lower/isle.rs | 1 + .../src/isa/s390x/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/s390x/mod.rs | 1 + cranelift/codegen/src/isa/s390x/settings.rs | 1 + cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/isa/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/unwind/winarm64.rs | 1 + cranelift/codegen/src/isa/unwind/winx64.rs | 1 + cranelift/codegen/src/isa/winch.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit_state.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 1 + cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/isa/x64/inst/stack_switch.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs | 1 + cranelift/codegen/src/isa/x64/lower.rs | 1 + cranelift/codegen/src/isa/x64/lower/isle.rs | 1 + .../codegen/src/isa/x64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 1 + cranelift/codegen/src/isa/x64/pcc.rs | 1 + cranelift/codegen/src/isa/x64/settings.rs | 1 + cranelift/codegen/src/isle_prelude.rs | 1 + cranelift/codegen/src/legalizer/branch_to_trap.rs | 1 + cranelift/codegen/src/legalizer/globalvalue.rs | 1 + cranelift/codegen/src/legalizer/mod.rs | 1 + cranelift/codegen/src/lib.rs | 3 +++ cranelift/codegen/src/loop_analysis.rs | 1 + cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/blockorder.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 1 + cranelift/codegen/src/machinst/compile.rs | 1 + cranelift/codegen/src/machinst/helpers.rs | 1 + cranelift/codegen/src/machinst/inst_common.rs | 1 + cranelift/codegen/src/machinst/isle.rs | 1 + cranelift/codegen/src/machinst/lower.rs | 1 + cranelift/codegen/src/machinst/mod.rs | 1 + cranelift/codegen/src/machinst/pcc.rs | 1 + cranelift/codegen/src/machinst/reg.rs | 1 + cranelift/codegen/src/machinst/valueregs.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/nan_canonicalization.rs | 1 + cranelift/codegen/src/opts.rs | 1 + cranelift/codegen/src/opts/div_const.rs | 1 + cranelift/codegen/src/opts/generated_code.rs | 1 + cranelift/codegen/src/prelude.rs | 12 ++++++++---- cranelift/codegen/src/print_errors.rs | 1 + cranelift/codegen/src/ranges.rs | 1 + cranelift/codegen/src/remove_constant_phis.rs | 1 + cranelift/codegen/src/result.rs | 1 + cranelift/codegen/src/scoped_hash_map.rs | 1 + cranelift/codegen/src/settings.rs | 1 + cranelift/codegen/src/souper_harvest.rs | 1 + cranelift/codegen/src/take_and_replace.rs | 1 + cranelift/codegen/src/timing.rs | 1 + cranelift/codegen/src/traversals.rs | 1 + cranelift/codegen/src/unreachable_code.rs | 1 + cranelift/codegen/src/value_label.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 1 + cranelift/codegen/src/write.rs | 1 + 167 files changed, 176 insertions(+), 4 deletions(-) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index 93adce052c9f..b915db0f79e7 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -400,3 +400,4 @@ fn get_ext_opcode(op: Opcode) -> Option { _ => Some(op), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs index cd34c0b3ff13..022eb7db5fca 100644 --- a/cranelift/codegen/src/binemit/mod.rs +++ b/cranelift/codegen/src/binemit/mod.rs @@ -190,3 +190,4 @@ pub struct CodeInfo { /// Number of bytes in total. pub total_size: CodeOffset, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/cfg_printer.rs b/cranelift/codegen/src/cfg_printer.rs index ef71b63ca712..8c07f0ac478b 100644 --- a/cranelift/codegen/src/cfg_printer.rs +++ b/cranelift/codegen/src/cfg_printer.rs @@ -81,3 +81,4 @@ impl<'a> Display for CFGPrinter<'a> { self.write(f) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/constant_hash.rs b/cranelift/codegen/src/constant_hash.rs index 1de2a2edb43e..be018675b5e2 100644 --- a/cranelift/codegen/src/constant_hash.rs +++ b/cranelift/codegen/src/constant_hash.rs @@ -60,3 +60,4 @@ pub fn probe + ?Sized>( idx += step; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index c37de05497bc..46267cb446d2 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -391,3 +391,4 @@ impl Context { self.verify_if(fisa) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 7148046ae9c1..7e6b852907f3 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -223,3 +223,4 @@ mod test { assert_eq!(*map.get(&k0, &ctx).unwrap(), 84); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/cursor.rs b/cranelift/codegen/src/cursor.rs index ae7b0ea874ad..b1bec22fa159 100644 --- a/cranelift/codegen/src/cursor.rs +++ b/cranelift/codegen/src/cursor.rs @@ -687,3 +687,4 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> { &mut self.func.dfg } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index a2e69a724e1b..26a66d53694e 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -420,3 +420,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dbg.rs b/cranelift/codegen/src/dbg.rs index 4796f3967b91..8a0da7a24aed 100644 --- a/cranelift/codegen/src/dbg.rs +++ b/cranelift/codegen/src/dbg.rs @@ -26,3 +26,4 @@ where } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 23d099a4251a..90e700d0097d 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -771,3 +771,4 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree/simple.rs b/cranelift/codegen/src/dominator_tree/simple.rs index 853158bc80b1..9abc47e4df95 100644 --- a/cranelift/codegen/src/dominator_tree/simple.rs +++ b/cranelift/codegen/src/dominator_tree/simple.rs @@ -582,3 +582,4 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph.rs index 46fdaf36985b..a8d6a80ee3b2 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph.rs @@ -1110,3 +1110,4 @@ pub(crate) struct Stats { pub(crate) elaborate_func_post_insts: u64, pub(crate) eclass_size_limit: u64, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index 062196964c96..f2f2048497b9 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -236,3 +236,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index 9328354b2dc2..ec617344b9ba 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -865,3 +865,4 @@ impl<'a> Elaborator<'a> { self.stats.elaborate_func_post_insts += self.func.dfg.num_insts() as u64; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/flowgraph.rs b/cranelift/codegen/src/flowgraph.rs index 6478dfddbf90..9358c851b4e3 100644 --- a/cranelift/codegen/src/flowgraph.rs +++ b/cranelift/codegen/src/flowgraph.rs @@ -347,3 +347,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index a597d18869ce..973cca13ece1 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -239,3 +239,4 @@ pub fn try_finish_recompile(func: &Function, bytes: &[u8]) -> Result Err(RecompileError::Deserialize(err)), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/inline.rs b/cranelift/codegen/src/inline.rs index ac150c598980..6e6756871545 100644 --- a/cranelift/codegen/src/inline.rs +++ b/cranelift/codegen/src/inline.rs @@ -1584,3 +1584,4 @@ fn create_constants(allocs: &mut InliningAllocs, func: &mut ir::Function, callee allocs.constants[*callee_constant] = Some(inlined_constant).into(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs index 7b42e1728663..91cb01ca7cf3 100644 --- a/cranelift/codegen/src/inst_predicates.rs +++ b/cranelift/codegen/src/inst_predicates.rs @@ -215,3 +215,4 @@ pub(crate) fn visit_block_succs( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/atomic_rmw_op.rs b/cranelift/codegen/src/ir/atomic_rmw_op.rs index 0317fc00d2c1..ea6a16b7d969 100644 --- a/cranelift/codegen/src/ir/atomic_rmw_op.rs +++ b/cranelift/codegen/src/ir/atomic_rmw_op.rs @@ -102,3 +102,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/builder.rs b/cranelift/codegen/src/ir/builder.rs index 24d9beaee660..c36673bd79ee 100644 --- a/cranelift/codegen/src/ir/builder.rs +++ b/cranelift/codegen/src/ir/builder.rs @@ -280,3 +280,4 @@ mod tests { .Trap(Opcode::Return, I32, TrapCode::BAD_CONVERSION_TO_INTEGER); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index 009f95bf391c..454423f7a189 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -402,3 +402,4 @@ mod tests { assert_eq!("bogus".parse::(), Err(())); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index 67310cd9462f..5612510c8f33 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -485,3 +485,4 @@ mod tests { assert_eq!(Ieee128::try_from(&constant).unwrap().bits(), value.bits()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/debug_tags.rs b/cranelift/codegen/src/ir/debug_tags.rs index 39d137c2973b..d2ca049f6c53 100644 --- a/cranelift/codegen/src/ir/debug_tags.rs +++ b/cranelift/codegen/src/ir/debug_tags.rs @@ -139,3 +139,4 @@ impl core::fmt::Display for DebugTag { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dfg.rs b/cranelift/codegen/src/ir/dfg.rs index 3dd2ad4211c3..e48cdd42d990 100644 --- a/cranelift/codegen/src/ir/dfg.rs +++ b/cranelift/codegen/src/ir/dfg.rs @@ -1882,3 +1882,4 @@ mod tests { assert_eq!(v1, func.dfg.inst_args(call_inst_dup)[0]); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dynamic_type.rs b/cranelift/codegen/src/ir/dynamic_type.rs index 53027c196945..369bcc74eeba 100644 --- a/cranelift/codegen/src/ir/dynamic_type.rs +++ b/cranelift/codegen/src/ir/dynamic_type.rs @@ -52,3 +52,4 @@ pub fn dynamic_to_fixed(ty: Type) -> Type { _ => unreachable!("unhandled type: {}", ty), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/entities.rs b/cranelift/codegen/src/ir/entities.rs index cbb8f3097aff..a1ab10662d7d 100644 --- a/cranelift/codegen/src/ir/entities.rs +++ b/cranelift/codegen/src/ir/entities.rs @@ -562,3 +562,4 @@ mod tests { assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 4130f23792b4..80730652054a 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -287,3 +287,4 @@ impl<'a> Display for DisplayExceptionTable<'a> { Ok(()) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extfunc.rs b/cranelift/codegen/src/ir/extfunc.rs index ebfaf3a8ddaf..61880e27fc84 100644 --- a/cranelift/codegen/src/ir/extfunc.rs +++ b/cranelift/codegen/src/ir/extfunc.rs @@ -418,3 +418,4 @@ mod tests { assert_eq!(sig.to_string(), "(i32, i32x4) -> f32, i8 windows_fastcall"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index d28ebcb4e7b2..e80fb4cf34b4 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -336,3 +336,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/function.rs b/cranelift/codegen/src/ir/function.rs index 80926edcdf1c..296d0c9cf938 100644 --- a/cranelift/codegen/src/ir/function.rs +++ b/cranelift/codegen/src/ir/function.rs @@ -517,3 +517,4 @@ impl<'a> fmt::Debug for DisplayFunctionSpec<'a> { write_function_spec(fmt, self.0) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/globalvalue.rs b/cranelift/codegen/src/ir/globalvalue.rs index 89120c8b8364..8ea7372c7349 100644 --- a/cranelift/codegen/src/ir/globalvalue.rs +++ b/cranelift/codegen/src/ir/globalvalue.rs @@ -145,3 +145,4 @@ impl fmt::Display for GlobalValueData { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 051f26ea451c..ce89abd2307d 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1959,3 +1959,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 80c04e48e6fb..6a95b1ce9975 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -1538,3 +1538,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 5bdad87d941f..85d6d77b1a51 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -173,3 +173,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/known_symbol.rs b/cranelift/codegen/src/ir/known_symbol.rs index c3d17501a39b..6c594b7faff3 100644 --- a/cranelift/codegen/src/ir/known_symbol.rs +++ b/cranelift/codegen/src/ir/known_symbol.rs @@ -45,3 +45,4 @@ mod tests { assert_eq!("CoffTlsIndex".parse(), Ok(KnownSymbol::CoffTlsIndex)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/layout.rs b/cranelift/codegen/src/ir/layout.rs index 1284ab65676e..2a2d139018fe 100644 --- a/cranelift/codegen/src/ir/layout.rs +++ b/cranelift/codegen/src/ir/layout.rs @@ -1193,3 +1193,4 @@ mod tests { assert_eq!(layout.pp_cmp(i3, i2), Ordering::Greater) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/libcall.rs b/cranelift/codegen/src/ir/libcall.rs index 6b60dfd07d27..3cf1ebb2d7f2 100644 --- a/cranelift/codegen/src/ir/libcall.rs +++ b/cranelift/codegen/src/ir/libcall.rs @@ -230,3 +230,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memflags.rs b/cranelift/codegen/src/ir/memflags.rs index 45f32ce85fd2..726004dcd59f 100644 --- a/cranelift/codegen/src/ir/memflags.rs +++ b/cranelift/codegen/src/ir/memflags.rs @@ -485,3 +485,4 @@ mod tests { assert!(big.set_by_name("table").is_err()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index b7b0d7e2db1e..8501c9bb73a3 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -188,3 +188,4 @@ impl MemoryTypeData { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/mod.rs b/cranelift/codegen/src/ir/mod.rs index eca17e7badda..db671b366444 100644 --- a/cranelift/codegen/src/ir/mod.rs +++ b/cranelift/codegen/src/ir/mod.rs @@ -117,3 +117,4 @@ pub enum ValueLabelAssignments { value: Value, }, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index d1bf7ea62dba..f9062a1ddad6 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -1679,3 +1679,4 @@ pub fn check_vcode_facts( } Ok(()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/progpoint.rs b/cranelift/codegen/src/ir/progpoint.rs index 84d394276f67..dafcd16d7c5d 100644 --- a/cranelift/codegen/src/ir/progpoint.rs +++ b/cranelift/codegen/src/ir/progpoint.rs @@ -73,3 +73,4 @@ mod tests { assert_eq!(pp2.to_string(), "block3"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/sourceloc.rs b/cranelift/codegen/src/ir/sourceloc.rs index 6704574d0d09..38efbe2939aa 100644 --- a/cranelift/codegen/src/ir/sourceloc.rs +++ b/cranelift/codegen/src/ir/sourceloc.rs @@ -115,3 +115,4 @@ mod tests { assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 1ad2a5d7d871..3c10fdc98026 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -249,3 +249,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/trapcode.rs b/cranelift/codegen/src/ir/trapcode.rs index e3fbcfbb4a50..f990f312b94f 100644 --- a/cranelift/codegen/src/ir/trapcode.rs +++ b/cranelift/codegen/src/ir/trapcode.rs @@ -145,3 +145,4 @@ mod tests { assert_eq!("users".parse::(), Err(())); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs index bc7704cf0662..48e98fd352d2 100644 --- a/cranelift/codegen/src/ir/types.rs +++ b/cranelift/codegen/src/ir/types.rs @@ -622,3 +622,4 @@ mod tests { assert_eq!(Type::int_with_byte_size(evil), None); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs index 6ad9b697cd02..92aaa198effa 100644 --- a/cranelift/codegen/src/ir/user_stack_maps.rs +++ b/cranelift/codegen/src/ir/user_stack_maps.rs @@ -197,3 +197,4 @@ impl UserStackMap { }) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 33e986347018..89b7546e0a0d 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -1633,3 +1633,4 @@ fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv { env } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index a382a5ef725a..d912aee4dd79 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -724,3 +724,4 @@ impl TestBitAndBranchKind { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 06e0eb017708..b5bb377591df 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -3685,3 +3685,4 @@ fn emit_return_call_common_sequence( sink.put4(key.enc_auti_hint()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index baa42a265cb2..fdca784dd038 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -7970,3 +7970,4 @@ fn test_cond_invert() { assert_eq!(cond.invert().invert(), cond); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index fcd67deed576..69a1ca5312e7 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -1240,3 +1240,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 9ccfb7ad985c..7e02b79c219a 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -3114,3 +3114,4 @@ mod tests { assert_eq!(expected, core::mem::size_of::()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 7db69df4ebe4..c625d99d964d 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -279,3 +279,4 @@ pub fn pretty_print_vreg_vector(reg: Reg, size: VectorSize) -> String { pub fn pretty_print_vreg_element(reg: Reg, idx: usize, size: ScalarSize) -> String { show_vreg_element(reg, idx as u8, size) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs index 9378c46fa53b..25a095983c42 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs @@ -175,3 +175,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs index 6d51a380433f..99c9f2f95592 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.rs +++ b/cranelift/codegen/src/isa/aarch64/lower.rs @@ -143,3 +143,4 @@ impl LowerBackend for AArch64Backend { type FactFlowState = pcc::FactFlowState; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 31800f10dafb..6898f2852403 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -860,3 +860,4 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.backend.flags.is_pic() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 2e0f7bd77dda..3867a060b7f3 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -14,3 +14,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_aarch64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index dc3ab2c92c3d..707f88bc1b81 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -279,3 +279,4 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs index e5ee1919803e..3b5e31d11c0e 100644 --- a/cranelift/codegen/src/isa/aarch64/pcc.rs +++ b/cranelift/codegen/src/isa/aarch64/pcc.rs @@ -568,3 +568,4 @@ fn check_store_addr( let _output_fact = ctx.store(&fact, ty, None)?; Ok(()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/settings.rs b/cranelift/codegen/src/isa/aarch64/settings.rs index 2cda69446ff3..21031399b5eb 100644 --- a/cranelift/codegen/src/isa/aarch64/settings.rs +++ b/cranelift/codegen/src/isa/aarch64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/arm64.rs`. include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/call_conv.rs b/cranelift/codegen/src/isa/call_conv.rs index a8f6ce50203e..65e6c514c830 100644 --- a/cranelift/codegen/src/isa/call_conv.rs +++ b/cranelift/codegen/src/isa/call_conv.rs @@ -153,3 +153,4 @@ impl str::FromStr for CallConv { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2bc2033983ef..2c31830e139a 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -499,3 +499,4 @@ impl Debug for &dyn TargetIsa { ) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley32.rs b/cranelift/codegen/src/isa/pulley32.rs index b337274660d0..e3467275472e 100644 --- a/cranelift/codegen/src/isa/pulley32.rs +++ b/cranelift/codegen/src/isa/pulley32.rs @@ -11,3 +11,4 @@ impl PulleyTargetKind for Pulley32 { PointerWidth::PointerWidth32 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley64.rs b/cranelift/codegen/src/isa/pulley64.rs index 31b1d08a04b2..234840c45eb5 100644 --- a/cranelift/codegen/src/isa/pulley64.rs +++ b/cranelift/codegen/src/isa/pulley64.rs @@ -11,3 +11,4 @@ impl PulleyTargetKind for Pulley64 { PointerWidth::PointerWidth64 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index cd7427a4e345..efb7cd7f6628 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -986,3 +986,4 @@ fn create_reg_environment() -> MachineEnv { scratch_by_class: [None, None, None], } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index 440699490b8e..3520abec8d24 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -780,3 +780,4 @@ impl fmt::Display for AddrG32Bne { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs index 74082b4260c3..25614218b03b 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs @@ -707,3 +707,4 @@ fn patch_pc_rel_offset

( assert_eq!(*chunk, [0, 0, 0, 0]); *chunk = (end - start - 4).to_le_bytes(); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index d76705a7fb9f..497ba5e2031e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -952,3 +952,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs index 90f7d36e104b..069050e7cd55 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs @@ -162,3 +162,4 @@ define_registers! { v_reg(30) => v30, writable_v30; v_reg(31) => v31, writable_v31; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.rs b/cranelift/codegen/src/isa/pulley_shared/lower.rs index 8dd5a0cea50c..b436d1d3e46e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower.rs @@ -34,3 +34,4 @@ where type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs index d72b6a023789..baa93a5eb1bc 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs @@ -327,3 +327,4 @@ where let mut isle_ctx = PulleyIsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs index 45dd7050dc3c..6b0853db8f25 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_pulley_shared.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 1c0b736c15f3..8bcaa2eae62a 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -313,3 +313,4 @@ impl PulleyFlags { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/settings.rs b/cranelift/codegen/src/isa/pulley_shared/settings.rs index 5d4fd19ed116..d611e3a6f2a5 100644 --- a/cranelift/codegen/src/isa/pulley_shared/settings.rs +++ b/cranelift/codegen/src/isa/pulley_shared/settings.rs @@ -14,3 +14,4 @@ use core::fmt; include!(concat!(env!("OUT_DIR"), "/settings-pulley.rs")); impl IsaFlags for Flags {} +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index ca08f1c0b58a..f14805735aff 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -1056,3 +1056,4 @@ impl Riscv64MachineDeps { insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index 918a4854b3a3..d710f4348e46 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -1946,3 +1946,4 @@ impl ZcbMemOp { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 5e631c3af1d3..714271546539 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -2885,3 +2885,4 @@ fn return_call_emit_impl( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 3b0cf59b633f..09880464c68e 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -2283,3 +2283,4 @@ fn riscv64_worst_case_instruction_size() { println!("calculate max size is {} , inst is {:?}", max.0, max.1); assert!(max.0 <= Inst::worst_case_size()); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/encode.rs b/cranelift/codegen/src/isa/riscv64/inst/encode.rs index 048fc2af05b5..b167f319ccfe 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs @@ -718,3 +718,4 @@ pub fn encode_fp_rrrr( funct7, ) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 92a8ceb60b83..5e9f0faeee45 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -371,3 +371,4 @@ mod test { assert!(Inst::imm_min() == i32::MIN as i64 - 2048); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 119ff1fd48d2..9043aa77bb3b 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -1943,3 +1943,4 @@ mod test { assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/regs.rs b/cranelift/codegen/src/isa/riscv64/inst/regs.rs index 76493732bfe1..d1e9fa7cd00f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/regs.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/regs.rs @@ -151,3 +151,4 @@ pub const fn pf_reg(enc: usize) -> PReg { pub const fn pv_reg(enc: usize) -> PReg { PReg::new(enc, RegClass::Vector) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs index 0b2ef040b19c..0edc32ba221f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs @@ -171,3 +171,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 269e6481b506..dcbda4aa1850 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -1148,3 +1148,4 @@ pub trait VecInstOverlapInfo { self.forbids_src_dst_overlaps() || (mask.is_enabled() && self.forbids_mask_dst_overlaps()) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower.rs b/cranelift/codegen/src/isa/riscv64/lower.rs index 117778f820b3..8de92855b2f8 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.rs +++ b/cranelift/codegen/src/isa/riscv64/lower.rs @@ -33,3 +33,4 @@ impl LowerBackend for Riscv64Backend { type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index e0ef1971bdf3..6a8aed5eb907 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -751,3 +751,4 @@ pub(crate) fn lower_branch( let mut isle_ctx = RV64IsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs index ad8466108a3b..9fb78bfb80ca 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_riscv64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index a2c1ffe5691e..fa320acab489 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -293,3 +293,4 @@ fn isa_constructor( let backend = Riscv64Backend::new_with_flags(triple, shared_flags, isa_flags); Ok(backend.wrapped()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/settings.rs b/cranelift/codegen/src/isa/riscv64/settings.rs index c896dd5fe911..f4ca3fb3a88a 100644 --- a/cranelift/codegen/src/isa/riscv64/settings.rs +++ b/cranelift/codegen/src/isa/riscv64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/riscv64/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-riscv64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 4ca965cba2b5..5c30ddab3ff2 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -1628,3 +1628,4 @@ fn tail_create_machine_env() -> MachineEnv { scratch_by_class: [None, None, None], } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/args.rs b/cranelift/codegen/src/isa/s390x/inst/args.rs index 33e790673b61..5e114104b320 100644 --- a/cranelift/codegen/src/isa/s390x/inst/args.rs +++ b/cranelift/codegen/src/isa/s390x/inst/args.rs @@ -269,3 +269,4 @@ impl PrettyPrint for Cond { s.to_string() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index 5baef0fede8a..e218fe55454a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3559,3 +3559,4 @@ impl Inst { state.clear_post_insn(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index 569c16ac5c4d..aa4ab565eaef 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -13496,3 +13496,4 @@ fn test_s390x_binemit() { assert_eq!(expected_encoding, actual_encoding); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 9559f34ac7f8..edb66ba08196 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -200,3 +200,4 @@ impl PrettyPrint for UImm32Shifted { format!("{}", self.bits) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 26dc83d16bff..9159f435ea1e 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -3552,3 +3552,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index d3985bb9d20b..eebcb36a33df 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -184,3 +184,4 @@ pub fn pretty_print_regpair_mod_lo(rd: WritableRegPair, ri: Reg) -> String { pub fn pretty_print_fpr(reg: Reg) -> (String, Option) { (show_reg(reg), maybe_show_fpr(reg)) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind.rs b/cranelift/codegen/src/isa/s390x/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs index 6ae2c7e262d9..a37ca84767d9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs @@ -216,3 +216,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index 9af0b96147e5..c111eee9c915 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -28,3 +28,4 @@ impl LowerBackend for S390xBackend { type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index b3115fd7229e..56176476ecb8 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -862,3 +862,4 @@ fn condcode_is_signed(cc: IntCC) -> bool { IntCC::UnsignedLessThan => false, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index a6daad546b62..c32fdefdc440 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_s390x.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 674e179d4459..d7e97f6f896a 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -237,3 +237,4 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/settings.rs b/cranelift/codegen/src/isa/s390x/settings.rs index 5bf89030f19d..16a717f9e7c7 100644 --- a/cranelift/codegen/src/isa/s390x/settings.rs +++ b/cranelift/codegen/src/isa/s390x/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/s390x/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index 7b842ac7e4ab..cd98fb9b8222 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -249,3 +249,4 @@ impl<'a> Writer<'a> { self.offset += 4; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index 5989e0b2a12b..0fb19d0408c7 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -286,3 +286,4 @@ impl UnwindInfo { fde } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winarm64.rs b/cranelift/codegen/src/isa/unwind/winarm64.rs index 3d3cdd8fcf48..803867af2a85 100644 --- a/cranelift/codegen/src/isa/unwind/winarm64.rs +++ b/cranelift/codegen/src/isa/unwind/winarm64.rs @@ -315,3 +315,4 @@ pub(crate) fn create_unwind_info_from_insts( Ok(UnwindInfo { unwind_codes }) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winx64.rs b/cranelift/codegen/src/isa/unwind/winx64.rs index 38cb46b83b55..e352dc6351df 100644 --- a/cranelift/codegen/src/isa/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/unwind/winx64.rs @@ -310,3 +310,4 @@ fn ensure_unwind_offset(offset: u32) -> CodegenResult { } Ok(offset as u8) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index df8fdce35223..8e9bbf0efdc3 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -20,3 +20,4 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index cd07032c2bc2..e00689769b40 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -1346,3 +1346,4 @@ fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv { env } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 35c22ca49b3c..c5e6a117ec04 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -1061,3 +1061,4 @@ impl OperandSize { self.to_bytes() * 8 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 363f9194bd6f..2374d6e63b58 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -2193,3 +2193,4 @@ fn emit_lea( _ => lea(*dst.as_ref(), addr, sink), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_state.rs b/cranelift/codegen/src/isa/x64/inst/emit_state.rs index 426a17a2803b..98ffebf3f3be 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_state.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_state.rs @@ -53,3 +53,4 @@ impl EmitState { self.user_stack_map = None; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 9e47ea081b56..7d9e7a6e7eba 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -383,3 +383,4 @@ fn test_x64_emit() { assert_eq!(expected_encoding, actual_encoding, "{expected_printing}"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 434eee65a63a..82c7f089ed77 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -563,3 +563,4 @@ mod tests { assert_eq!(pair.to_string(None), "(%v500 <- %v400)"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index d2ef4c40949f..451529d81e11 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -1680,3 +1680,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 03671acfbc8f..867b26b6b929 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -175,3 +175,4 @@ pub fn pretty_print_reg(reg: Reg, size: u8) -> String { name } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs index 4c9400df41bf..d32c59dd9fee 100644 --- a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs +++ b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs @@ -47,3 +47,4 @@ pub fn control_context_layout() -> ControlContextLayout { pub fn payload_register() -> Reg { regs::rdi() } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind.rs b/cranelift/codegen/src/isa/x64/inst/unwind.rs index cb86c3b7ccd5..56289f082012 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind.rs @@ -3,3 +3,4 @@ pub(crate) mod systemv; #[cfg(feature = "unwind")] pub(crate) mod winx64; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs index 3f46843ab4f4..ecbe379cd7da 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs @@ -202,3 +202,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs index f848a5baf76f..f6d80f5e531f 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs @@ -14,3 +14,4 @@ impl crate::isa::unwind::winx64::RegisterMapper for RegisterMapper { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index a000f8ece143..210f1d964a71 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -351,3 +351,4 @@ impl LowerBackend for X64Backend { type FactFlowState = pcc::FactFlowState; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 57bfa06ee7fd..3917b4203ca5 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -1249,3 +1249,4 @@ const I8X16_USHR_MASKS: [u8; 128] = [ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ]; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index c48996ec46d6..1bc434f23b5a 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -14,3 +14,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_x64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 37a386504347..52d1213866fe 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -264,3 +264,4 @@ fn isa_constructor( let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags)?; Ok(backend.wrapped()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs index 09b356d69958..b82eb7d5014e 100644 --- a/cranelift/codegen/src/isa/x64/pcc.rs +++ b/cranelift/codegen/src/isa/x64/pcc.rs @@ -324,3 +324,4 @@ fn compute_addr(ctx: &FactContext, vcode: &VCode, amode: &Amode, bits: u16 Amode::RipRelative { .. } => None, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/settings.rs b/cranelift/codegen/src/isa/x64/settings.rs index 12420311b34c..83faa5585cb6 100644 --- a/cranelift/codegen/src/isa/x64/settings.rs +++ b/cranelift/codegen/src/isa/x64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/x86/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-x86.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index a2b58b15431d..7e974bff3f56 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -941,3 +941,4 @@ macro_rules! isle_common_prelude_methods { } }; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/branch_to_trap.rs b/cranelift/codegen/src/legalizer/branch_to_trap.rs index 1cbb0e657ffb..330c47abc6e7 100644 --- a/cranelift/codegen/src/legalizer/branch_to_trap.rs +++ b/cranelift/codegen/src/legalizer/branch_to_trap.rs @@ -96,3 +96,4 @@ impl BranchToTrap { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index 45444d161934..85b7dee06108 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -176,3 +176,4 @@ fn symbol( WalkCommand::Continue } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs index 768afd306752..44dcd1ad4dcb 100644 --- a/cranelift/codegen/src/legalizer/mod.rs +++ b/cranelift/codegen/src/legalizer/mod.rs @@ -392,3 +392,4 @@ fn expand_stack_load( WalkCommand::Continue } +use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 425edb25e160..7cf1a47e3305 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -43,6 +43,8 @@ include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); #[macro_use] mod machinst; +mod prelude; + pub mod binemit; pub mod cfg_printer; pub mod cursor; @@ -122,3 +124,4 @@ macro_rules! trace_log_enabled { } include!(concat!(env!("OUT_DIR"), "/version.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index 5d88c519af5a..adb70bc20971 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -430,3 +430,4 @@ mod tests { assert_eq!(loop_analysis.loop_level(block5).level(), 1); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 951d74959703..ce4b6740e3f2 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -2616,3 +2616,4 @@ mod tests { assert_eq!(core::mem::size_of::(), 24); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 9e48e2c4d607..5edbc8b0b62f 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -483,3 +483,4 @@ mod test { assert!(order.lowered_order[8].out_edge().is_none()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index fb7241d01c65..1f05b5b3fc5a 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -2915,3 +2915,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index cd2e7e9d6ac5..efc1f60de90f 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -95,3 +95,4 @@ pub fn compile( Ok((vcode, regalloc_result)) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 01f397c8c67f..222dc072e470 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -21,3 +21,4 @@ where let alignment_mask = alignment - 1.into(); (x + alignment_mask) & !alignment_mask } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/inst_common.rs b/cranelift/codegen/src/machinst/inst_common.rs index b077dd3b6112..1a15cde4e1fa 100644 --- a/cranelift/codegen/src/machinst/inst_common.rs +++ b/cranelift/codegen/src/machinst/inst_common.rs @@ -14,3 +14,4 @@ pub struct InsnInput { pub(crate) insn: IRInst, pub(crate) input: usize, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index f73ede5b257b..96cfe717456b 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -849,3 +849,4 @@ where &self.lower_ctx.f.dfg } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 18ee7643f231..84fc96654dff 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -1798,3 +1798,4 @@ mod tests { assert_eq!(uses[v5], ValueUseState::Unused); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 61ebb9bc0800..6bc6890f8a35 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -628,3 +628,4 @@ pub trait TextSectionBuilder { /// the bytes of the text section. fn finish(&mut self, ctrl_plane: &mut ControlPlane) -> Vec; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/pcc.rs b/cranelift/codegen/src/machinst/pcc.rs index 046b2ca3b3e2..665790bad4b9 100644 --- a/cranelift/codegen/src/machinst/pcc.rs +++ b/cranelift/codegen/src/machinst/pcc.rs @@ -164,3 +164,4 @@ pub(crate) enum LoadOrStore<'a> { stored_fact: Option<&'a Fact>, }, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index dd28ee05f4c8..5d364601297d 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -563,3 +563,4 @@ pub trait PrettyPrint { self.pretty_print(0) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index 8a684d868f86..f7d3a2c0c91b 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -150,3 +150,4 @@ pub(crate) fn writable_value_regs(regs: ValueRegs) -> ValueRegs>) -> ValueRegs { regs.map(|r| r.to_reg()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 22c855584c09..a1fb9c9e12bb 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -2058,3 +2058,4 @@ mod test { // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes. } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/nan_canonicalization.rs b/cranelift/codegen/src/nan_canonicalization.rs index e6a73deaf83a..04f8ffdc0f6f 100644 --- a/cranelift/codegen/src/nan_canonicalization.rs +++ b/cranelift/codegen/src/nan_canonicalization.rs @@ -124,3 +124,4 @@ fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst, has_vector_support: bool) pos.prev_inst(); // Step backwards so the pass does not skip instructions. } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 4ec9728f1e35..50ced940f133 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -368,3 +368,4 @@ impl<'a, 'b, 'c> generated_code::Context for IsleContext<'a, 'b, 'c> { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/div_const.rs b/cranelift/codegen/src/opts/div_const.rs index a88f0c6344f5..4ef0163a2d8b 100644 --- a/cranelift/codegen/src/opts/div_const.rs +++ b/cranelift/codegen/src/opts/div_const.rs @@ -1212,3 +1212,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/generated_code.rs b/cranelift/codegen/src/opts/generated_code.rs index 82208623362a..2ff9eaef16bc 100644 --- a/cranelift/codegen/src/opts/generated_code.rs +++ b/cranelift/codegen/src/opts/generated_code.rs @@ -16,3 +16,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_opt.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index b2d13852bc08..981d7fe27e43 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,4 +1,8 @@ -use alloc::format; -use alloc::string::{String, ToString}; -use alloc::vec::Vec; -use alloc::vec; +pub use alloc::format; +pub use alloc::string::{String, ToString}; +pub use alloc::vec::Vec; +pub use alloc::vec; +pub use alloc::slice; + +pub use core::prelude::*; +pub use core::ops; \ No newline at end of file diff --git a/cranelift/codegen/src/print_errors.rs b/cranelift/codegen/src/print_errors.rs index 21a2767267e8..348497eeb96b 100644 --- a/cranelift/codegen/src/print_errors.rs +++ b/cranelift/codegen/src/print_errors.rs @@ -221,3 +221,4 @@ pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String { err.to_string() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ranges.rs b/cranelift/codegen/src/ranges.rs index 419dee83c08f..4ea817d64457 100644 --- a/cranelift/codegen/src/ranges.rs +++ b/cranelift/codegen/src/ranges.rs @@ -129,3 +129,4 @@ impl Ranges { self.reverse_index(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index ae9f3ad6ed24..a6b2712059f0 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -418,3 +418,4 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) n_consts ); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index c62572cd9958..0f56d06772ed 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -109,3 +109,4 @@ impl<'a> core::fmt::Debug for CompileError<'a> { /// A convenient alias for a `Result` that uses `CompileError` as the error type. pub type CompileResult<'a, T> = Result>; +use crate::prelude::*; diff --git a/cranelift/codegen/src/scoped_hash_map.rs b/cranelift/codegen/src/scoped_hash_map.rs index b599d36dc205..0835af1c4368 100644 --- a/cranelift/codegen/src/scoped_hash_map.rs +++ b/cranelift/codegen/src/scoped_hash_map.rs @@ -332,3 +332,4 @@ mod tests { assert_eq!(map.get(&NullCtx, &3), Some(&4)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 158ba139bd42..39899e63480c 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -566,3 +566,4 @@ enable_incremental_compilation_cache_checks = false assert_eq!(f.opt_level(), super::OptLevel::Speed); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/souper_harvest.rs b/cranelift/codegen/src/souper_harvest.rs index 02958ed56a71..5ea25882bae3 100644 --- a/cranelift/codegen/src/souper_harvest.rs +++ b/cranelift/codegen/src/souper_harvest.rs @@ -587,3 +587,4 @@ fn post_order_dfs( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index 584d9239d0fa..e6232e901a39 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -89,3 +89,4 @@ where (&mut *self.container, &mut self.value) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index a06c6001ef41..0c02dcb790c8 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -303,3 +303,4 @@ mod tests { assert_eq!(Pass::regalloc.to_string(), "Register allocation"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/traversals.rs b/cranelift/codegen/src/traversals.rs index db57036aacd6..24e8feb38b61 100644 --- a/cranelift/codegen/src/traversals.rs +++ b/cranelift/codegen/src/traversals.rs @@ -277,3 +277,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/unreachable_code.rs b/cranelift/codegen/src/unreachable_code.rs index 68d7bd33fdeb..7af5e6d7d33c 100644 --- a/cranelift/codegen/src/unreachable_code.rs +++ b/cranelift/codegen/src/unreachable_code.rs @@ -71,3 +71,4 @@ pub fn eliminate_unreachable_code( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/value_label.rs b/cranelift/codegen/src/value_label.rs index 65b3e7d1eac9..f822e19437c8 100644 --- a/cranelift/codegen/src/value_label.rs +++ b/cranelift/codegen/src/value_label.rs @@ -30,3 +30,4 @@ pub enum LabelValueLoc { /// Resulting map of Value labels and their ranges/locations. pub type ValueLabelsRanges = HashMap>; +use crate::prelude::*; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 304c3ebb202f..a5f66efd89b7 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2314,3 +2314,4 @@ mod tests { assert_err_with_msg!(errors, "block0 cannot be empty"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index c0025aa6fca3..ab4b51effee1 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -749,3 +749,4 @@ mod tests { ); } } +use crate::prelude::*; From 0e909fe6e61db07afffb05b54915d28daf909440 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 19:33:44 +0100 Subject: [PATCH 23/61] update isle to use alloc and core --- cranelift/isle/isle/src/codegen.rs | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/cranelift/isle/isle/src/codegen.rs b/cranelift/isle/isle/src/codegen.rs index c215e1db74ea..e42ef1ae5a7c 100644 --- a/cranelift/isle/isle/src/codegen.rs +++ b/cranelift/isle/isle/src/codegen.rs @@ -166,7 +166,8 @@ impl<'a> Codegen<'a> { } writeln!(code, "\nuse super::*; // Pulls in all external types.").unwrap(); - writeln!(code, "use std::marker::PhantomData;").unwrap(); + writeln!(code, "use alloc::vec::Vec;").unwrap(); + writeln!(code, "use core::{{marker::PhantomData, ops}};").unwrap(); } fn generate_trait_sig(&self, code: &mut String, indent: &str, sig: &ExternalSig) { @@ -271,38 +272,38 @@ pub trait Length {{ fn len(&self) -> usize; }} -impl Length for std::vec::Vec {{ +impl Length for alloc::vec::Vec {{ fn len(&self) -> usize {{ - std::vec::Vec::len(self) + alloc::vec::Vec::len(self) }} }} pub struct ContextIterWrapper {{ iter: I, - _ctx: std::marker::PhantomData, + _ctx: core::marker::PhantomData, }} impl Default for ContextIterWrapper {{ fn default() -> Self {{ ContextIterWrapper {{ iter: I::default(), - _ctx: std::marker::PhantomData + _ctx: core::marker::PhantomData }} }} }} -impl std::ops::Deref for ContextIterWrapper {{ +impl core::ops::Deref for ContextIterWrapper {{ type Target = I; fn deref(&self) -> &I {{ &self.iter }} }} -impl std::ops::DerefMut for ContextIterWrapper {{ +impl core::ops::DerefMut for ContextIterWrapper {{ fn deref_mut(&mut self) -> &mut I {{ &mut self.iter }} }} impl From for ContextIterWrapper {{ fn from(iter: I) -> Self {{ - Self {{ iter, _ctx: std::marker::PhantomData }} + Self {{ iter, _ctx: core::marker::PhantomData }} }} }} impl ContextIter for ContextIterWrapper {{ @@ -322,7 +323,7 @@ impl IntoContextIter for ContextIterWrapper { fn into_context_iter(self) -> Self::IntoIter {{ ContextIterWrapper {{ iter: self.iter.into_iter(), - _ctx: std::marker::PhantomData + _ctx: core::marker::PhantomData }} }} }} From 88fb4fda7700bfa3ab656f0d22a3be0467eb242a Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 19:50:17 +0100 Subject: [PATCH 24/61] some instances shouldn't have been renamed, fixes cargo test --- .../codegen/src/isa/s390x/inst/emit_tests.rs | 16 ++++++++-------- cranelift/codegen/src/isa/s390x/inst/mod.rs | 2 +- cranelift/codegen/src/verifier/mod.rs | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index aa4ab565eaef..9f5afa33448e 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -12039,7 +12039,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102000", - "core %f1, 0(%r2)", + "std %f1, 0(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12054,7 +12054,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102FFF", - "core %f1, 4095(%r2)", + "std %f1, 4095(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12069,7 +12069,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1020008067", - "corey %f1, -524288(%r2)", + "stdy %f1, -524288(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12084,7 +12084,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED102FFF7F67", - "corey %f1, 524287(%r2)", + "stdy %f1, 524287(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12129,7 +12129,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123000", - "core %f1, 0(%r2,%r3)", + "std %f1, 0(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12144,7 +12144,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123FFF", - "core %f1, 4095(%r2,%r3)", + "std %f1, 4095(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12159,7 +12159,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1230008067", - "corey %f1, -524288(%r2,%r3)", + "stdy %f1, -524288(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12174,7 +12174,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED123FFF7F67", - "corey %f1, 524287(%r2,%r3)", + "stdy %f1, 524287(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 9159f435ea1e..427c8cd05292 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -2970,7 +2970,7 @@ impl Inst { (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None), (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None), (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")), - (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("core"), Some("corey")), + (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")), (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None), (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None), (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None), diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index a5f66efd89b7..0aac5d0d024f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2130,9 +2130,9 @@ mod tests { None => panic!("Expected an error"), Some(&VerifierError { ref message, .. }) => { if !message.contains($msg) { - #[cfg(feature = "core")] + #[cfg(feature = "std")] panic!("'{}' did not contain the substring '{}'", message, $msg); - #[cfg(not(feature = "core"))] + #[cfg(not(feature = "std"))] panic!("error message did not contain the expected substring"); } } From 6d855859f0bcaa76a8a5f7c5690d4814df9ab4a1 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:00:47 +0100 Subject: [PATCH 25/61] add cranelift-assembler-x64 (no_std) to CI --- .github/workflows/main.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 99a6b0204d59..592cea2b3635 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,6 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && + cargo check -p cranelift-assembler-x64 --no-default-features -F core && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. From fe3194e309ba4c007859f6446badb9b6673bcdd2 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:25:58 +0100 Subject: [PATCH 26/61] automatically remove prelude with cargo fix --- cranelift/codegen/src/binemit/mod.rs | 1 - cranelift/codegen/src/cfg_printer.rs | 1 - cranelift/codegen/src/constant_hash.rs | 1 - cranelift/codegen/src/context.rs | 1 - cranelift/codegen/src/ctxhash.rs | 1 - cranelift/codegen/src/cursor.rs | 1 - cranelift/codegen/src/dbg.rs | 1 - cranelift/codegen/src/dominator_tree/simple.rs | 1 - cranelift/codegen/src/egraph/cost.rs | 1 - cranelift/codegen/src/flowgraph.rs | 1 - cranelift/codegen/src/inst_predicates.rs | 1 - cranelift/codegen/src/ir/atomic_rmw_op.rs | 1 - cranelift/codegen/src/ir/builder.rs | 1 - cranelift/codegen/src/ir/condcodes.rs | 1 - cranelift/codegen/src/ir/constant.rs | 1 - cranelift/codegen/src/ir/dfg.rs | 1 - cranelift/codegen/src/ir/dynamic_type.rs | 1 - cranelift/codegen/src/ir/extfunc.rs | 1 - cranelift/codegen/src/ir/extname.rs | 1 - cranelift/codegen/src/ir/function.rs | 1 - cranelift/codegen/src/ir/globalvalue.rs | 1 - cranelift/codegen/src/ir/instructions.rs | 1 - cranelift/codegen/src/ir/jumptable.rs | 1 - cranelift/codegen/src/ir/known_symbol.rs | 1 - cranelift/codegen/src/ir/libcall.rs | 1 - cranelift/codegen/src/ir/memflags.rs | 1 - cranelift/codegen/src/ir/memtype.rs | 1 - cranelift/codegen/src/ir/mod.rs | 1 - cranelift/codegen/src/ir/pcc.rs | 1 - cranelift/codegen/src/ir/progpoint.rs | 1 - cranelift/codegen/src/ir/sourceloc.rs | 1 - cranelift/codegen/src/ir/user_stack_maps.rs | 1 - cranelift/codegen/src/isa/call_conv.rs | 1 - cranelift/codegen/src/isa/mod.rs | 2 +- cranelift/codegen/src/isa/unwind.rs | 1 - cranelift/codegen/src/isa/winch.rs | 1 - cranelift/codegen/src/isa/x64/inst/emit.rs | 1 - cranelift/codegen/src/isa/x64/inst/emit_state.rs | 1 - cranelift/codegen/src/isa/x64/inst/stack_switch.rs | 1 - cranelift/codegen/src/isa/x64/inst/unwind.rs | 1 - cranelift/codegen/src/isa/x64/lower.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 2 +- cranelift/codegen/src/isa/x64/pcc.rs | 1 - cranelift/codegen/src/isa/x64/settings.rs | 1 - cranelift/codegen/src/isle_prelude.rs | 1 - cranelift/codegen/src/legalizer/branch_to_trap.rs | 1 - cranelift/codegen/src/legalizer/globalvalue.rs | 1 - cranelift/codegen/src/legalizer/mod.rs | 1 - cranelift/codegen/src/lib.rs | 3 +-- cranelift/codegen/src/loop_analysis.rs | 1 - cranelift/codegen/src/machinst/blockorder.rs | 1 - cranelift/codegen/src/machinst/compile.rs | 1 - cranelift/codegen/src/machinst/helpers.rs | 1 - cranelift/codegen/src/machinst/isle.rs | 1 - cranelift/codegen/src/machinst/mod.rs | 1 - cranelift/codegen/src/machinst/pcc.rs | 1 - cranelift/codegen/src/machinst/valueregs.rs | 1 - cranelift/codegen/src/nan_canonicalization.rs | 1 - cranelift/codegen/src/opts.rs | 1 - cranelift/codegen/src/opts/div_const.rs | 1 - cranelift/codegen/src/prelude.rs | 6 +----- cranelift/codegen/src/print_errors.rs | 1 - cranelift/codegen/src/ranges.rs | 1 - cranelift/codegen/src/remove_constant_phis.rs | 1 - cranelift/codegen/src/result.rs | 1 - cranelift/codegen/src/scoped_hash_map.rs | 1 - cranelift/codegen/src/take_and_replace.rs | 1 - cranelift/codegen/src/timing.rs | 1 - cranelift/codegen/src/traversals.rs | 1 - cranelift/codegen/src/unreachable_code.rs | 1 - cranelift/codegen/src/value_label.rs | 1 - 71 files changed, 4 insertions(+), 76 deletions(-) diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs index 022eb7db5fca..cd34c0b3ff13 100644 --- a/cranelift/codegen/src/binemit/mod.rs +++ b/cranelift/codegen/src/binemit/mod.rs @@ -190,4 +190,3 @@ pub struct CodeInfo { /// Number of bytes in total. pub total_size: CodeOffset, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/cfg_printer.rs b/cranelift/codegen/src/cfg_printer.rs index 8c07f0ac478b..ef71b63ca712 100644 --- a/cranelift/codegen/src/cfg_printer.rs +++ b/cranelift/codegen/src/cfg_printer.rs @@ -81,4 +81,3 @@ impl<'a> Display for CFGPrinter<'a> { self.write(f) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/constant_hash.rs b/cranelift/codegen/src/constant_hash.rs index be018675b5e2..1de2a2edb43e 100644 --- a/cranelift/codegen/src/constant_hash.rs +++ b/cranelift/codegen/src/constant_hash.rs @@ -60,4 +60,3 @@ pub fn probe + ?Sized>( idx += step; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index 46267cb446d2..c37de05497bc 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -391,4 +391,3 @@ impl Context { self.verify_if(fisa) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 7e6b852907f3..7148046ae9c1 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -223,4 +223,3 @@ mod test { assert_eq!(*map.get(&k0, &ctx).unwrap(), 84); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/cursor.rs b/cranelift/codegen/src/cursor.rs index b1bec22fa159..ae7b0ea874ad 100644 --- a/cranelift/codegen/src/cursor.rs +++ b/cranelift/codegen/src/cursor.rs @@ -687,4 +687,3 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> { &mut self.func.dfg } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dbg.rs b/cranelift/codegen/src/dbg.rs index 8a0da7a24aed..4796f3967b91 100644 --- a/cranelift/codegen/src/dbg.rs +++ b/cranelift/codegen/src/dbg.rs @@ -26,4 +26,3 @@ where } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree/simple.rs b/cranelift/codegen/src/dominator_tree/simple.rs index 9abc47e4df95..853158bc80b1 100644 --- a/cranelift/codegen/src/dominator_tree/simple.rs +++ b/cranelift/codegen/src/dominator_tree/simple.rs @@ -582,4 +582,3 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index f2f2048497b9..062196964c96 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -236,4 +236,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/flowgraph.rs b/cranelift/codegen/src/flowgraph.rs index 9358c851b4e3..6478dfddbf90 100644 --- a/cranelift/codegen/src/flowgraph.rs +++ b/cranelift/codegen/src/flowgraph.rs @@ -347,4 +347,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs index 91cb01ca7cf3..7b42e1728663 100644 --- a/cranelift/codegen/src/inst_predicates.rs +++ b/cranelift/codegen/src/inst_predicates.rs @@ -215,4 +215,3 @@ pub(crate) fn visit_block_succs( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/atomic_rmw_op.rs b/cranelift/codegen/src/ir/atomic_rmw_op.rs index ea6a16b7d969..0317fc00d2c1 100644 --- a/cranelift/codegen/src/ir/atomic_rmw_op.rs +++ b/cranelift/codegen/src/ir/atomic_rmw_op.rs @@ -102,4 +102,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/builder.rs b/cranelift/codegen/src/ir/builder.rs index c36673bd79ee..24d9beaee660 100644 --- a/cranelift/codegen/src/ir/builder.rs +++ b/cranelift/codegen/src/ir/builder.rs @@ -280,4 +280,3 @@ mod tests { .Trap(Opcode::Return, I32, TrapCode::BAD_CONVERSION_TO_INTEGER); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index 454423f7a189..009f95bf391c 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -402,4 +402,3 @@ mod tests { assert_eq!("bogus".parse::(), Err(())); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index 5612510c8f33..67310cd9462f 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -485,4 +485,3 @@ mod tests { assert_eq!(Ieee128::try_from(&constant).unwrap().bits(), value.bits()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dfg.rs b/cranelift/codegen/src/ir/dfg.rs index e48cdd42d990..3dd2ad4211c3 100644 --- a/cranelift/codegen/src/ir/dfg.rs +++ b/cranelift/codegen/src/ir/dfg.rs @@ -1882,4 +1882,3 @@ mod tests { assert_eq!(v1, func.dfg.inst_args(call_inst_dup)[0]); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dynamic_type.rs b/cranelift/codegen/src/ir/dynamic_type.rs index 369bcc74eeba..53027c196945 100644 --- a/cranelift/codegen/src/ir/dynamic_type.rs +++ b/cranelift/codegen/src/ir/dynamic_type.rs @@ -52,4 +52,3 @@ pub fn dynamic_to_fixed(ty: Type) -> Type { _ => unreachable!("unhandled type: {}", ty), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extfunc.rs b/cranelift/codegen/src/ir/extfunc.rs index 61880e27fc84..ebfaf3a8ddaf 100644 --- a/cranelift/codegen/src/ir/extfunc.rs +++ b/cranelift/codegen/src/ir/extfunc.rs @@ -418,4 +418,3 @@ mod tests { assert_eq!(sig.to_string(), "(i32, i32x4) -> f32, i8 windows_fastcall"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index e80fb4cf34b4..d28ebcb4e7b2 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -336,4 +336,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/function.rs b/cranelift/codegen/src/ir/function.rs index 296d0c9cf938..80926edcdf1c 100644 --- a/cranelift/codegen/src/ir/function.rs +++ b/cranelift/codegen/src/ir/function.rs @@ -517,4 +517,3 @@ impl<'a> fmt::Debug for DisplayFunctionSpec<'a> { write_function_spec(fmt, self.0) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/globalvalue.rs b/cranelift/codegen/src/ir/globalvalue.rs index 8ea7372c7349..89120c8b8364 100644 --- a/cranelift/codegen/src/ir/globalvalue.rs +++ b/cranelift/codegen/src/ir/globalvalue.rs @@ -145,4 +145,3 @@ impl fmt::Display for GlobalValueData { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 6a95b1ce9975..80c04e48e6fb 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -1538,4 +1538,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 85d6d77b1a51..5bdad87d941f 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -173,4 +173,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/known_symbol.rs b/cranelift/codegen/src/ir/known_symbol.rs index 6c594b7faff3..c3d17501a39b 100644 --- a/cranelift/codegen/src/ir/known_symbol.rs +++ b/cranelift/codegen/src/ir/known_symbol.rs @@ -45,4 +45,3 @@ mod tests { assert_eq!("CoffTlsIndex".parse(), Ok(KnownSymbol::CoffTlsIndex)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/libcall.rs b/cranelift/codegen/src/ir/libcall.rs index 3cf1ebb2d7f2..6b60dfd07d27 100644 --- a/cranelift/codegen/src/ir/libcall.rs +++ b/cranelift/codegen/src/ir/libcall.rs @@ -230,4 +230,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memflags.rs b/cranelift/codegen/src/ir/memflags.rs index 726004dcd59f..45f32ce85fd2 100644 --- a/cranelift/codegen/src/ir/memflags.rs +++ b/cranelift/codegen/src/ir/memflags.rs @@ -485,4 +485,3 @@ mod tests { assert!(big.set_by_name("table").is_err()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index 8501c9bb73a3..b7b0d7e2db1e 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -188,4 +188,3 @@ impl MemoryTypeData { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/mod.rs b/cranelift/codegen/src/ir/mod.rs index db671b366444..eca17e7badda 100644 --- a/cranelift/codegen/src/ir/mod.rs +++ b/cranelift/codegen/src/ir/mod.rs @@ -117,4 +117,3 @@ pub enum ValueLabelAssignments { value: Value, }, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index f9062a1ddad6..d1bf7ea62dba 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -1679,4 +1679,3 @@ pub fn check_vcode_facts( } Ok(()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/progpoint.rs b/cranelift/codegen/src/ir/progpoint.rs index dafcd16d7c5d..84d394276f67 100644 --- a/cranelift/codegen/src/ir/progpoint.rs +++ b/cranelift/codegen/src/ir/progpoint.rs @@ -73,4 +73,3 @@ mod tests { assert_eq!(pp2.to_string(), "block3"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/sourceloc.rs b/cranelift/codegen/src/ir/sourceloc.rs index 38efbe2939aa..6704574d0d09 100644 --- a/cranelift/codegen/src/ir/sourceloc.rs +++ b/cranelift/codegen/src/ir/sourceloc.rs @@ -115,4 +115,3 @@ mod tests { assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs index 92aaa198effa..6ad9b697cd02 100644 --- a/cranelift/codegen/src/ir/user_stack_maps.rs +++ b/cranelift/codegen/src/ir/user_stack_maps.rs @@ -197,4 +197,3 @@ impl UserStackMap { }) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/call_conv.rs b/cranelift/codegen/src/isa/call_conv.rs index 65e6c514c830..a8f6ce50203e 100644 --- a/cranelift/codegen/src/isa/call_conv.rs +++ b/cranelift/codegen/src/isa/call_conv.rs @@ -153,4 +153,3 @@ impl str::FromStr for CallConv { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2c31830e139a..2c44409de892 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -50,7 +50,7 @@ use crate::CodegenResult; use crate::ir::{self, Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::{UnwindInfoKind, systemv::RegisterMappingError}; -use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder}; +use crate::machinst::{CompiledCodeStencil, TextSectionBuilder}; use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index cd98fb9b8222..7b842ac7e4ab 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -249,4 +249,3 @@ impl<'a> Writer<'a> { self.offset += 4; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index 8e9bbf0efdc3..df8fdce35223 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -20,4 +20,3 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 2374d6e63b58..363f9194bd6f 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -2193,4 +2193,3 @@ fn emit_lea( _ => lea(*dst.as_ref(), addr, sink), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_state.rs b/cranelift/codegen/src/isa/x64/inst/emit_state.rs index 98ffebf3f3be..426a17a2803b 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_state.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_state.rs @@ -53,4 +53,3 @@ impl EmitState { self.user_stack_map = None; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs index d32c59dd9fee..4c9400df41bf 100644 --- a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs +++ b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs @@ -47,4 +47,3 @@ pub fn control_context_layout() -> ControlContextLayout { pub fn payload_register() -> Reg { regs::rdi() } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind.rs b/cranelift/codegen/src/isa/x64/inst/unwind.rs index 56289f082012..cb86c3b7ccd5 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind.rs @@ -3,4 +3,3 @@ pub(crate) mod systemv; #[cfg(feature = "unwind")] pub(crate) mod winx64; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 210f1d964a71..a000f8ece143 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -351,4 +351,3 @@ impl LowerBackend for X64Backend { type FactFlowState = pcc::FactFlowState; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 52d1213866fe..c67ccc5b654b 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -10,7 +10,7 @@ use crate::isa::unwind::systemv; use crate::isa::x64::settings as x64_settings; use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey}; use crate::machinst::{ - CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, + CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; use crate::result::{CodegenError, CodegenResult}; diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs index b82eb7d5014e..09b356d69958 100644 --- a/cranelift/codegen/src/isa/x64/pcc.rs +++ b/cranelift/codegen/src/isa/x64/pcc.rs @@ -324,4 +324,3 @@ fn compute_addr(ctx: &FactContext, vcode: &VCode, amode: &Amode, bits: u16 Amode::RipRelative { .. } => None, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/settings.rs b/cranelift/codegen/src/isa/x64/settings.rs index 83faa5585cb6..12420311b34c 100644 --- a/cranelift/codegen/src/isa/x64/settings.rs +++ b/cranelift/codegen/src/isa/x64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/x86/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-x86.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index 7e974bff3f56..a2b58b15431d 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -941,4 +941,3 @@ macro_rules! isle_common_prelude_methods { } }; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/branch_to_trap.rs b/cranelift/codegen/src/legalizer/branch_to_trap.rs index 330c47abc6e7..1cbb0e657ffb 100644 --- a/cranelift/codegen/src/legalizer/branch_to_trap.rs +++ b/cranelift/codegen/src/legalizer/branch_to_trap.rs @@ -96,4 +96,3 @@ impl BranchToTrap { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index 85b7dee06108..45444d161934 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -176,4 +176,3 @@ fn symbol( WalkCommand::Continue } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs index 44dcd1ad4dcb..768afd306752 100644 --- a/cranelift/codegen/src/legalizer/mod.rs +++ b/cranelift/codegen/src/legalizer/mod.rs @@ -392,4 +392,3 @@ fn expand_stack_load( WalkCommand::Continue } -use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 7cf1a47e3305..fe017ca4468e 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -21,7 +21,7 @@ extern crate alloc; extern crate std; #[cfg(not(feature = "std"))] -use hashbrown::{HashMap, HashSet, hash_map}; +use hashbrown::{HashMap, hash_map}; #[cfg(feature = "std")] use std::collections::{HashMap, hash_map}; @@ -124,4 +124,3 @@ macro_rules! trace_log_enabled { } include!(concat!(env!("OUT_DIR"), "/version.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index adb70bc20971..5d88c519af5a 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -430,4 +430,3 @@ mod tests { assert_eq!(loop_analysis.loop_level(block5).level(), 1); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 5edbc8b0b62f..9e48e2c4d607 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -483,4 +483,3 @@ mod test { assert!(order.lowered_order[8].out_edge().is_none()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index efc1f60de90f..cd2e7e9d6ac5 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -95,4 +95,3 @@ pub fn compile( Ok((vcode, regalloc_result)) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 222dc072e470..01f397c8c67f 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -21,4 +21,3 @@ where let alignment_mask = alignment - 1.into(); (x + alignment_mask) & !alignment_mask } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index 96cfe717456b..f73ede5b257b 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -849,4 +849,3 @@ where &self.lower_ctx.f.dfg } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 6bc6890f8a35..61ebb9bc0800 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -628,4 +628,3 @@ pub trait TextSectionBuilder { /// the bytes of the text section. fn finish(&mut self, ctrl_plane: &mut ControlPlane) -> Vec; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/pcc.rs b/cranelift/codegen/src/machinst/pcc.rs index 665790bad4b9..046b2ca3b3e2 100644 --- a/cranelift/codegen/src/machinst/pcc.rs +++ b/cranelift/codegen/src/machinst/pcc.rs @@ -164,4 +164,3 @@ pub(crate) enum LoadOrStore<'a> { stored_fact: Option<&'a Fact>, }, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index f7d3a2c0c91b..8a684d868f86 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -150,4 +150,3 @@ pub(crate) fn writable_value_regs(regs: ValueRegs) -> ValueRegs>) -> ValueRegs { regs.map(|r| r.to_reg()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/nan_canonicalization.rs b/cranelift/codegen/src/nan_canonicalization.rs index 04f8ffdc0f6f..e6a73deaf83a 100644 --- a/cranelift/codegen/src/nan_canonicalization.rs +++ b/cranelift/codegen/src/nan_canonicalization.rs @@ -124,4 +124,3 @@ fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst, has_vector_support: bool) pos.prev_inst(); // Step backwards so the pass does not skip instructions. } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 50ced940f133..4ec9728f1e35 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -368,4 +368,3 @@ impl<'a, 'b, 'c> generated_code::Context for IsleContext<'a, 'b, 'c> { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/div_const.rs b/cranelift/codegen/src/opts/div_const.rs index 4ef0163a2d8b..a88f0c6344f5 100644 --- a/cranelift/codegen/src/opts/div_const.rs +++ b/cranelift/codegen/src/opts/div_const.rs @@ -1212,4 +1212,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index 981d7fe27e43..5dd5950bdf86 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,8 +1,4 @@ pub use alloc::format; -pub use alloc::string::{String, ToString}; -pub use alloc::vec::Vec; +pub use alloc::string::ToString; pub use alloc::vec; -pub use alloc::slice; -pub use core::prelude::*; -pub use core::ops; \ No newline at end of file diff --git a/cranelift/codegen/src/print_errors.rs b/cranelift/codegen/src/print_errors.rs index 348497eeb96b..21a2767267e8 100644 --- a/cranelift/codegen/src/print_errors.rs +++ b/cranelift/codegen/src/print_errors.rs @@ -221,4 +221,3 @@ pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String { err.to_string() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ranges.rs b/cranelift/codegen/src/ranges.rs index 4ea817d64457..419dee83c08f 100644 --- a/cranelift/codegen/src/ranges.rs +++ b/cranelift/codegen/src/ranges.rs @@ -129,4 +129,3 @@ impl Ranges { self.reverse_index(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index a6b2712059f0..ae9f3ad6ed24 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -418,4 +418,3 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) n_consts ); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index 0f56d06772ed..c62572cd9958 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -109,4 +109,3 @@ impl<'a> core::fmt::Debug for CompileError<'a> { /// A convenient alias for a `Result` that uses `CompileError` as the error type. pub type CompileResult<'a, T> = Result>; -use crate::prelude::*; diff --git a/cranelift/codegen/src/scoped_hash_map.rs b/cranelift/codegen/src/scoped_hash_map.rs index 0835af1c4368..b599d36dc205 100644 --- a/cranelift/codegen/src/scoped_hash_map.rs +++ b/cranelift/codegen/src/scoped_hash_map.rs @@ -332,4 +332,3 @@ mod tests { assert_eq!(map.get(&NullCtx, &3), Some(&4)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index e6232e901a39..584d9239d0fa 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -89,4 +89,3 @@ where (&mut *self.container, &mut self.value) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index 0c02dcb790c8..a06c6001ef41 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -303,4 +303,3 @@ mod tests { assert_eq!(Pass::regalloc.to_string(), "Register allocation"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/traversals.rs b/cranelift/codegen/src/traversals.rs index 24e8feb38b61..db57036aacd6 100644 --- a/cranelift/codegen/src/traversals.rs +++ b/cranelift/codegen/src/traversals.rs @@ -277,4 +277,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/unreachable_code.rs b/cranelift/codegen/src/unreachable_code.rs index 7af5e6d7d33c..68d7bd33fdeb 100644 --- a/cranelift/codegen/src/unreachable_code.rs +++ b/cranelift/codegen/src/unreachable_code.rs @@ -71,4 +71,3 @@ pub fn eliminate_unreachable_code( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/value_label.rs b/cranelift/codegen/src/value_label.rs index f822e19437c8..65b3e7d1eac9 100644 --- a/cranelift/codegen/src/value_label.rs +++ b/cranelift/codegen/src/value_label.rs @@ -30,4 +30,3 @@ pub enum LabelValueLoc { /// Resulting map of Value labels and their ranges/locations. pub type ValueLabelsRanges = HashMap>; -use crate::prelude::*; From 5624c4d14fa3512796a9ec5bec5cdc6d4d1853a9 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 00:16:09 +0100 Subject: [PATCH 27/61] update isle changes --- cranelift/isle/isle/isle_examples/link/borrows_main.rs | 3 +++ cranelift/isle/isle/isle_examples/link/iflets_main.rs | 3 +++ .../isle/isle/isle_examples/link/multi_constructor_main.rs | 3 +++ cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs | 3 +++ cranelift/isle/isle/isle_examples/link/test_main.rs | 3 +++ cranelift/isle/isle/isle_examples/run/iconst_main.rs | 3 +++ cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs | 3 +++ cranelift/isle/isle/src/codegen.rs | 3 +-- 8 files changed, 22 insertions(+), 2 deletions(-) diff --git a/cranelift/isle/isle/isle_examples/link/borrows_main.rs b/cranelift/isle/isle/isle_examples/link/borrows_main.rs index 9de7d4ddded8..eaff4d9f918e 100644 --- a/cranelift/isle/isle/isle_examples/link/borrows_main.rs +++ b/cranelift/isle/isle/isle_examples/link/borrows_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod borrows; #[derive(Clone)] diff --git a/cranelift/isle/isle/isle_examples/link/iflets_main.rs b/cranelift/isle/isle/isle_examples/link/iflets_main.rs index 4c5717cbf407..ee974818f991 100644 --- a/cranelift/isle/isle/isle_examples/link/iflets_main.rs +++ b/cranelift/isle/isle/isle_examples/link/iflets_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod iflets; struct Context; diff --git a/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs b/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs index 3c05532ce077..c7bd08fd5bd1 100644 --- a/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs +++ b/cranelift/isle/isle/isle_examples/link/multi_constructor_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod multi_constructor; use multi_constructor::{ContextIter, IntoContextIter}; diff --git a/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs b/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs index ebfa38e30fdf..0554dd582976 100644 --- a/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs +++ b/cranelift/isle/isle/isle_examples/link/multi_extractor_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod multi_extractor; use multi_extractor::{ContextIter, IntoContextIter}; diff --git a/cranelift/isle/isle/isle_examples/link/test_main.rs b/cranelift/isle/isle/isle_examples/link/test_main.rs index 733e2a20193b..87f633e2ec6f 100644 --- a/cranelift/isle/isle/isle_examples/link/test_main.rs +++ b/cranelift/isle/isle/isle_examples/link/test_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod test; struct Context; diff --git a/cranelift/isle/isle/isle_examples/run/iconst_main.rs b/cranelift/isle/isle/isle_examples/run/iconst_main.rs index d53edea43831..275054993780 100644 --- a/cranelift/isle/isle/isle_examples/run/iconst_main.rs +++ b/cranelift/isle/isle/isle_examples/run/iconst_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod iconst; struct Context; diff --git a/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs b/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs index 37ddb0bcc50b..ec57de3383e1 100644 --- a/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs +++ b/cranelift/isle/isle/isle_examples/run/let_shadowing_main.rs @@ -1,3 +1,6 @@ +extern crate alloc; +extern crate core; + mod let_shadowing; struct Context; diff --git a/cranelift/isle/isle/src/codegen.rs b/cranelift/isle/isle/src/codegen.rs index e42ef1ae5a7c..78a8fee729e7 100644 --- a/cranelift/isle/isle/src/codegen.rs +++ b/cranelift/isle/isle/src/codegen.rs @@ -166,8 +166,7 @@ impl<'a> Codegen<'a> { } writeln!(code, "\nuse super::*; // Pulls in all external types.").unwrap(); - writeln!(code, "use alloc::vec::Vec;").unwrap(); - writeln!(code, "use core::{{marker::PhantomData, ops}};").unwrap(); + writeln!(code, "use core::marker::PhantomData;").unwrap(); } fn generate_trait_sig(&self, code: &mut String, indent: &str, sig: &ExternalSig) { From 5c37b8842551019812a537b20ec8275f2a4a4ba0 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 00:16:50 +0100 Subject: [PATCH 28/61] update assembler changes --- cranelift/assembler-x64/Cargo.toml | 1 - cranelift/assembler-x64/src/api.rs | 3 ++- cranelift/assembler-x64/src/custom.rs | 2 +- cranelift/assembler-x64/src/fuzz.rs | 4 ++++ cranelift/assembler-x64/src/imm.rs | 4 +--- cranelift/assembler-x64/src/inst.rs | 1 - cranelift/assembler-x64/src/lib.rs | 4 +++- cranelift/assembler-x64/src/main.rs | 12 ------------ cranelift/assembler-x64/src/mem.rs | 5 ++--- cranelift/assembler-x64/src/xmm.rs | 2 -- 10 files changed, 13 insertions(+), 25 deletions(-) diff --git a/cranelift/assembler-x64/Cargo.toml b/cranelift/assembler-x64/Cargo.toml index 424d26f206ce..6935ec669950 100644 --- a/cranelift/assembler-x64/Cargo.toml +++ b/cranelift/assembler-x64/Cargo.toml @@ -23,4 +23,3 @@ workspace = true [features] fuzz = ['dep:arbitrary', 'dep:capstone'] -core = [] diff --git a/cranelift/assembler-x64/src/api.rs b/cranelift/assembler-x64/src/api.rs index f65cfc338045..f861b7726822 100644 --- a/cranelift/assembler-x64/src/api.rs +++ b/cranelift/assembler-x64/src/api.rs @@ -3,10 +3,11 @@ use crate::gpr; use crate::xmm; use crate::{Amode, DeferredTarget, GprMem, XmmMem}; +use alloc::string::String; use alloc::vec::Vec; use core::fmt; use core::num::NonZeroU8; -use alloc::string::String; + /// Describe how an instruction is emitted into a code buffer. pub trait CodeSink { /// Add 1 byte to the code section. diff --git a/cranelift/assembler-x64/src/custom.rs b/cranelift/assembler-x64/src/custom.rs index c2b70fecbc24..25c63e239cf4 100644 --- a/cranelift/assembler-x64/src/custom.rs +++ b/cranelift/assembler-x64/src/custom.rs @@ -191,8 +191,8 @@ pub mod mnemonic { pub mod display { use crate::inst; use crate::{Amode, Gpr, GprMem, Registers, Size}; - use core::fmt; use alloc::string::ToString; + use core::fmt; pub fn callq_d(f: &mut fmt::Formatter, inst: &inst::callq_d) -> fmt::Result { let inst::callq_d { imm32 } = inst; diff --git a/cranelift/assembler-x64/src/fuzz.rs b/cranelift/assembler-x64/src/fuzz.rs index 9bbcaf83509f..290d888f5a00 100644 --- a/cranelift/assembler-x64/src/fuzz.rs +++ b/cranelift/assembler-x64/src/fuzz.rs @@ -4,6 +4,10 @@ //! throughout this crate to avoid depending on the `arbitrary` crate //! unconditionally (use the `fuzz` feature instead). +use std::string::{String, ToString}; +use std::vec::Vec; +use std::{format, println}; + use crate::{ AmodeOffset, AmodeOffsetPlusKnownOffset, AsReg, CodeSink, DeferredTarget, Fixed, Gpr, Inst, KnownOffset, NonRspGpr, Registers, TrapCode, Xmm, diff --git a/cranelift/assembler-x64/src/imm.rs b/cranelift/assembler-x64/src/imm.rs index 0c129cd65d45..f350952dd23f 100644 --- a/cranelift/assembler-x64/src/imm.rs +++ b/cranelift/assembler-x64/src/imm.rs @@ -1,10 +1,8 @@ //! Immediate operands to instructions. use crate::api::CodeSink; -use core::fmt; - -#[cfg(feature = "core")] use alloc::{format, string::String}; +use core::fmt; /// This helper function prints the unsigned hexadecimal representation of the /// immediate value: e.g., this prints `$0xfe` to represent both the signed `-2` diff --git a/cranelift/assembler-x64/src/inst.rs b/cranelift/assembler-x64/src/inst.rs index e4f23849cd12..c9073401b040 100644 --- a/cranelift/assembler-x64/src/inst.rs +++ b/cranelift/assembler-x64/src/inst.rs @@ -16,7 +16,6 @@ use crate::xmm::{self, Xmm}; use alloc::string::ToString; - // Include code generated by the `meta` crate. include!(concat!(env!("OUT_DIR"), "/assembler.rs")); diff --git a/cranelift/assembler-x64/src/lib.rs b/cranelift/assembler-x64/src/lib.rs index d28e102ffeb7..bf781a50de44 100644 --- a/cranelift/assembler-x64/src/lib.rs +++ b/cranelift/assembler-x64/src/lib.rs @@ -41,8 +41,10 @@ non_camel_case_types, reason = "all of the generated struct names use snake case" )] -#![cfg_attr(feature = "core", no_std)] +#![no_std] extern crate alloc; +#[cfg(any(test, feature = "fuzz"))] +extern crate std; mod api; mod custom; diff --git a/cranelift/assembler-x64/src/main.rs b/cranelift/assembler-x64/src/main.rs index 4361d85624f9..31ae7a7d55c5 100644 --- a/cranelift/assembler-x64/src/main.rs +++ b/cranelift/assembler-x64/src/main.rs @@ -1,19 +1,7 @@ //! Print the path to the generated code. -#![cfg_attr(feature = "core", no_std)] - -#[cfg(not(feature = "core"))] fn main() { let paths: Vec = include!(concat!(env!("OUT_DIR"), "/generated-files.rs")); for path in paths { println!("{}", path.display()); } } - -#[cfg(feature = "core")] -fn main() {} - -#[cfg(feature = "core")] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} \ No newline at end of file diff --git a/cranelift/assembler-x64/src/mem.rs b/cranelift/assembler-x64/src/mem.rs index cffecf9bf18b..8235f9b5bfa9 100644 --- a/cranelift/assembler-x64/src/mem.rs +++ b/cranelift/assembler-x64/src/mem.rs @@ -1,12 +1,11 @@ //! Memory operands to instructions. +use alloc::string::{String, ToString}; + use crate::api::{AsReg, CodeSink, Constant, KnownOffset, Label, TrapCode}; use crate::gpr::{self, NonRspGpr, Size}; use crate::rex::{Disp, RexPrefix, encode_modrm, encode_sib}; -#[cfg(feature = "core")] -use alloc::string::{String, ToString}; - /// x64 memory addressing modes. #[derive(Copy, Clone, Debug, PartialEq)] #[cfg_attr(any(test, feature = "fuzz"), derive(arbitrary::Arbitrary))] diff --git a/cranelift/assembler-x64/src/xmm.rs b/cranelift/assembler-x64/src/xmm.rs index 636c887afbc7..d016e270b8e9 100644 --- a/cranelift/assembler-x64/src/xmm.rs +++ b/cranelift/assembler-x64/src/xmm.rs @@ -2,9 +2,7 @@ use crate::{AsReg, CodeSink, rex::encode_modrm}; -#[cfg(feature = "core")] use alloc::string::String; -//use core::convert::{AsMut, AsRef, From}; /// An x64 SSE register (e.g., `%xmm0`). #[derive(Clone, Copy, Debug)] From 775a0fc6b82215a440de72ab3b5e7071d49165d0 Mon Sep 17 00:00:00 2001 From: SSD <96286755+the-ssd@users.noreply.github.com> Date: Fri, 2 Jan 2026 00:18:23 +0100 Subject: [PATCH 29/61] update assembler changes --- .github/workflows/main.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 592cea2b3635..39e6898c6b38 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,7 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && - cargo check -p cranelift-assembler-x64 --no-default-features -F core && + cargo check -p cranelift-assembler-x64 && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. From d2eca411b0f864b410334b6cfd9c881f6c6c711e Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 08:25:44 +0100 Subject: [PATCH 30/61] use latest codegen changes + fix FxHash problem --- .github/workflows/main.yml | 2 +- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/alias_analysis.rs | 3 +-- cranelift/codegen/src/ctxhash.rs | 1 - cranelift/codegen/src/data_value.rs | 1 - cranelift/codegen/src/dominator_tree.rs | 1 - cranelift/codegen/src/egraph.rs | 3 +-- cranelift/codegen/src/egraph/elaborate.rs | 3 +-- cranelift/codegen/src/incremental_cache.rs | 1 - cranelift/codegen/src/inline.rs | 1 - cranelift/codegen/src/ir/debug_tags.rs | 1 - cranelift/codegen/src/ir/entities.rs | 1 - cranelift/codegen/src/ir/exception_table.rs | 1 - cranelift/codegen/src/ir/immediates.rs | 2 -- cranelift/codegen/src/ir/layout.rs | 1 - cranelift/codegen/src/ir/pcc.rs | 1 - cranelift/codegen/src/ir/stackslot.rs | 1 - cranelift/codegen/src/ir/trapcode.rs | 1 - cranelift/codegen/src/ir/types.rs | 1 - cranelift/codegen/src/isa/aarch64/abi.rs | 2 -- cranelift/codegen/src/isa/aarch64/inst/args.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/emit.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs | 3 +-- cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/mod.rs | 3 --- cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/unwind.rs | 1 - .../codegen/src/isa/aarch64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/aarch64/lower.rs | 1 - cranelift/codegen/src/isa/aarch64/lower/isle.rs | 3 --- .../src/isa/aarch64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/aarch64/mod.rs | 2 -- cranelift/codegen/src/isa/aarch64/pcc.rs | 1 - cranelift/codegen/src/isa/aarch64/settings.rs | 1 - cranelift/codegen/src/isa/mod.rs | 3 +-- cranelift/codegen/src/isa/pulley32.rs | 1 - cranelift/codegen/src/isa/pulley64.rs | 1 - cranelift/codegen/src/isa/pulley_shared/abi.rs | 2 -- cranelift/codegen/src/isa/pulley_shared/inst/args.rs | 2 -- cranelift/codegen/src/isa/pulley_shared/inst/emit.rs | 1 - cranelift/codegen/src/isa/pulley_shared/inst/mod.rs | 1 - cranelift/codegen/src/isa/pulley_shared/inst/regs.rs | 1 - cranelift/codegen/src/isa/pulley_shared/lower.rs | 1 - cranelift/codegen/src/isa/pulley_shared/lower/isle.rs | 1 - .../isa/pulley_shared/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/pulley_shared/mod.rs | 2 -- cranelift/codegen/src/isa/pulley_shared/settings.rs | 1 - cranelift/codegen/src/isa/riscv64/abi.rs | 2 -- cranelift/codegen/src/isa/riscv64/inst/args.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/emit.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/encode.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/imms.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/mod.rs | 4 ---- cranelift/codegen/src/isa/riscv64/inst/regs.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/unwind.rs | 1 - .../codegen/src/isa/riscv64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 - cranelift/codegen/src/isa/riscv64/lower.rs | 1 - cranelift/codegen/src/isa/riscv64/lower/isle.rs | 3 --- .../src/isa/riscv64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/riscv64/mod.rs | 2 -- cranelift/codegen/src/isa/riscv64/settings.rs | 1 - cranelift/codegen/src/isa/s390x/abi.rs | 2 -- cranelift/codegen/src/isa/s390x/inst/args.rs | 1 - cranelift/codegen/src/isa/s390x/inst/emit.rs | 1 - cranelift/codegen/src/isa/s390x/inst/emit_tests.rs | 1 - cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 - cranelift/codegen/src/isa/s390x/inst/mod.rs | 3 --- cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 - cranelift/codegen/src/isa/s390x/inst/unwind.rs | 1 - .../codegen/src/isa/s390x/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/s390x/lower.rs | 1 - cranelift/codegen/src/isa/s390x/lower/isle.rs | 4 ---- .../src/isa/s390x/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/s390x/mod.rs | 2 -- cranelift/codegen/src/isa/s390x/settings.rs | 1 - cranelift/codegen/src/isa/unwind.rs | 1 - cranelift/codegen/src/isa/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/unwind/winarm64.rs | 1 - cranelift/codegen/src/isa/unwind/winx64.rs | 1 - cranelift/codegen/src/isa/x64/abi.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/args.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/external.rs | 2 -- cranelift/codegen/src/isa/x64/inst/mod.rs | 3 --- cranelift/codegen/src/isa/x64/inst/regs.rs | 2 -- cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs | 1 - cranelift/codegen/src/isa/x64/lower/isle.rs | 1 - .../codegen/src/isa/x64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 3 +-- cranelift/codegen/src/lib.rs | 11 +++++++---- cranelift/codegen/src/machinst/abi.rs | 4 +--- cranelift/codegen/src/machinst/blockorder.rs | 2 +- cranelift/codegen/src/machinst/buffer.rs | 6 ------ cranelift/codegen/src/machinst/inst_common.rs | 1 - cranelift/codegen/src/machinst/lower.rs | 8 +++----- cranelift/codegen/src/machinst/mod.rs | 1 - cranelift/codegen/src/machinst/reg.rs | 1 - cranelift/codegen/src/machinst/vcode.rs | 4 +--- cranelift/codegen/src/opts.rs | 1 - cranelift/codegen/src/opts/generated_code.rs | 1 - cranelift/codegen/src/remove_constant_phis.rs | 2 +- cranelift/codegen/src/settings.rs | 1 - cranelift/codegen/src/souper_harvest.rs | 1 - cranelift/codegen/src/verifier/mod.rs | 1 - cranelift/codegen/src/write.rs | 1 - 108 files changed, 25 insertions(+), 161 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 39e6898c6b38..fe35d822d676 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,7 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && - cargo check -p cranelift-assembler-x64 && + cargo check -p cranelift-assembler-x64 --lib && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 03040f037d3c..9376b79ddd2c 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -71,7 +71,7 @@ std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # deprecated (we (i) always use hashbrown, and (ii) don't support a # no_std build anymore). The feature remains for backward # compatibility as a no-op. -core = ["cranelift-assembler-x64/core"] +core = [] # Enable the `to_capstone` method on TargetIsa, for constructing a Capstone # context, and the `disassemble` method on `MachBufferFinalized`. diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index b915db0f79e7..eecb38096d1b 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,6 +61,7 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. +use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, dominator_tree::DominatorTree, @@ -71,7 +72,6 @@ use crate::{ trace, }; use cranelift_entity::{EntityRef, packed_option::PackedOption}; -use rustc_hash::{FxHashMap, FxHashSet}; /// For a given program point, the vector of last-store instruction /// indices for each disjoint category of abstract state. @@ -400,4 +400,3 @@ fn get_ext_opcode(op: Opcode) -> Option { _ => Some(op), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 7148046ae9c1..ea7de766006e 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -6,7 +6,6 @@ use core::hash::{Hash, Hasher}; use hashbrown::hash_table::HashTable; -use core::hash::{Hash, Hasher}; /// Trait that allows for equality comparison given some external /// context. diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index 26a66d53694e..a2e69a724e1b 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -420,4 +420,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 90e700d0097d..23d099a4251a 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -771,4 +771,3 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph.rs index a8d6a80ee3b2..280109470d01 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph.rs @@ -1,5 +1,6 @@ //! Support for egraphs represented in the DataFlowGraph. +use crate::FxHashSet; use crate::alias_analysis::{AliasAnalysis, LastStores}; use crate::ctxhash::{CtxEq, CtxHash, NullCtx}; use crate::cursor::{Cursor, CursorPosition, FuncCursor}; @@ -24,7 +25,6 @@ use core::hash::Hasher; use cranelift_control::ControlPlane; use cranelift_entity::SecondaryMap; use cranelift_entity::packed_option::ReservedValue; -use rustc_hash::FxHashSet; use smallvec::SmallVec; mod cost; @@ -1110,4 +1110,3 @@ pub(crate) struct Stats { pub(crate) elaborate_func_post_insts: u64, pub(crate) eclass_size_limit: u64, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index ec617344b9ba..86443e5cb126 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -11,10 +11,10 @@ use crate::ir::{Block, Function, Inst, Value, ValueDef}; use crate::loop_analysis::{Loop, LoopAnalysis}; use crate::scoped_hash_map::ScopedHashMap; use crate::trace; +use crate::{FxHashMap, FxHashSet}; use alloc::vec::Vec; use cranelift_control::ControlPlane; use cranelift_entity::{EntitySet, SecondaryMap, packed_option::ReservedValue}; -use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; pub(crate) struct Elaborator<'a> { @@ -865,4 +865,3 @@ impl<'a> Elaborator<'a> { self.stats.elaborate_func_post_insts += self.func.dfg.num_insts() as u64; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index 973cca13ece1..a597d18869ce 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -239,4 +239,3 @@ pub fn try_finish_recompile(func: &Function, bytes: &[u8]) -> Result Err(RecompileError::Deserialize(err)), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/inline.rs b/cranelift/codegen/src/inline.rs index 6e6756871545..ac150c598980 100644 --- a/cranelift/codegen/src/inline.rs +++ b/cranelift/codegen/src/inline.rs @@ -1584,4 +1584,3 @@ fn create_constants(allocs: &mut InliningAllocs, func: &mut ir::Function, callee allocs.constants[*callee_constant] = Some(inlined_constant).into(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/debug_tags.rs b/cranelift/codegen/src/ir/debug_tags.rs index d2ca049f6c53..39d137c2973b 100644 --- a/cranelift/codegen/src/ir/debug_tags.rs +++ b/cranelift/codegen/src/ir/debug_tags.rs @@ -139,4 +139,3 @@ impl core::fmt::Display for DebugTag { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/entities.rs b/cranelift/codegen/src/ir/entities.rs index a1ab10662d7d..cbb8f3097aff 100644 --- a/cranelift/codegen/src/ir/entities.rs +++ b/cranelift/codegen/src/ir/entities.rs @@ -562,4 +562,3 @@ mod tests { assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 80730652054a..4130f23792b4 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -287,4 +287,3 @@ impl<'a> Display for DisplayExceptionTable<'a> { Ok(()) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index ce89abd2307d..79b9432960af 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1,4 +1,3 @@ - //! Immediate operands for Cranelift instructions //! //! This module defines the types of immediate operands that can appear on Cranelift instructions. @@ -1959,4 +1958,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/layout.rs b/cranelift/codegen/src/ir/layout.rs index 2a2d139018fe..1284ab65676e 100644 --- a/cranelift/codegen/src/ir/layout.rs +++ b/cranelift/codegen/src/ir/layout.rs @@ -1193,4 +1193,3 @@ mod tests { assert_eq!(layout.pp_cmp(i3, i2), Ordering::Greater) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index d1bf7ea62dba..8b9a3cc6bb6e 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -79,7 +79,6 @@ use crate::machinst::{BlockIndex, LowerBackend, VCode}; use crate::trace; use core::fmt; use regalloc2::Function as _; -use core::fmt; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 3c10fdc98026..1ad2a5d7d871 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -249,4 +249,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/trapcode.rs b/cranelift/codegen/src/ir/trapcode.rs index f990f312b94f..e3fbcfbb4a50 100644 --- a/cranelift/codegen/src/ir/trapcode.rs +++ b/cranelift/codegen/src/ir/trapcode.rs @@ -145,4 +145,3 @@ mod tests { assert_eq!("users".parse::(), Err(())); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs index 48e98fd352d2..bc7704cf0662 100644 --- a/cranelift/codegen/src/ir/types.rs +++ b/cranelift/codegen/src/ir/types.rs @@ -622,4 +622,3 @@ mod tests { assert_eq!(Type::int_with_byte_size(evil), None); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 89b7546e0a0d..8f1afce63a87 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -17,7 +17,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because @@ -1633,4 +1632,3 @@ fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv { env } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index d912aee4dd79..a382a5ef725a 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -724,4 +724,3 @@ impl TestBitAndBranchKind { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index b5bb377591df..06e0eb017708 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -3685,4 +3685,3 @@ fn emit_return_call_common_sequence( sink.put4(key.enc_auti_hint()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index fdca784dd038..d8e6cd6a2083 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -27,7 +27,7 @@ fn test_aarch64_binemit() { // // #!/bin/sh // tmp=`mktemp /tmp/XXXXXXXX.o` - // aarch64-linux-gnu-as /dev/corein -o $tmp + // aarch64-linux-gnu-as /dev/stdin -o $tmp // aarch64-linux-gnu-objdump -d $tmp // rm -f $tmp // @@ -7970,4 +7970,3 @@ fn test_cond_invert() { assert_eq!(cond.invert().invert(), cond); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index 69a1ca5312e7..fcd67deed576 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -1240,4 +1240,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 7e02b79c219a..90ba2ef0c75d 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -14,8 +14,6 @@ use alloc::vec::Vec; use core::fmt::Write; use core::slice; use smallvec::{SmallVec, smallvec}; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub(crate) mod regs; pub(crate) use self::regs::*; @@ -3114,4 +3112,3 @@ mod tests { assert_eq!(expected, core::mem::size_of::()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index c625d99d964d..7db69df4ebe4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -279,4 +279,3 @@ pub fn pretty_print_vreg_vector(reg: Reg, size: VectorSize) -> String { pub fn pretty_print_vreg_element(reg: Reg, idx: usize, size: ScalarSize) -> String { show_vreg_element(reg, idx as u8, size) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs index 25a095983c42..9378c46fa53b 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs @@ -175,4 +175,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs index 99c9f2f95592..6d51a380433f 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.rs +++ b/cranelift/codegen/src/isa/aarch64/lower.rs @@ -143,4 +143,3 @@ impl LowerBackend for AArch64Backend { type FactFlowState = pcc::FactFlowState; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 6898f2852403..3e82af2a9c8e 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -35,8 +35,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::u32; use regalloc2::PReg; -use alloc::boxed::Box; -use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxCallIndInfo = Box>; @@ -860,4 +858,3 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.backend.flags.is_pic() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 3867a060b7f3..2e0f7bd77dda 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -14,4 +14,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_aarch64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 707f88bc1b81..2f80ad9fa29b 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -16,7 +16,6 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Aarch64Architecture, Architecture, OperatingSystem, Triple}; // New backend: @@ -279,4 +278,3 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs index 3b5e31d11c0e..e5ee1919803e 100644 --- a/cranelift/codegen/src/isa/aarch64/pcc.rs +++ b/cranelift/codegen/src/isa/aarch64/pcc.rs @@ -568,4 +568,3 @@ fn check_store_addr( let _output_fact = ctx.store(&fact, ty, None)?; Ok(()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/settings.rs b/cranelift/codegen/src/isa/aarch64/settings.rs index 21031399b5eb..2cda69446ff3 100644 --- a/cranelift/codegen/src/isa/aarch64/settings.rs +++ b/cranelift/codegen/src/isa/aarch64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/arm64.rs`. include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2c44409de892..2bc2033983ef 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -50,7 +50,7 @@ use crate::CodegenResult; use crate::ir::{self, Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::{UnwindInfoKind, systemv::RegisterMappingError}; -use crate::machinst::{CompiledCodeStencil, TextSectionBuilder}; +use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder}; use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; @@ -499,4 +499,3 @@ impl Debug for &dyn TargetIsa { ) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley32.rs b/cranelift/codegen/src/isa/pulley32.rs index e3467275472e..b337274660d0 100644 --- a/cranelift/codegen/src/isa/pulley32.rs +++ b/cranelift/codegen/src/isa/pulley32.rs @@ -11,4 +11,3 @@ impl PulleyTargetKind for Pulley32 { PointerWidth::PointerWidth32 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley64.rs b/cranelift/codegen/src/isa/pulley64.rs index 234840c45eb5..31b1d08a04b2 100644 --- a/cranelift/codegen/src/isa/pulley64.rs +++ b/cranelift/codegen/src/isa/pulley64.rs @@ -11,4 +11,3 @@ impl PulleyTargetKind for Pulley64 { PointerWidth::PointerWidth64 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index efb7cd7f6628..de32099a14a7 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,7 +15,6 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). @@ -986,4 +985,3 @@ fn create_reg_environment() -> MachineEnv { scratch_by_class: [None, None, None], } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index 3520abec8d24..e97e3303ef99 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -6,7 +6,6 @@ use crate::machinst::abi::StackAMode; use core::fmt; use pulley_interpreter::encode; use pulley_interpreter::regs::Reg as _; -use core::fmt; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). @@ -780,4 +779,3 @@ impl fmt::Display for AddrG32Bne { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs index 25614218b03b..74082b4260c3 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs @@ -707,4 +707,3 @@ fn patch_pc_rel_offset

( assert_eq!(*chunk, [0, 0, 0, 0]); *chunk = (end - start - 4).to_le_bytes(); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index 497ba5e2031e..d76705a7fb9f 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -952,4 +952,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs index 069050e7cd55..90f7d36e104b 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs @@ -162,4 +162,3 @@ define_registers! { v_reg(30) => v30, writable_v30; v_reg(31) => v31, writable_v31; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.rs b/cranelift/codegen/src/isa/pulley_shared/lower.rs index b436d1d3e46e..8dd5a0cea50c 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower.rs @@ -34,4 +34,3 @@ where type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs index baa93a5eb1bc..d72b6a023789 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs @@ -327,4 +327,3 @@ where let mut isle_ctx = PulleyIsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs index 6b0853db8f25..45dd7050dc3c 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_pulley_shared.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 8bcaa2eae62a..0b781e467a08 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -22,7 +22,6 @@ use alloc::vec::Vec; use core::fmt::Debug; use core::marker::PhantomData; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; pub use settings::Flags as PulleyFlags; @@ -313,4 +312,3 @@ impl PulleyFlags { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/settings.rs b/cranelift/codegen/src/isa/pulley_shared/settings.rs index d611e3a6f2a5..5d4fd19ed116 100644 --- a/cranelift/codegen/src/isa/pulley_shared/settings.rs +++ b/cranelift/codegen/src/isa/pulley_shared/settings.rs @@ -14,4 +14,3 @@ use core::fmt; include!(concat!(env!("OUT_DIR"), "/settings-pulley.rs")); impl IsaFlags for Flags {} -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index f14805735aff..f53eee9a53a0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -21,7 +21,6 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). @@ -1056,4 +1055,3 @@ impl Riscv64MachineDeps { insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index d710f4348e46..918a4854b3a3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -1946,4 +1946,3 @@ impl ZcbMemOp { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 714271546539..5e631c3af1d3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -2885,4 +2885,3 @@ fn return_call_emit_impl( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 09880464c68e..3b0cf59b633f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -2283,4 +2283,3 @@ fn riscv64_worst_case_instruction_size() { println!("calculate max size is {} , inst is {:?}", max.0, max.1); assert!(max.0 <= Inst::worst_case_size()); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/encode.rs b/cranelift/codegen/src/isa/riscv64/inst/encode.rs index b167f319ccfe..048fc2af05b5 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs @@ -718,4 +718,3 @@ pub fn encode_fp_rrrr( funct7, ) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 5e9f0faeee45..92a8ceb60b83 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -371,4 +371,3 @@ mod test { assert!(Inst::imm_min() == i32::MIN as i64 - 2048); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 9043aa77bb3b..9349d64cd08f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -18,9 +18,6 @@ use alloc::vec::Vec; use core::fmt::Write; use regalloc2::RegClass; use smallvec::{SmallVec, smallvec}; -use alloc::boxed::Box; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; @@ -1943,4 +1940,3 @@ mod test { assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/regs.rs b/cranelift/codegen/src/isa/riscv64/inst/regs.rs index d1e9fa7cd00f..76493732bfe1 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/regs.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/regs.rs @@ -151,4 +151,3 @@ pub const fn pf_reg(enc: usize) -> PReg { pub const fn pv_reg(enc: usize) -> PReg { PReg::new(enc, RegClass::Vector) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs index 0edc32ba221f..0b2ef040b19c 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs @@ -171,4 +171,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index dcbda4aa1850..269e6481b506 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -1148,4 +1148,3 @@ pub trait VecInstOverlapInfo { self.forbids_src_dst_overlaps() || (mask.is_enabled() && self.forbids_mask_dst_overlaps()) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower.rs b/cranelift/codegen/src/isa/riscv64/lower.rs index 8de92855b2f8..117778f820b3 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.rs +++ b/cranelift/codegen/src/isa/riscv64/lower.rs @@ -33,4 +33,3 @@ impl LowerBackend for Riscv64Backend { type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index 6a8aed5eb907..a2a7d0c196e6 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -24,8 +24,6 @@ use crate::{ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::PReg; -use alloc::boxed::Box; -use alloc::vec::Vec; use wasmtime_math::{f32_cvt_to_int_bounds, f64_cvt_to_int_bounds}; type BoxCallInfo = Box>; @@ -751,4 +749,3 @@ pub(crate) fn lower_branch( let mut isle_ctx = RV64IsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs index 9fb78bfb80ca..ad8466108a3b 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_riscv64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index fa320acab489..ca0a1a13e2e9 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -17,7 +17,6 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; mod abi; pub(crate) mod inst; @@ -293,4 +292,3 @@ fn isa_constructor( let backend = Riscv64Backend::new_with_flags(triple, shared_flags, isa_flags); Ok(backend.wrapped()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/settings.rs b/cranelift/codegen/src/isa/riscv64/settings.rs index f4ca3fb3a88a..c896dd5fe911 100644 --- a/cranelift/codegen/src/isa/riscv64/settings.rs +++ b/cranelift/codegen/src/isa/riscv64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/riscv64/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-riscv64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 5c30ddab3ff2..738e037047d3 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -148,7 +148,6 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -1628,4 +1627,3 @@ fn tail_create_machine_env() -> MachineEnv { scratch_by_class: [None, None, None], } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/args.rs b/cranelift/codegen/src/isa/s390x/inst/args.rs index 5e114104b320..33e790673b61 100644 --- a/cranelift/codegen/src/isa/s390x/inst/args.rs +++ b/cranelift/codegen/src/isa/s390x/inst/args.rs @@ -269,4 +269,3 @@ impl PrettyPrint for Cond { s.to_string() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index e218fe55454a..5baef0fede8a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3559,4 +3559,3 @@ impl Inst { state.clear_post_insn(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index 9f5afa33448e..aa6f9e6b19c9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -13496,4 +13496,3 @@ fn test_s390x_binemit() { assert_eq!(expected_encoding, actual_encoding); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index edb66ba08196..9559f34ac7f8 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -200,4 +200,3 @@ impl PrettyPrint for UImm32Shifted { format!("{}", self.bits) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 427c8cd05292..762f6c58d27e 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -11,8 +11,6 @@ use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::Write; use smallvec::SmallVec; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; pub mod imms; @@ -3552,4 +3550,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index eebcb36a33df..d3985bb9d20b 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -184,4 +184,3 @@ pub fn pretty_print_regpair_mod_lo(rd: WritableRegPair, ri: Reg) -> String { pub fn pretty_print_fpr(reg: Reg) -> (String, Option) { (show_reg(reg), maybe_show_fpr(reg)) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind.rs b/cranelift/codegen/src/isa/s390x/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs index a37ca84767d9..6ae2c7e262d9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs @@ -216,4 +216,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index c111eee9c915..9af0b96147e5 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -28,4 +28,3 @@ impl LowerBackend for S390xBackend { type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index 56176476ecb8..561fabd9561e 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -27,9 +27,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::cell::Cell; use regalloc2::PReg; -use alloc::boxed::Box; -use core::cell::Cell; -use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxReturnCallInfo = Box>; @@ -862,4 +859,3 @@ fn condcode_is_signed(cc: IntCC) -> bool { IntCC::UnsignedLessThan => false, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index c32fdefdc440..a6daad546b62 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_s390x.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index d7e97f6f896a..6bc40484153d 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -16,7 +16,6 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; // New backend: @@ -237,4 +236,3 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/settings.rs b/cranelift/codegen/src/isa/s390x/settings.rs index 16a717f9e7c7..5bf89030f19d 100644 --- a/cranelift/codegen/src/isa/s390x/settings.rs +++ b/cranelift/codegen/src/isa/s390x/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/s390x/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index 7b842ac7e4ab..ada37b03ccbb 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -15,7 +15,6 @@ pub mod winx64; pub mod winarm64; /// CFA-based unwind information used on SystemV. -#[cfg(feature = "unwind")] pub type CfaUnwindInfo = systemv::UnwindInfo; /// Expected unwind info type. diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index 0fb19d0408c7..5989e0b2a12b 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -286,4 +286,3 @@ impl UnwindInfo { fde } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winarm64.rs b/cranelift/codegen/src/isa/unwind/winarm64.rs index 803867af2a85..3d3cdd8fcf48 100644 --- a/cranelift/codegen/src/isa/unwind/winarm64.rs +++ b/cranelift/codegen/src/isa/unwind/winarm64.rs @@ -315,4 +315,3 @@ pub(crate) fn create_unwind_info_from_insts( Ok(UnwindInfo { unwind_codes }) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winx64.rs b/cranelift/codegen/src/isa/unwind/winx64.rs index e352dc6351df..38cb46b83b55 100644 --- a/cranelift/codegen/src/isa/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/unwind/winx64.rs @@ -310,4 +310,3 @@ fn ensure_unwind_offset(offset: u32) -> CodegenResult { } Ok(offset as u8) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index e00689769b40..b3a8dfed44a0 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -13,10 +13,10 @@ use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use args::*; -use std::sync::OnceLock; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -1346,4 +1346,3 @@ fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv { env } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index c5e6a117ec04..233299966a16 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,8 +7,8 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use core::fmt; use alloc::string::String; +use core::fmt; /// An extension trait for converting `Writable{Xmm,Gpr}` to `Writable`. pub trait ToWritableReg { @@ -1061,4 +1061,3 @@ impl OperandSize { self.to_bytes() * 8 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 7d9e7a6e7eba..1bd8b0f6b28e 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -2,7 +2,7 @@ //! //! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases. //! -//! to see coreout: cargo test -- --nocapture +//! to see stdout: cargo test -- --nocapture //! //! for this specific case, as of 24 Aug 2020: //! @@ -383,4 +383,3 @@ fn test_x64_emit() { assert_eq!(expected_encoding, actual_encoding, "{expected_printing}"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 82c7f089ed77..8d41f2e6d484 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -8,7 +8,6 @@ use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; use regalloc2::{PReg, RegClass}; -use alloc::string::String; /// Define the types of registers Cranelift will use. #[derive(Clone, Debug)] @@ -563,4 +562,3 @@ mod tests { assert_eq!(pair.to_string(None), "(%v500 <- %v400)"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 451529d81e11..8bff031e3fc4 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -18,8 +18,6 @@ use core::fmt::{self, Write}; use core::slice; use cranelift_assembler_x64 as asm; use smallvec::{SmallVec, smallvec}; -use core::fmt::{self, Write}; -use alloc::string::{String, ToString}; pub mod args; mod emit; @@ -1680,4 +1678,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 867b26b6b929..b1416e88df5c 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -10,7 +10,6 @@ use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; use regalloc2::{PReg, RegClass, VReg}; -use alloc::string::String; // Constructors for Regs. @@ -175,4 +174,3 @@ pub fn pretty_print_reg(reg: Reg, size: u8) -> String { name } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs index ecbe379cd7da..3f46843ab4f4 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs @@ -202,4 +202,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs index f6d80f5e531f..f848a5baf76f 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs @@ -14,4 +14,3 @@ impl crate::isa::unwind::winx64::RegisterMapper for RegisterMapper { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 3917b4203ca5..57bfa06ee7fd 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -1249,4 +1249,3 @@ const I8X16_USHR_MASKS: [u8; 128] = [ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ]; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index 1bc434f23b5a..c48996ec46d6 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -14,4 +14,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_x64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index c67ccc5b654b..37a386504347 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -10,7 +10,7 @@ use crate::isa::unwind::systemv; use crate::isa::x64::settings as x64_settings; use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey}; use crate::machinst::{ - CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, + CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; use crate::result::{CodegenError, CodegenResult}; @@ -264,4 +264,3 @@ fn isa_constructor( let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags)?; Ok(backend.wrapped()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index fe017ca4468e..7e006e41014a 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -21,9 +21,14 @@ extern crate alloc; extern crate std; #[cfg(not(feature = "std"))] -use hashbrown::{HashMap, hash_map}; +use hashbrown::{HashMap, HashSet, hash_map}; #[cfg(feature = "std")] -use std::collections::{HashMap, hash_map}; +use std::collections::{HashMap, HashSet, hash_map}; + +/// Type alias for a hash map that uses the Fx hashing algorithm. +pub type FxHashMap = HashMap; +/// Type alias for a hash set that uses the Fx hashing algorithm. +pub type FxHashSet = HashSet; pub use crate::context::Context; pub use crate::value_label::{LabelValueLoc, ValueLabelsRanges, ValueLocRange}; @@ -43,8 +48,6 @@ include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); #[macro_use] mod machinst; -mod prelude; - pub mod binemit; pub mod cfg_printer; pub mod cursor; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index ce4b6740e3f2..08f275ccca76 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -99,6 +99,7 @@ //! ABI. See each platform's `abi.rs` implementation for details. use crate::CodegenError; +use crate::FxHashMap; use crate::HashMap; use crate::entity::SecondaryMap; use crate::ir::{ArgumentExtension, ArgumentPurpose, ExceptionTag, Signature}; @@ -109,9 +110,7 @@ use crate::{ir, isa}; use crate::{machinst::*, trace}; use alloc::boxed::Box; use core::marker::PhantomData; -use hashbrown::HashMap; use regalloc2::{MachineEnv, PReg, PRegSet}; -use rustc_hash::FxHashMap; use smallvec::smallvec; /// A small vector of instructions (with some reasonable size); appropriate for @@ -2616,4 +2615,3 @@ mod tests { assert_eq!(core::mem::size_of::(), 24); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 9e48e2c4d607..671426e600b2 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -64,8 +64,8 @@ use crate::dominator_tree::DominatorTree; use crate::entity::SecondaryMap; use crate::inst_predicates::visit_block_succs; use crate::ir::{Block, Function, Inst, Opcode}; +use crate::{FxHashMap, FxHashSet}; use crate::{machinst::*, trace}; -use rustc_hash::{FxHashMap, FxHashSet}; /// Mapping from CLIF BBs to VCode BBs. #[derive(Debug)] diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index 1f05b5b3fc5a..abd5396178db 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -189,11 +189,6 @@ use core::ops::Range; use cranelift_control::ControlPlane; use cranelift_entity::{PrimaryMap, SecondaryMap, entity_impl}; use smallvec::SmallVec; -use core::cmp::Ordering; -use alloc::collections::BinaryHeap; -use core::mem; -use alloc::string::String; -use alloc::vec::Vec; #[cfg(feature = "enable-serde")] use serde::{Deserialize, Serialize}; @@ -2915,4 +2910,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/inst_common.rs b/cranelift/codegen/src/machinst/inst_common.rs index 1a15cde4e1fa..b077dd3b6112 100644 --- a/cranelift/codegen/src/machinst/inst_common.rs +++ b/cranelift/codegen/src/machinst/inst_common.rs @@ -14,4 +14,3 @@ pub struct InsnInput { pub(crate) insn: IRInst, pub(crate) input: usize, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 84fc96654dff..c3ce9fa9c96c 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -22,12 +22,11 @@ use crate::machinst::{ }; use crate::settings::Flags; use crate::{CodegenError, CodegenResult, trace}; +use crate::{FxHashMap, FxHashSet}; use alloc::vec::Vec; use core::fmt::Debug; use cranelift_control::ControlPlane; -use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; -use core::fmt::Debug; use super::{VCodeBuildDirection, VRegAllocator}; @@ -39,7 +38,7 @@ pub type InstOutput = SmallVec<[ValueRegs; 2]>; /// any side-effecting op (for this purpose, loads are also considered /// side-effecting, to avoid subtle questions w.r.t. the memory model), and /// furthermore, it is guaranteed that for any two instructions A and B such -/// that color(A) == color(B), either A dominates B and B pocoreominates A, or +/// that color(A) == color(B), either A dominates B and B postdominates A, or /// vice-versa. (For now, in practice, only ops in the same basic block can ever /// have the same color, trivially providing the second condition.) Intuitively, /// this means that the ops of the same color must always execute "together", as @@ -1390,7 +1389,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { /// Instruction input/output queries. impl<'func, I: VCodeInst> Lower<'func, I> { - /// Get the incoreata for a given IR instruction. + /// Get the instdata for a given IR instruction. pub fn data(&self, ir_inst: Inst) -> &InstructionData { &self.f.dfg.insts[ir_inst] } @@ -1798,4 +1797,3 @@ mod tests { assert_eq!(uses[v5], ValueUseState::Unused); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 61ebb9bc0800..c327803d5fb3 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -60,7 +60,6 @@ use cranelift_control::ControlPlane; use cranelift_entity::PrimaryMap; use regalloc2::VReg; use smallvec::{SmallVec, smallvec}; -use alloc::string::String; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index 5d364601297d..dd28ee05f4c8 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -563,4 +563,3 @@ pub trait PrettyPrint { self.pretty_print(0) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index a1fb9c9e12bb..abf575f8847a 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -18,6 +18,7 @@ //! backend pipeline. use crate::CodegenError; +use crate::FxHashMap; use crate::ir::pcc::*; use crate::ir::{self, Constant, ConstantData, ValueLabel, types}; use crate::ranges::Ranges; @@ -29,11 +30,9 @@ use regalloc2::{ Edit, Function as RegallocFunction, InstOrEdit, InstPosition, InstRange, Operand, OperandConstraint, OperandKind, PRegSet, ProgPoint, RegClass, }; -use rustc_hash::FxHashMap; use crate::HashMap; use crate::hash_map::Entry; - use core::cmp::Ordering; use core::fmt::{self, Write}; use core::mem::take; @@ -2058,4 +2057,3 @@ mod test { // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes. } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 4ec9728f1e35..fc360913b1d9 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -18,7 +18,6 @@ use crate::trace; use core::marker::PhantomData; use cranelift_entity::packed_option::ReservedValue; use smallvec::{SmallVec, smallvec}; -use core::marker::PhantomData; pub type Unit = (); pub type ValueArray2 = [Value; 2]; diff --git a/cranelift/codegen/src/opts/generated_code.rs b/cranelift/codegen/src/opts/generated_code.rs index 2ff9eaef16bc..82208623362a 100644 --- a/cranelift/codegen/src/opts/generated_code.rs +++ b/cranelift/codegen/src/opts/generated_code.rs @@ -16,4 +16,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_opt.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index ae9f3ad6ed24..ab5def4f75b4 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -5,9 +5,9 @@ use crate::ir; use crate::ir::Function; use crate::ir::{Block, BlockArg, BlockCall, Inst, Value}; use crate::timing; +use crate::{FxHashMap, FxHashSet}; use bumpalo::Bump; use cranelift_entity::SecondaryMap; -use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::SmallVec; // A note on notation. For the sake of clarity, this file uses the phrase diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 39899e63480c..158ba139bd42 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -566,4 +566,3 @@ enable_incremental_compilation_cache_checks = false assert_eq!(f.opt_level(), super::OptLevel::Speed); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/souper_harvest.rs b/cranelift/codegen/src/souper_harvest.rs index 5ea25882bae3..02958ed56a71 100644 --- a/cranelift/codegen/src/souper_harvest.rs +++ b/cranelift/codegen/src/souper_harvest.rs @@ -587,4 +587,3 @@ fn post_order_dfs( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 0aac5d0d024f..c57846c59c1f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2314,4 +2314,3 @@ mod tests { assert_err_with_msg!(errors, "block0 cannot be empty"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index ab4b51effee1..c0025aa6fca3 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -749,4 +749,3 @@ mod tests { ); } } -use crate::prelude::*; From 9e39486a2f026d227eecbda645e9bc4492a69c1a Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 08:56:34 +0100 Subject: [PATCH 31/61] add imports --- cranelift/codegen/src/alias_analysis.rs | 1 + cranelift/codegen/src/dominator_tree.rs | 1 + cranelift/codegen/src/egraph/elaborate.rs | 1 + cranelift/codegen/src/{egraph.rs => egraph/mod.rs} | 1 + cranelift/codegen/src/ir/exception_table.rs | 1 + cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/ir/stackslot.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 1 + cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 1 + cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 1 + cranelift/codegen/src/lib.rs | 2 ++ cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 1 + cranelift/codegen/src/machinst/isle.rs | 2 +- cranelift/codegen/src/machinst/lower.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/settings.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 1 + cranelift/codegen/src/write.rs | 1 + 22 files changed, 23 insertions(+), 1 deletion(-) rename cranelift/codegen/src/{egraph.rs => egraph/mod.rs} (99%) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index eecb38096d1b..ba141d235001 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,6 +61,7 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. +use crate::prelude::*; use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 23d099a4251a..29e65a9ae806 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -4,6 +4,7 @@ use crate::entity::SecondaryMap; use crate::flowgraph::{BlockPredecessor, ControlFlowGraph}; use crate::ir::{Block, Function, Layout, ProgramPoint}; use crate::packed_option::PackedOption; +use crate::prelude::*; use crate::timing; use alloc::vec::Vec; use core::cmp; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index 86443e5cb126..b717fc32df4e 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -9,6 +9,7 @@ use crate::hash_map::Entry as HashEntry; use crate::inst_predicates::is_pure_for_egraph; use crate::ir::{Block, Function, Inst, Value, ValueDef}; use crate::loop_analysis::{Loop, LoopAnalysis}; +use crate::prelude::*; use crate::scoped_hash_map::ScopedHashMap; use crate::trace; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/egraph.rs b/cranelift/codegen/src/egraph/mod.rs similarity index 99% rename from cranelift/codegen/src/egraph.rs rename to cranelift/codegen/src/egraph/mod.rs index 280109470d01..938f632bf892 100644 --- a/cranelift/codegen/src/egraph.rs +++ b/cranelift/codegen/src/egraph/mod.rs @@ -15,6 +15,7 @@ use crate::ir::{ use crate::loop_analysis::LoopAnalysis; use crate::opts::IsleContext; use crate::opts::generated_code::SkeletonInstSimplification; +use crate::prelude::*; use crate::scoped_hash_map::{Entry as ScopedEntry, ScopedHashMap}; use crate::settings::Flags; use crate::take_and_replace::TakeAndReplace; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 4130f23792b4..f92ad688e565 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -19,6 +19,7 @@ use crate::ir::entities::{ExceptionTag, SigRef}; use crate::ir::instructions::ValueListPool; use crate::ir::{BlockCall, Value}; +use crate::prelude::*; use alloc::vec::Vec; use core::fmt::{self, Display, Formatter}; #[cfg(feature = "enable-serde")] diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 79b9432960af..d6f1deb65015 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -4,6 +4,7 @@ //! Each type here should have a corresponding definition in the //! `cranelift-codegen/meta/src/shared/immediates` crate in the meta language. +use crate::prelude::*; use alloc::vec::Vec; use core::cmp::Ordering; use core::fmt::{self, Display, Formatter}; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 1ad2a5d7d871..01bf2ff1a6ab 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -6,6 +6,7 @@ use crate::entity::PrimaryMap; use crate::ir::StackSlot; use crate::ir::entities::{DynamicStackSlot, DynamicType}; +use crate::prelude::*; use core::fmt; use core::str::FromStr; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index b3a8dfed44a0..76eeb9e4a16b 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -8,6 +8,7 @@ use crate::isa::winch; use crate::isa::{CallConv, unwind::UnwindInst, x64::inst::*, x64::settings as x64_settings}; use crate::machinst::abi::*; use crate::machinst::*; +use crate::prelude::*; use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 233299966a16..1ac58c5f8872 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,6 +7,7 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; +use crate::prelude::*; use alloc::string::String; use core::fmt; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 8d41f2e6d484..783f33414cb2 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -4,6 +4,7 @@ use super::{ Amode, Gpr, Inst, LabelUse, MachBuffer, MachLabel, OperandVisitor, OperandVisitorImpl, SyntheticAmode, VCodeConstant, WritableGpr, WritableXmm, Xmm, args::FromWritableReg, }; +use crate::prelude::*; use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 8bff031e3fc4..f6e0b02cb38a 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -8,6 +8,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::isa::x64::settings as x64_settings; use crate::isa::{CallConv, FunctionAlignment}; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; use crate::{machinst::*, trace}; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index b1416e88df5c..62a81a6dd722 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,6 +6,7 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; +use crate::prelude::*; use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 37a386504347..bf41f40c2af5 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -13,6 +13,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::{CodegenError, CodegenResult}; use crate::settings::{self as shared_settings, Flags}; use crate::{Final, MachBufferFinalized}; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 7e006e41014a..2ba4a4db5a4c 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -45,6 +45,8 @@ pub use gimli; // Pull in generated the `isle_numerics_methods` macro. include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); +mod prelude; + #[macro_use] mod machinst; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 08f275ccca76..b885a0275c10 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -105,6 +105,7 @@ use crate::entity::SecondaryMap; use crate::ir::{ArgumentExtension, ArgumentPurpose, ExceptionTag, Signature}; use crate::ir::{StackSlotKey, types::*}; use crate::isa::TargetIsa; +use crate::prelude::*; use crate::settings::ProbestackStrategy; use crate::{ir, isa}; use crate::{machinst::*, trace}; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index abd5396178db..da95e541ff6b 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -177,6 +177,7 @@ use crate::isa::unwind::UnwindInst; use crate::machinst::{ BlockIndex, MachInstLabelUse, TextSectionBuilder, VCodeConstant, VCodeConstants, VCodeInst, }; +use crate::prelude::*; use crate::trace; use crate::{MachInstEmitState, ir}; use crate::{VCodeConstantData, timing}; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index f73ede5b257b..8a64fab294f3 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -641,7 +641,7 @@ macro_rules! isle_lower_prelude_methods { et: ExceptionTable, labels: &MachLabelSlice, ) -> OptionTryCallInfo { - let mut exception_handlers = vec![]; + let mut exception_handlers = alloc::vec![]; let mut labels = labels.iter().cloned(); for item in self.lower_ctx.dfg().exception_tables[et].clone().items() { match item { diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index c3ce9fa9c96c..0dcc5170a97a 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -20,6 +20,7 @@ use crate::machinst::{ VCodeBuilder, VCodeConstant, VCodeConstantData, VCodeConstants, VCodeInst, ValueRegs, Writable, writable_value_regs, }; +use crate::prelude::*; use crate::settings::Flags; use crate::{CodegenError, CodegenResult, trace}; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index abf575f8847a..4cb6b0992cbd 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -21,6 +21,7 @@ use crate::CodegenError; use crate::FxHashMap; use crate::ir::pcc::*; use crate::ir::{self, Constant, ConstantData, ValueLabel, types}; +use crate::prelude::*; use crate::ranges::Ranges; use crate::timing; use crate::trace; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 158ba139bd42..90b835c0965a 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -22,6 +22,7 @@ use crate::constant_hash::{probe, simple_hash}; use crate::isa::TargetIsa; +use crate::prelude::*; use alloc::boxed::Box; use alloc::string::{String, ToString}; use core::fmt; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index c57846c59c1f..64079b289d83 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -77,6 +77,7 @@ use crate::ir::{ ValueList, types, }; use crate::isa::TargetIsa; +use crate::prelude::*; use crate::print_errors::pretty_verifier_error; use crate::settings::FlagsOrIsa; use crate::timing; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index c0025aa6fca3..1961a57dfd9a 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -9,6 +9,7 @@ use crate::ir::immediates::Ieee128; use crate::ir::pcc::Fact; use crate::ir::{Block, DataFlowGraph, Function, Inst, Opcode, SigRef, Type, Value, ValueDef}; use crate::packed_option::ReservedValue; +use crate::prelude::*; use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::{self, Write}; From 679d3efdfa1caf37495ecb58475e63b90093bbcc Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 09:47:49 +0100 Subject: [PATCH 32/61] fix floating issues with libm --- Cargo.lock | 1 + cranelift/codegen/Cargo.toml | 5 +++-- cranelift/codegen/src/ir/immediates.rs | 11 ++++++----- cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 3 +++ cranelift/codegen/src/machinst/vcode.rs | 3 +++ 6 files changed, 17 insertions(+), 7 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 5adfd6c34940..dca90fc5af31 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -766,6 +766,7 @@ dependencies = [ "env_logger 0.11.5", "gimli 0.32.3", "hashbrown 0.15.2", + "libm", "log", "postcard", "proptest", diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 9376b79ddd2c..bc86d1b8d8d6 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -37,13 +37,14 @@ serde = { workspace = true, optional = true } serde_derive = { workspace = true, optional = true } pulley-interpreter = { workspace = true, optional = true } postcard = { workspace = true, optional = true } -gimli = { workspace = true, features = ["write", "std"], optional = true } +gimli = { workspace = true, features = ["write"], optional = true } smallvec = { workspace = true } regalloc2 = { workspace = true, features = ["checker"] } souper-ir = { version = "2.1.0", optional = true } sha2 = { version = "0.10.2", optional = true } rustc-hash = { workspace = true } wasmtime-math = { workspace = true } +libm = { workspace = true, features = ["unstable-public-internals"] } # It is a goal of the cranelift-codegen crate to have minimal external dependencies. # Please don't add any unless they are essential to the task of creating binary # machine code. Integration tests that need external dependencies can be @@ -65,7 +66,7 @@ default = ["std", "unwind", "host-arch", "timing"] # The "std" feature enables use of libstd. The "core" feature enables use # of some minimal std-like replacement libraries. At least one of these two # features need to be enabled. -std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] +std = ["serde?/std", "rustc-hash/std", "gimli/std", "cranelift-control/fuzz"] # The "core" feature used to enable a hashmap workaround, but is now # deprecated (we (i) always use hashbrown, and (ii) don't support a diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index d6f1deb65015..15af5a5ec20f 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -11,6 +11,7 @@ use core::fmt::{self, Display, Formatter}; use core::ops::{Add, BitAnd, BitOr, BitXor, Div, Mul, Neg, Not, Sub}; use core::str::FromStr; use core::{i32, u32}; +use libm::Libm; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; @@ -683,28 +684,28 @@ macro_rules! ieee_float { $( /// Returns the square root of `self`. pub fn sqrt(self) -> Self { - Self::with_float(self.$as_float().sqrt()) + Self::with_float(Libm::<$float_ty>::sqrt(self.$as_float())) } /// Returns the smallest integer greater than or equal to `self`. pub fn ceil(self) -> Self { - Self::with_float(self.$as_float().ceil()) + Self::with_float(Libm::<$float_ty>::ceil(self.$as_float())) } /// Returns the largest integer less than or equal to `self`. pub fn floor(self) -> Self { - Self::with_float(self.$as_float().floor()) + Self::with_float(Libm::<$float_ty>::floor(self.$as_float())) } /// Returns the integer part of `self`. This means that non-integer numbers are always truncated towards zero. pub fn trunc(self) -> Self { - Self::with_float(self.$as_float().trunc()) + Self::with_float(Libm::<$float_ty>::trunc(self.$as_float())) } /// Returns the nearest integer to `self`. Rounds half-way cases to the number /// with an even least significant digit. pub fn round_ties_even(self) -> Self { - Self::with_float(self.$as_float().round_ties_even()) + Self::with_float(libm::generic::rint_round(self.$as_float(), libm::support::Round::Nearest).val) } )? } diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index ada37b03ccbb..c9ea050fb28a 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -14,6 +14,7 @@ pub mod winx64; #[cfg(feature = "unwind")] pub mod winarm64; +#[cfg(feature = "unwind")] /// CFA-based unwind information used on SystemV. pub type CfaUnwindInfo = systemv::UnwindInfo; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index bf41f40c2af5..b4cc5467536a 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -29,6 +29,7 @@ mod lower; mod pcc; pub mod settings; +#[cfg(feature = "unwind")] pub use inst::unwind::systemv::create_cie; /// An X64 backend. @@ -218,6 +219,7 @@ pub fn emit_unwind_info( ) -> CodegenResult> { use crate::isa::unwind::{UnwindInfo, UnwindInfoKind}; Ok(match kind { + #[cfg(feature = "unwind")] UnwindInfoKind::SystemV => { let mapper = self::inst::unwind::systemv::RegisterMapper; Some(UnwindInfo::SystemV( @@ -228,6 +230,7 @@ pub fn emit_unwind_info( )?, )) } + #[cfg(feature = "unwind")] UnwindInfoKind::Windows => Some(UnwindInfo::WindowsX64( crate::isa::unwind::winx64::create_unwind_info_from_insts::< self::inst::unwind::winx64::RegisterMapper, diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 4cb6b0992cbd..8ffebaba177e 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -1278,6 +1278,9 @@ impl VCode { let slot = alloc.as_stack().unwrap(); let slot_offset = self.abi.get_spillslot_offset(slot); let slot_base_to_caller_sp_offset = self.abi.slot_base_to_caller_sp_offset(); + #[cfg(not(feature = "unwind"))] + let caller_sp_to_cfa_offset = 0; + #[cfg(feature = "unwind")] let caller_sp_to_cfa_offset = crate::isa::unwind::systemv::caller_sp_to_cfa_offset(); // NOTE: this is a negative offset because it's relative to the caller's SP From dfe43e8e04a73a64d536b3adda3549289eaf2ee7 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 10:15:01 +0100 Subject: [PATCH 33/61] remove unused import --- cranelift/codegen/src/prelude.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index 5dd5950bdf86..6a3c99912572 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,4 +1,2 @@ pub use alloc::format; -pub use alloc::string::ToString; pub use alloc::vec; - From 74c85e85860a7b3aa70637e464197e767f5c76d9 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 12:16:25 +0100 Subject: [PATCH 34/61] temporarily remove OnceLock --- cranelift/codegen/src/isa/aarch64/abi.rs | 9 +++------ cranelift/codegen/src/isa/pulley_shared/abi.rs | 6 ++---- cranelift/codegen/src/isa/riscv64/abi.rs | 6 ++---- cranelift/codegen/src/isa/s390x/abi.rs | 13 +++---------- cranelift/codegen/src/isa/x64/abi.rs | 9 +++------ cranelift/codegen/src/machinst/abi.rs | 4 ++-- cranelift/codegen/src/machinst/compile.rs | 5 +++-- cranelift/codegen/src/machinst/vcode.rs | 2 +- 8 files changed, 19 insertions(+), 35 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 8f1afce63a87..68e23a6054d9 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -17,7 +17,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because // these ABIs are very similar. @@ -1087,13 +1086,11 @@ impl ABIMachineSpec for AArch64MachineDeps { } } - fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { + fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { if flags.enable_pinned_reg() { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env(true)) + create_reg_env(true) } else { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env(false)) + create_reg_env(false) } } diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index de32099a14a7..07a537b94127 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,7 +15,6 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). pub(crate) type PulleyCallee

= Callee>; @@ -474,9 +473,8 @@ where } } - fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(create_reg_environment) + fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { + create_reg_environment() } fn get_regs_clobbered_by_call( diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index f53eee9a53a0..d8646010d2d0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -21,7 +21,6 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). pub(crate) type Riscv64Callee = Callee; @@ -612,9 +611,8 @@ impl ABIMachineSpec for Riscv64MachineDeps { } } - fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(create_reg_environment) + fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { + create_reg_environment() } fn get_regs_clobbered_by_call( diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 738e037047d3..2c4c281d8051 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -148,7 +148,6 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -904,16 +903,10 @@ impl ABIMachineSpec for S390xMachineDeps { } } - fn get_machine_env(_flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv { + fn get_machine_env(_flags: &settings::Flags, call_conv: isa::CallConv) -> MachineEnv { match call_conv { - isa::CallConv::Tail => { - static TAIL_MACHINE_ENV: OnceLock = OnceLock::new(); - TAIL_MACHINE_ENV.get_or_init(tail_create_machine_env) - } - _ => { - static SYSV_MACHINE_ENV: OnceLock = OnceLock::new(); - SYSV_MACHINE_ENV.get_or_init(sysv_create_machine_env) - } + isa::CallConv::Tail => tail_create_machine_env(), + _ => sysv_create_machine_env(), } } diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 76eeb9e4a16b..2563083f917e 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -17,7 +17,6 @@ use args::*; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -874,13 +873,11 @@ impl ABIMachineSpec for X64ABIMachineSpec { } } - fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { + fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { if flags.enable_pinned_reg() { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env_systemv(true)) + create_reg_env_systemv(true) } else { - static MACHINE_ENV: OnceLock = OnceLock::new(); - MACHINE_ENV.get_or_init(|| create_reg_env_systemv(false)) + create_reg_env_systemv(false) } } diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index b885a0275c10..1474eac342a2 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -575,7 +575,7 @@ pub trait ABIMachineSpec { ) -> u32; /// Get the ABI-dependent MachineEnv for managing register allocation. - fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv; + fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> MachineEnv; /// Get all caller-save registers, that is, registers that we expect /// not to be saved across a call to a callee with the given ABI. @@ -1540,7 +1540,7 @@ impl Callee { } /// Get the ABI-dependent MachineEnv for managing register allocation. - pub fn machine_env(&self) -> &MachineEnv { + pub fn machine_env(&self) -> MachineEnv { M::get_machine_env(&self.flags, self.call_conv) } diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index cd2e7e9d6ac5..9c7d2d55bd26 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -69,7 +69,7 @@ pub fn compile( RegallocAlgorithm::SinglePass => Algorithm::Fastalloc, }; - regalloc2::run(&vcode, vcode.abi.machine_env(), &options) + regalloc2::run(&vcode, &vcode.abi.machine_env(), &options) .map_err(|err| { log::error!( "Register allocation error for vcode\n{vcode:?}\nError: {err:?}\nCLIF for error:\n{f:?}", @@ -82,7 +82,8 @@ pub fn compile( // Run the regalloc checker, if requested. if b.flags().regalloc_checker() { let _tt = timing::regalloc_checker(); - let mut checker = regalloc2::checker::Checker::new(&vcode, vcode.abi.machine_env()); + let machine_env = vcode.abi.machine_env(); + let mut checker = regalloc2::checker::Checker::new(&vcode, &machine_env); checker.prepare(®alloc_result); checker .run() diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 8ffebaba177e..97c467ce212f 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -516,7 +516,7 @@ impl VCodeBuilder { } fn collect_operands(&mut self, vregs: &VRegAllocator) { - let allocatable = PRegSet::from(self.vcode.abi.machine_env()); + let allocatable = PRegSet::from(&self.vcode.abi.machine_env()); for (i, insn) in self.vcode.insts.iter_mut().enumerate() { // Push operands from the instruction onto the operand list. // From 32c540e32c43fe62c353e551704285f80f6e2003 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 12:44:44 +0100 Subject: [PATCH 35/61] add no_std arm support and add it into CI --- .github/workflows/main.yml | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 + cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 + cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 1 + cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 + cranelift/codegen/src/isa/s390x/inst/mod.rs | 1 + cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 + cranelift/codegen/src/isa/s390x/mod.rs | 1 + 15 files changed, 15 insertions(+) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index fe35d822d676..50e7d5bd599c 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -551,6 +551,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && cargo check -p cranelift-assembler-x64 --lib && + cargo check -p cranelift-codegen --no-default-features -F x86,arm64 && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 68e23a6054d9..cb75d3082fb0 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -11,6 +11,7 @@ use crate::isa::aarch64::{inst::*, settings as aarch64_settings}; use crate::isa::unwind::UnwindInst; use crate::isa::winch; use crate::machinst::*; +use crate::prelude::*; use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index fcd67deed576..09aa838b8e82 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -3,6 +3,7 @@ use crate::ir::types::*; use crate::isa::aarch64::inst::{OperandSize, ScalarSize}; use crate::machinst::PrettyPrint; +use crate::prelude::*; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 90ba2ef0c75d..ead759b93028 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -5,6 +5,7 @@ use crate::ir::types::{F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128}; use crate::ir::{MemFlags, Type, types}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; use crate::machinst::{PrettyPrint, Reg, RegClass, Writable}; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 7db69df4ebe4..c9468f46e932 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -5,6 +5,7 @@ use crate::isa::aarch64::inst::ScalarSize; use crate::isa::aarch64::inst::VectorSize; use crate::machinst::RealReg; use crate::machinst::{Reg, RegClass, Writable}; +use crate::prelude::*; use regalloc2::PReg; use regalloc2::VReg; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 2f80ad9fa29b..dafb6364f38d 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -10,6 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index d8646010d2d0..d1d12621dd5c 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -14,6 +14,7 @@ use crate::ir::LibCall; use crate::ir::Signature; use crate::isa::riscv64::settings::Flags as RiscvFlags; use crate::isa::unwind::UnwindInst; +use crate::prelude::*; use crate::settings; use alloc::boxed::Box; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 9349d64cd08f..2addfd65b63a 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -8,6 +8,7 @@ use crate::ir::types::{self, F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128 pub use crate::ir::{ExternalName, MemFlags, Type}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; pub use crate::ir::condcodes::FloatCC; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 269e6481b506..0c8c49f8544b 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -5,6 +5,7 @@ use crate::isa::riscv64::lower::isle::generated_code::{ VecElementWidth, VecLmul, VecMaskMode, VecOpCategory, VecOpMasking, VecTailMode, }; use crate::machinst::{OperandVisitor, RegClass}; +use crate::prelude::*; use core::fmt; use super::{Type, UImm5}; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index ca0a1a13e2e9..5affb19a8a65 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -10,6 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::CodegenResult; use crate::settings::{self as shared_settings, Flags}; use crate::{CodegenError, ir}; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 2c4c281d8051..8c566ff24756 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -143,6 +143,7 @@ use crate::isa; use crate::isa::s390x::{inst::*, settings as s390x_settings}; use crate::isa::unwind::UnwindInst; use crate::machinst::*; +use crate::prelude::*; use crate::settings; use alloc::borrow::ToOwned; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 9559f34ac7f8..e114d9b022b0 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,6 +1,7 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; +use crate::prelude::*; use alloc::string::String; /// An unsigned 12-bit immediate. diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 762f6c58d27e..b61bb215c187 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -5,6 +5,7 @@ use crate::ir::{ExternalName, Type, types}; use crate::isa::s390x::abi::S390xMachineDeps; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; +use crate::prelude::*; use crate::{CodegenError, CodegenResult, settings}; use alloc::boxed::Box; use alloc::string::{String, ToString}; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index d3985bb9d20b..8b0205569b80 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -5,6 +5,7 @@ use regalloc2::PReg; use crate::isa::s390x::inst::{RegPair, WritableRegPair}; use crate::machinst::*; +use crate::prelude::*; //============================================================================= // Registers, the Universe thereof, and printing diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 6bc40484153d..b3f7986b9e8b 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -10,6 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; +use crate::prelude::*; use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; From c047e01fc26ee50a582ae65ad737f5ca7cf71d7f Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 16:45:24 +0100 Subject: [PATCH 36/61] Move most things from std to core and alloc --- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/ctxhash.rs | 1 + cranelift/codegen/src/ir/pcc.rs | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 2 ++ .../codegen/src/isa/aarch64/inst/emit_tests.rs | 2 +- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 2 ++ cranelift/codegen/src/isa/aarch64/lower/isle.rs | 2 ++ cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/abi.rs | 2 ++ .../codegen/src/isa/pulley_shared/inst/args.rs | 1 + cranelift/codegen/src/isa/pulley_shared/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 2 ++ cranelift/codegen/src/isa/riscv64/inst/mod.rs | 3 +++ cranelift/codegen/src/isa/riscv64/lower/isle.rs | 2 ++ cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 2 ++ .../codegen/src/isa/s390x/inst/emit_tests.rs | 16 ++++++++-------- cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 - cranelift/codegen/src/isa/s390x/inst/mod.rs | 4 +++- cranelift/codegen/src/isa/s390x/lower/isle.rs | 3 +++ cranelift/codegen/src/isa/s390x/mod.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 2 +- cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 2 ++ cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 5 +++++ cranelift/codegen/src/machinst/lower.rs | 5 +++-- cranelift/codegen/src/machinst/mod.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/opts.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 4 ++-- 34 files changed, 61 insertions(+), 19 deletions(-) diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 33c3c3b90c51..e84ea6ae1e30 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -66,7 +66,7 @@ default = ["std", "unwind", "host-arch", "timing"] # The "std" feature enables use of libstd. The "core" feature enables use # of some minimal std-like replacement libraries. At least one of these two # features need to be enabled. -std = ["serde?/std", "rustc-hash/std", "gimli/std", "cranelift-control/fuzz"] +std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # The "core" feature used to enable a hashmap workaround, but is now # deprecated (we (i) always use hashbrown, and (ii) don't support a diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index ea7de766006e..7148046ae9c1 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -6,6 +6,7 @@ use core::hash::{Hash, Hasher}; use hashbrown::hash_table::HashTable; +use core::hash::{Hash, Hasher}; /// Trait that allows for equality comparison given some external /// context. diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index 8b9a3cc6bb6e..d1bf7ea62dba 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -79,6 +79,7 @@ use crate::machinst::{BlockIndex, LowerBackend, VCode}; use crate::trace; use core::fmt; use regalloc2::Function as _; +use core::fmt; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index cb75d3082fb0..9bdb74fb591a 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -18,6 +18,8 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; +use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because // these ABIs are very similar. diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index d8e6cd6a2083..baa42a265cb2 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -27,7 +27,7 @@ fn test_aarch64_binemit() { // // #!/bin/sh // tmp=`mktemp /tmp/XXXXXXXX.o` - // aarch64-linux-gnu-as /dev/stdin -o $tmp + // aarch64-linux-gnu-as /dev/corein -o $tmp // aarch64-linux-gnu-objdump -d $tmp // rm -f $tmp // diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index ead759b93028..e29302008ea5 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -15,6 +15,8 @@ use alloc::vec::Vec; use core::fmt::Write; use core::slice; use smallvec::{SmallVec, smallvec}; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub(crate) mod regs; pub(crate) use self::regs::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 3e82af2a9c8e..31800f10dafb 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -35,6 +35,8 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::u32; use regalloc2::PReg; +use alloc::boxed::Box; +use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxCallIndInfo = Box>; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index dafb6364f38d..ca1939acbd58 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -17,6 +17,7 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Aarch64Architecture, Architecture, OperatingSystem, Triple}; // New backend: diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 07a537b94127..db9b47ab6523 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,6 +15,8 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; +use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). pub(crate) type PulleyCallee

= Callee>; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index e97e3303ef99..440699490b8e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -6,6 +6,7 @@ use crate::machinst::abi::StackAMode; use core::fmt; use pulley_interpreter::encode; use pulley_interpreter::regs::Reg as _; +use core::fmt; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 0b781e467a08..1c0b736c15f3 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -22,6 +22,7 @@ use alloc::vec::Vec; use core::fmt::Debug; use core::marker::PhantomData; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; pub use settings::Flags as PulleyFlags; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index d1d12621dd5c..74e1916e4167 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -22,6 +22,8 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; +use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). pub(crate) type Riscv64Callee = Callee; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 2addfd65b63a..74f89c823b09 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -19,6 +19,9 @@ use alloc::vec::Vec; use core::fmt::Write; use regalloc2::RegClass; use smallvec::{SmallVec, smallvec}; +use alloc::boxed::Box; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index a2a7d0c196e6..e0ef1971bdf3 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -24,6 +24,8 @@ use crate::{ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::PReg; +use alloc::boxed::Box; +use alloc::vec::Vec; use wasmtime_math::{f32_cvt_to_int_bounds, f64_cvt_to_int_bounds}; type BoxCallInfo = Box>; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 5affb19a8a65..5034f6589b8a 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -18,6 +18,7 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; mod abi; pub(crate) mod inst; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 8c566ff24756..055371ee9c93 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -149,6 +149,8 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; +use alloc::borrow::ToOwned; +use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index aa6f9e6b19c9..569c16ac5c4d 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -12039,7 +12039,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102000", - "std %f1, 0(%r2)", + "core %f1, 0(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12054,7 +12054,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102FFF", - "std %f1, 4095(%r2)", + "core %f1, 4095(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12069,7 +12069,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1020008067", - "stdy %f1, -524288(%r2)", + "corey %f1, -524288(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12084,7 +12084,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED102FFF7F67", - "stdy %f1, 524287(%r2)", + "corey %f1, 524287(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12129,7 +12129,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123000", - "std %f1, 0(%r2,%r3)", + "core %f1, 0(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12144,7 +12144,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123FFF", - "std %f1, 4095(%r2,%r3)", + "core %f1, 4095(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12159,7 +12159,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1230008067", - "stdy %f1, -524288(%r2,%r3)", + "corey %f1, -524288(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12174,7 +12174,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED123FFF7F67", - "stdy %f1, 524287(%r2,%r3)", + "corey %f1, 524287(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index e114d9b022b0..9559f34ac7f8 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,7 +1,6 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; -use crate::prelude::*; use alloc::string::String; /// An unsigned 12-bit immediate. diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index b61bb215c187..b22d051aae01 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -12,6 +12,8 @@ use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::Write; use smallvec::SmallVec; +use core::fmt::Write; +use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; pub mod imms; @@ -2969,7 +2971,7 @@ impl Inst { (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None), (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None), (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")), - (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")), + (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("core"), Some("corey")), (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None), (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None), (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None), diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index 561fabd9561e..b3115fd7229e 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -27,6 +27,9 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::cell::Cell; use regalloc2::PReg; +use alloc::boxed::Box; +use core::cell::Cell; +use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxReturnCallInfo = Box>; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index b3f7986b9e8b..83752285d8a5 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -17,6 +17,7 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; +use alloc::string::String; use target_lexicon::{Architecture, Triple}; // New backend: diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 2563083f917e..a0edee844d0a 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -14,6 +14,7 @@ use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use args::*; +use std::sync::OnceLock; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 1ac58c5f8872..35c22ca49b3c 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,9 +7,8 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use crate::prelude::*; -use alloc::string::String; use core::fmt; +use alloc::string::String; /// An extension trait for converting `Writable{Xmm,Gpr}` to `Writable`. pub trait ToWritableReg { diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 1bd8b0f6b28e..9e47ea081b56 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -2,7 +2,7 @@ //! //! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases. //! -//! to see stdout: cargo test -- --nocapture +//! to see coreout: cargo test -- --nocapture //! //! for this specific case, as of 24 Aug 2020: //! diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 783f33414cb2..e0fceb201cc7 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -9,6 +9,7 @@ use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; use regalloc2::{PReg, RegClass}; +use alloc::string::String; /// Define the types of registers Cranelift will use. #[derive(Clone, Debug)] diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index f6e0b02cb38a..f15bcca93a28 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -19,6 +19,8 @@ use core::fmt::{self, Write}; use core::slice; use cranelift_assembler_x64 as asm; use smallvec::{SmallVec, smallvec}; +use core::fmt::{self, Write}; +use alloc::string::{String, ToString}; pub mod args; mod emit; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 62a81a6dd722..493058bd8c6a 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -11,6 +11,7 @@ use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; use regalloc2::{PReg, RegClass, VReg}; +use alloc::string::String; // Constructors for Regs. diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 1474eac342a2..0c4b205433cb 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -111,6 +111,7 @@ use crate::{ir, isa}; use crate::{machinst::*, trace}; use alloc::boxed::Box; use core::marker::PhantomData; +use hashbrown::HashMap; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::smallvec; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index da95e541ff6b..b76f4a5d7d48 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -190,6 +190,11 @@ use core::ops::Range; use cranelift_control::ControlPlane; use cranelift_entity::{PrimaryMap, SecondaryMap, entity_impl}; use smallvec::SmallVec; +use core::cmp::Ordering; +use alloc::collections::BinaryHeap; +use core::mem; +use alloc::string::String; +use alloc::vec::Vec; #[cfg(feature = "enable-serde")] use serde::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 0dcc5170a97a..930f4aaa4b30 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -28,6 +28,7 @@ use alloc::vec::Vec; use core::fmt::Debug; use cranelift_control::ControlPlane; use smallvec::{SmallVec, smallvec}; +use core::fmt::Debug; use super::{VCodeBuildDirection, VRegAllocator}; @@ -39,7 +40,7 @@ pub type InstOutput = SmallVec<[ValueRegs; 2]>; /// any side-effecting op (for this purpose, loads are also considered /// side-effecting, to avoid subtle questions w.r.t. the memory model), and /// furthermore, it is guaranteed that for any two instructions A and B such -/// that color(A) == color(B), either A dominates B and B postdominates A, or +/// that color(A) == color(B), either A dominates B and B pocoreominates A, or /// vice-versa. (For now, in practice, only ops in the same basic block can ever /// have the same color, trivially providing the second condition.) Intuitively, /// this means that the ops of the same color must always execute "together", as @@ -1390,7 +1391,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { /// Instruction input/output queries. impl<'func, I: VCodeInst> Lower<'func, I> { - /// Get the instdata for a given IR instruction. + /// Get the incoreata for a given IR instruction. pub fn data(&self, ir_inst: Inst) -> &InstructionData { &self.f.dfg.insts[ir_inst] } diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index c327803d5fb3..61ebb9bc0800 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -60,6 +60,7 @@ use cranelift_control::ControlPlane; use cranelift_entity::PrimaryMap; use regalloc2::VReg; use smallvec::{SmallVec, smallvec}; +use alloc::string::String; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 97c467ce212f..09d299968c54 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -34,6 +34,7 @@ use regalloc2::{ use crate::HashMap; use crate::hash_map::Entry; + use core::cmp::Ordering; use core::fmt::{self, Write}; use core::mem::take; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index fc360913b1d9..4ec9728f1e35 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -18,6 +18,7 @@ use crate::trace; use core::marker::PhantomData; use cranelift_entity::packed_option::ReservedValue; use smallvec::{SmallVec, smallvec}; +use core::marker::PhantomData; pub type Unit = (); pub type ValueArray2 = [Value; 2]; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 64079b289d83..822d6e27ede0 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2131,9 +2131,9 @@ mod tests { None => panic!("Expected an error"), Some(&VerifierError { ref message, .. }) => { if !message.contains($msg) { - #[cfg(feature = "std")] + #[cfg(feature = "core")] panic!("'{}' did not contain the substring '{}'", message, $msg); - #[cfg(not(feature = "std"))] + #[cfg(not(feature = "core"))] panic!("error message did not contain the expected substring"); } } From 073a20cc8507951e833fd8c81068cea7bac5f725 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 17:58:06 +0100 Subject: [PATCH 37/61] Port assembler_x64 to no_std --- cranelift/assembler-x64/Cargo.toml | 1 + cranelift/assembler-x64/src/api.rs | 3 +-- cranelift/assembler-x64/src/custom.rs | 2 +- cranelift/assembler-x64/src/imm.rs | 4 +++- cranelift/assembler-x64/src/inst.rs | 1 + cranelift/assembler-x64/src/lib.rs | 4 +--- cranelift/assembler-x64/src/main.rs | 12 ++++++++++++ cranelift/assembler-x64/src/mem.rs | 3 +++ cranelift/assembler-x64/src/xmm.rs | 2 ++ 9 files changed, 25 insertions(+), 7 deletions(-) diff --git a/cranelift/assembler-x64/Cargo.toml b/cranelift/assembler-x64/Cargo.toml index ef0822d3113a..1a49192f219f 100644 --- a/cranelift/assembler-x64/Cargo.toml +++ b/cranelift/assembler-x64/Cargo.toml @@ -23,3 +23,4 @@ workspace = true [features] fuzz = ['dep:arbitrary', 'dep:capstone'] +core = [] diff --git a/cranelift/assembler-x64/src/api.rs b/cranelift/assembler-x64/src/api.rs index f861b7726822..f65cfc338045 100644 --- a/cranelift/assembler-x64/src/api.rs +++ b/cranelift/assembler-x64/src/api.rs @@ -3,11 +3,10 @@ use crate::gpr; use crate::xmm; use crate::{Amode, DeferredTarget, GprMem, XmmMem}; -use alloc::string::String; use alloc::vec::Vec; use core::fmt; use core::num::NonZeroU8; - +use alloc::string::String; /// Describe how an instruction is emitted into a code buffer. pub trait CodeSink { /// Add 1 byte to the code section. diff --git a/cranelift/assembler-x64/src/custom.rs b/cranelift/assembler-x64/src/custom.rs index 25c63e239cf4..c2b70fecbc24 100644 --- a/cranelift/assembler-x64/src/custom.rs +++ b/cranelift/assembler-x64/src/custom.rs @@ -191,8 +191,8 @@ pub mod mnemonic { pub mod display { use crate::inst; use crate::{Amode, Gpr, GprMem, Registers, Size}; - use alloc::string::ToString; use core::fmt; + use alloc::string::ToString; pub fn callq_d(f: &mut fmt::Formatter, inst: &inst::callq_d) -> fmt::Result { let inst::callq_d { imm32 } = inst; diff --git a/cranelift/assembler-x64/src/imm.rs b/cranelift/assembler-x64/src/imm.rs index f350952dd23f..0c129cd65d45 100644 --- a/cranelift/assembler-x64/src/imm.rs +++ b/cranelift/assembler-x64/src/imm.rs @@ -1,9 +1,11 @@ //! Immediate operands to instructions. use crate::api::CodeSink; -use alloc::{format, string::String}; use core::fmt; +#[cfg(feature = "core")] +use alloc::{format, string::String}; + /// This helper function prints the unsigned hexadecimal representation of the /// immediate value: e.g., this prints `$0xfe` to represent both the signed `-2` /// and the unsigned `254`. diff --git a/cranelift/assembler-x64/src/inst.rs b/cranelift/assembler-x64/src/inst.rs index c9073401b040..e4f23849cd12 100644 --- a/cranelift/assembler-x64/src/inst.rs +++ b/cranelift/assembler-x64/src/inst.rs @@ -16,6 +16,7 @@ use crate::xmm::{self, Xmm}; use alloc::string::ToString; + // Include code generated by the `meta` crate. include!(concat!(env!("OUT_DIR"), "/assembler.rs")); diff --git a/cranelift/assembler-x64/src/lib.rs b/cranelift/assembler-x64/src/lib.rs index bf781a50de44..d28e102ffeb7 100644 --- a/cranelift/assembler-x64/src/lib.rs +++ b/cranelift/assembler-x64/src/lib.rs @@ -41,10 +41,8 @@ non_camel_case_types, reason = "all of the generated struct names use snake case" )] -#![no_std] +#![cfg_attr(feature = "core", no_std)] extern crate alloc; -#[cfg(any(test, feature = "fuzz"))] -extern crate std; mod api; mod custom; diff --git a/cranelift/assembler-x64/src/main.rs b/cranelift/assembler-x64/src/main.rs index 31ae7a7d55c5..4361d85624f9 100644 --- a/cranelift/assembler-x64/src/main.rs +++ b/cranelift/assembler-x64/src/main.rs @@ -1,7 +1,19 @@ //! Print the path to the generated code. +#![cfg_attr(feature = "core", no_std)] + +#[cfg(not(feature = "core"))] fn main() { let paths: Vec = include!(concat!(env!("OUT_DIR"), "/generated-files.rs")); for path in paths { println!("{}", path.display()); } } + +#[cfg(feature = "core")] +fn main() {} + +#[cfg(feature = "core")] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} \ No newline at end of file diff --git a/cranelift/assembler-x64/src/mem.rs b/cranelift/assembler-x64/src/mem.rs index 8235f9b5bfa9..3bfc88066009 100644 --- a/cranelift/assembler-x64/src/mem.rs +++ b/cranelift/assembler-x64/src/mem.rs @@ -6,6 +6,9 @@ use crate::api::{AsReg, CodeSink, Constant, KnownOffset, Label, TrapCode}; use crate::gpr::{self, NonRspGpr, Size}; use crate::rex::{Disp, RexPrefix, encode_modrm, encode_sib}; +#[cfg(feature = "core")] +use alloc::string::{String, ToString}; + /// x64 memory addressing modes. #[derive(Copy, Clone, Debug, PartialEq)] #[cfg_attr(any(test, feature = "fuzz"), derive(arbitrary::Arbitrary))] diff --git a/cranelift/assembler-x64/src/xmm.rs b/cranelift/assembler-x64/src/xmm.rs index d016e270b8e9..636c887afbc7 100644 --- a/cranelift/assembler-x64/src/xmm.rs +++ b/cranelift/assembler-x64/src/xmm.rs @@ -2,7 +2,9 @@ use crate::{AsReg, CodeSink, rex::encode_modrm}; +#[cfg(feature = "core")] use alloc::string::String; +//use core::convert::{AsMut, AsRef, From}; /// An x64 SSE register (e.g., `%xmm0`). #[derive(Clone, Copy, Debug)] From 40a81e6aaf1d2e0cee811ae535cc8273bbb647d8 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 18:26:16 +0100 Subject: [PATCH 38/61] before adding prelude to each file --- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/prelude.rs | 6 ++++-- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index e84ea6ae1e30..6220a20e9068 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -72,7 +72,7 @@ std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # deprecated (we (i) always use hashbrown, and (ii) don't support a # no_std build anymore). The feature remains for backward # compatibility as a no-op. -core = [] +core = ["cranelift-assembler-x64/core"] # Enable the `to_capstone` method on TargetIsa, for constructing a Capstone # context, and the `disassemble` method on `MachBufferFinalized`. diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 15af5a5ec20f..ba417c08429f 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1,3 +1,4 @@ + //! Immediate operands for Cranelift instructions //! //! This module defines the types of immediate operands that can appear on Cranelift instructions. diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index c9ea050fb28a..a2e47590f4d3 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -16,6 +16,7 @@ pub mod winarm64; #[cfg(feature = "unwind")] /// CFA-based unwind information used on SystemV. +#[cfg(feature = "unwind")] pub type CfaUnwindInfo = systemv::UnwindInfo; /// Expected unwind info type. diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index 6a3c99912572..b2d13852bc08 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,2 +1,4 @@ -pub use alloc::format; -pub use alloc::vec; +use alloc::format; +use alloc::string::{String, ToString}; +use alloc::vec::Vec; +use alloc::vec; From 8ebb4ef7fed49a408076c4fda5eb43e7d2a6ad14 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 18:42:45 +0100 Subject: [PATCH 39/61] Most of the files now work with no_std --- cranelift/codegen/src/alias_analysis.rs | 1 + cranelift/codegen/src/binemit/mod.rs | 1 + cranelift/codegen/src/cfg_printer.rs | 1 + cranelift/codegen/src/constant_hash.rs | 1 + cranelift/codegen/src/context.rs | 1 + cranelift/codegen/src/ctxhash.rs | 1 + cranelift/codegen/src/cursor.rs | 1 + cranelift/codegen/src/data_value.rs | 1 + cranelift/codegen/src/dbg.rs | 1 + cranelift/codegen/src/dominator_tree.rs | 1 + cranelift/codegen/src/dominator_tree/simple.rs | 1 + cranelift/codegen/src/egraph/cost.rs | 1 + cranelift/codegen/src/egraph/elaborate.rs | 1 + cranelift/codegen/src/egraph/mod.rs | 1 + cranelift/codegen/src/flowgraph.rs | 1 + cranelift/codegen/src/incremental_cache.rs | 1 + cranelift/codegen/src/inline.rs | 1 + cranelift/codegen/src/inst_predicates.rs | 1 + cranelift/codegen/src/ir/atomic_rmw_op.rs | 1 + cranelift/codegen/src/ir/builder.rs | 1 + cranelift/codegen/src/ir/condcodes.rs | 1 + cranelift/codegen/src/ir/constant.rs | 1 + cranelift/codegen/src/ir/debug_tags.rs | 1 + cranelift/codegen/src/ir/dfg.rs | 1 + cranelift/codegen/src/ir/dynamic_type.rs | 1 + cranelift/codegen/src/ir/entities.rs | 1 + cranelift/codegen/src/ir/exception_table.rs | 1 + cranelift/codegen/src/ir/extfunc.rs | 1 + cranelift/codegen/src/ir/extname.rs | 1 + cranelift/codegen/src/ir/function.rs | 1 + cranelift/codegen/src/ir/globalvalue.rs | 1 + cranelift/codegen/src/ir/immediates.rs | 1 + cranelift/codegen/src/ir/instructions.rs | 1 + cranelift/codegen/src/ir/jumptable.rs | 1 + cranelift/codegen/src/ir/known_symbol.rs | 1 + cranelift/codegen/src/ir/layout.rs | 1 + cranelift/codegen/src/ir/libcall.rs | 1 + cranelift/codegen/src/ir/memflags.rs | 1 + cranelift/codegen/src/ir/memtype.rs | 1 + cranelift/codegen/src/ir/mod.rs | 1 + cranelift/codegen/src/ir/pcc.rs | 1 + cranelift/codegen/src/ir/progpoint.rs | 1 + cranelift/codegen/src/ir/sourceloc.rs | 1 + cranelift/codegen/src/ir/stackslot.rs | 1 + cranelift/codegen/src/ir/trapcode.rs | 1 + cranelift/codegen/src/ir/types.rs | 1 + cranelift/codegen/src/ir/user_stack_maps.rs | 1 + cranelift/codegen/src/isa/aarch64/abi.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/args.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/emit.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 + cranelift/codegen/src/isa/aarch64/inst/unwind.rs | 1 + .../codegen/src/isa/aarch64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/aarch64/lower.rs | 1 + cranelift/codegen/src/isa/aarch64/lower/isle.rs | 1 + .../src/isa/aarch64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/aarch64/mod.rs | 1 + cranelift/codegen/src/isa/aarch64/pcc.rs | 1 + cranelift/codegen/src/isa/aarch64/settings.rs | 1 + cranelift/codegen/src/isa/call_conv.rs | 1 + cranelift/codegen/src/isa/mod.rs | 1 + cranelift/codegen/src/isa/pulley32.rs | 1 + cranelift/codegen/src/isa/pulley64.rs | 1 + cranelift/codegen/src/isa/pulley_shared/abi.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/args.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/emit.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/inst/regs.rs | 1 + cranelift/codegen/src/isa/pulley_shared/lower.rs | 1 + .../codegen/src/isa/pulley_shared/lower/isle.rs | 1 + .../isa/pulley_shared/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/pulley_shared/mod.rs | 1 + cranelift/codegen/src/isa/pulley_shared/settings.rs | 1 + cranelift/codegen/src/isa/riscv64/abi.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/args.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/emit.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/encode.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/imms.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/regs.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/unwind.rs | 1 + .../codegen/src/isa/riscv64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 + cranelift/codegen/src/isa/riscv64/lower.rs | 1 + cranelift/codegen/src/isa/riscv64/lower/isle.rs | 1 + .../src/isa/riscv64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/riscv64/mod.rs | 1 + cranelift/codegen/src/isa/riscv64/settings.rs | 1 + cranelift/codegen/src/isa/s390x/abi.rs | 1 + cranelift/codegen/src/isa/s390x/inst/args.rs | 1 + cranelift/codegen/src/isa/s390x/inst/emit.rs | 1 + cranelift/codegen/src/isa/s390x/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 + cranelift/codegen/src/isa/s390x/inst/mod.rs | 1 + cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 + cranelift/codegen/src/isa/s390x/inst/unwind.rs | 1 + .../codegen/src/isa/s390x/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/s390x/lower.rs | 1 + cranelift/codegen/src/isa/s390x/lower/isle.rs | 1 + .../src/isa/s390x/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/s390x/mod.rs | 1 + cranelift/codegen/src/isa/s390x/settings.rs | 1 + cranelift/codegen/src/isa/unwind.rs | 1 + cranelift/codegen/src/isa/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/unwind/winarm64.rs | 1 + cranelift/codegen/src/isa/unwind/winx64.rs | 1 + cranelift/codegen/src/isa/winch.rs | 1 + cranelift/codegen/src/isa/x64/abi.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit_state.rs | 1 + cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 1 + cranelift/codegen/src/isa/x64/inst/external.rs | 1 + cranelift/codegen/src/isa/x64/inst/mod.rs | 1 + cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + cranelift/codegen/src/isa/x64/inst/stack_switch.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs | 1 + cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs | 1 + cranelift/codegen/src/isa/x64/lower.rs | 1 + cranelift/codegen/src/isa/x64/lower/isle.rs | 1 + .../codegen/src/isa/x64/lower/isle/generated_code.rs | 1 + cranelift/codegen/src/isa/x64/mod.rs | 1 + cranelift/codegen/src/isa/x64/pcc.rs | 1 + cranelift/codegen/src/isa/x64/settings.rs | 1 + cranelift/codegen/src/isle_prelude.rs | 1 + cranelift/codegen/src/legalizer/branch_to_trap.rs | 1 + cranelift/codegen/src/legalizer/globalvalue.rs | 1 + cranelift/codegen/src/legalizer/mod.rs | 1 + cranelift/codegen/src/lib.rs | 3 +++ cranelift/codegen/src/loop_analysis.rs | 1 + cranelift/codegen/src/machinst/abi.rs | 1 + cranelift/codegen/src/machinst/blockorder.rs | 1 + cranelift/codegen/src/machinst/buffer.rs | 1 + cranelift/codegen/src/machinst/compile.rs | 1 + cranelift/codegen/src/machinst/helpers.rs | 1 + cranelift/codegen/src/machinst/inst_common.rs | 1 + cranelift/codegen/src/machinst/isle.rs | 1 + cranelift/codegen/src/machinst/lower.rs | 1 + cranelift/codegen/src/machinst/mod.rs | 1 + cranelift/codegen/src/machinst/pcc.rs | 1 + cranelift/codegen/src/machinst/reg.rs | 1 + cranelift/codegen/src/machinst/valueregs.rs | 1 + cranelift/codegen/src/machinst/vcode.rs | 1 + cranelift/codegen/src/nan_canonicalization.rs | 1 + cranelift/codegen/src/opts.rs | 1 + cranelift/codegen/src/opts/div_const.rs | 1 + cranelift/codegen/src/opts/generated_code.rs | 1 + cranelift/codegen/src/prelude.rs | 12 ++++++++---- cranelift/codegen/src/print_errors.rs | 1 + cranelift/codegen/src/ranges.rs | 1 + cranelift/codegen/src/remove_constant_phis.rs | 1 + cranelift/codegen/src/result.rs | 1 + cranelift/codegen/src/scoped_hash_map.rs | 1 + cranelift/codegen/src/settings.rs | 1 + cranelift/codegen/src/souper_harvest.rs | 1 + cranelift/codegen/src/take_and_replace.rs | 1 + cranelift/codegen/src/timing.rs | 1 + cranelift/codegen/src/traversals.rs | 1 + cranelift/codegen/src/unreachable_code.rs | 1 + cranelift/codegen/src/value_label.rs | 1 + cranelift/codegen/src/verifier/mod.rs | 1 + cranelift/codegen/src/write.rs | 1 + 167 files changed, 176 insertions(+), 4 deletions(-) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index ba141d235001..f4c3fc30adad 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -401,3 +401,4 @@ fn get_ext_opcode(op: Opcode) -> Option { _ => Some(op), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs index cd34c0b3ff13..022eb7db5fca 100644 --- a/cranelift/codegen/src/binemit/mod.rs +++ b/cranelift/codegen/src/binemit/mod.rs @@ -190,3 +190,4 @@ pub struct CodeInfo { /// Number of bytes in total. pub total_size: CodeOffset, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/cfg_printer.rs b/cranelift/codegen/src/cfg_printer.rs index ef71b63ca712..8c07f0ac478b 100644 --- a/cranelift/codegen/src/cfg_printer.rs +++ b/cranelift/codegen/src/cfg_printer.rs @@ -81,3 +81,4 @@ impl<'a> Display for CFGPrinter<'a> { self.write(f) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/constant_hash.rs b/cranelift/codegen/src/constant_hash.rs index 1de2a2edb43e..be018675b5e2 100644 --- a/cranelift/codegen/src/constant_hash.rs +++ b/cranelift/codegen/src/constant_hash.rs @@ -60,3 +60,4 @@ pub fn probe + ?Sized>( idx += step; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index c37de05497bc..46267cb446d2 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -391,3 +391,4 @@ impl Context { self.verify_if(fisa) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 7148046ae9c1..7e6b852907f3 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -223,3 +223,4 @@ mod test { assert_eq!(*map.get(&k0, &ctx).unwrap(), 84); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/cursor.rs b/cranelift/codegen/src/cursor.rs index ae7b0ea874ad..b1bec22fa159 100644 --- a/cranelift/codegen/src/cursor.rs +++ b/cranelift/codegen/src/cursor.rs @@ -687,3 +687,4 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> { &mut self.func.dfg } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index a2e69a724e1b..26a66d53694e 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -420,3 +420,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dbg.rs b/cranelift/codegen/src/dbg.rs index 4796f3967b91..8a0da7a24aed 100644 --- a/cranelift/codegen/src/dbg.rs +++ b/cranelift/codegen/src/dbg.rs @@ -26,3 +26,4 @@ where } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 29e65a9ae806..b730b9a6107e 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -772,3 +772,4 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree/simple.rs b/cranelift/codegen/src/dominator_tree/simple.rs index 853158bc80b1..9abc47e4df95 100644 --- a/cranelift/codegen/src/dominator_tree/simple.rs +++ b/cranelift/codegen/src/dominator_tree/simple.rs @@ -582,3 +582,4 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index 062196964c96..f2f2048497b9 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -236,3 +236,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index b717fc32df4e..1ae2d260284f 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -866,3 +866,4 @@ impl<'a> Elaborator<'a> { self.stats.elaborate_func_post_insts += self.func.dfg.num_insts() as u64; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/mod.rs b/cranelift/codegen/src/egraph/mod.rs index 938f632bf892..0e0ec49278f9 100644 --- a/cranelift/codegen/src/egraph/mod.rs +++ b/cranelift/codegen/src/egraph/mod.rs @@ -1111,3 +1111,4 @@ pub(crate) struct Stats { pub(crate) elaborate_func_post_insts: u64, pub(crate) eclass_size_limit: u64, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/flowgraph.rs b/cranelift/codegen/src/flowgraph.rs index 6478dfddbf90..9358c851b4e3 100644 --- a/cranelift/codegen/src/flowgraph.rs +++ b/cranelift/codegen/src/flowgraph.rs @@ -347,3 +347,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index a597d18869ce..973cca13ece1 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -239,3 +239,4 @@ pub fn try_finish_recompile(func: &Function, bytes: &[u8]) -> Result Err(RecompileError::Deserialize(err)), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/inline.rs b/cranelift/codegen/src/inline.rs index ac150c598980..6e6756871545 100644 --- a/cranelift/codegen/src/inline.rs +++ b/cranelift/codegen/src/inline.rs @@ -1584,3 +1584,4 @@ fn create_constants(allocs: &mut InliningAllocs, func: &mut ir::Function, callee allocs.constants[*callee_constant] = Some(inlined_constant).into(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs index 7b42e1728663..91cb01ca7cf3 100644 --- a/cranelift/codegen/src/inst_predicates.rs +++ b/cranelift/codegen/src/inst_predicates.rs @@ -215,3 +215,4 @@ pub(crate) fn visit_block_succs( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/atomic_rmw_op.rs b/cranelift/codegen/src/ir/atomic_rmw_op.rs index 0317fc00d2c1..ea6a16b7d969 100644 --- a/cranelift/codegen/src/ir/atomic_rmw_op.rs +++ b/cranelift/codegen/src/ir/atomic_rmw_op.rs @@ -102,3 +102,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/builder.rs b/cranelift/codegen/src/ir/builder.rs index 24d9beaee660..c36673bd79ee 100644 --- a/cranelift/codegen/src/ir/builder.rs +++ b/cranelift/codegen/src/ir/builder.rs @@ -280,3 +280,4 @@ mod tests { .Trap(Opcode::Return, I32, TrapCode::BAD_CONVERSION_TO_INTEGER); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index 009f95bf391c..454423f7a189 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -402,3 +402,4 @@ mod tests { assert_eq!("bogus".parse::(), Err(())); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index 67310cd9462f..5612510c8f33 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -485,3 +485,4 @@ mod tests { assert_eq!(Ieee128::try_from(&constant).unwrap().bits(), value.bits()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/debug_tags.rs b/cranelift/codegen/src/ir/debug_tags.rs index 39d137c2973b..d2ca049f6c53 100644 --- a/cranelift/codegen/src/ir/debug_tags.rs +++ b/cranelift/codegen/src/ir/debug_tags.rs @@ -139,3 +139,4 @@ impl core::fmt::Display for DebugTag { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dfg.rs b/cranelift/codegen/src/ir/dfg.rs index 3dd2ad4211c3..e48cdd42d990 100644 --- a/cranelift/codegen/src/ir/dfg.rs +++ b/cranelift/codegen/src/ir/dfg.rs @@ -1882,3 +1882,4 @@ mod tests { assert_eq!(v1, func.dfg.inst_args(call_inst_dup)[0]); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dynamic_type.rs b/cranelift/codegen/src/ir/dynamic_type.rs index 53027c196945..369bcc74eeba 100644 --- a/cranelift/codegen/src/ir/dynamic_type.rs +++ b/cranelift/codegen/src/ir/dynamic_type.rs @@ -52,3 +52,4 @@ pub fn dynamic_to_fixed(ty: Type) -> Type { _ => unreachable!("unhandled type: {}", ty), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/entities.rs b/cranelift/codegen/src/ir/entities.rs index cbb8f3097aff..a1ab10662d7d 100644 --- a/cranelift/codegen/src/ir/entities.rs +++ b/cranelift/codegen/src/ir/entities.rs @@ -562,3 +562,4 @@ mod tests { assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index f92ad688e565..08f1a7cb778e 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -288,3 +288,4 @@ impl<'a> Display for DisplayExceptionTable<'a> { Ok(()) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extfunc.rs b/cranelift/codegen/src/ir/extfunc.rs index ebfaf3a8ddaf..61880e27fc84 100644 --- a/cranelift/codegen/src/ir/extfunc.rs +++ b/cranelift/codegen/src/ir/extfunc.rs @@ -418,3 +418,4 @@ mod tests { assert_eq!(sig.to_string(), "(i32, i32x4) -> f32, i8 windows_fastcall"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index d28ebcb4e7b2..e80fb4cf34b4 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -336,3 +336,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/function.rs b/cranelift/codegen/src/ir/function.rs index 80926edcdf1c..296d0c9cf938 100644 --- a/cranelift/codegen/src/ir/function.rs +++ b/cranelift/codegen/src/ir/function.rs @@ -517,3 +517,4 @@ impl<'a> fmt::Debug for DisplayFunctionSpec<'a> { write_function_spec(fmt, self.0) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/globalvalue.rs b/cranelift/codegen/src/ir/globalvalue.rs index 89120c8b8364..8ea7372c7349 100644 --- a/cranelift/codegen/src/ir/globalvalue.rs +++ b/cranelift/codegen/src/ir/globalvalue.rs @@ -145,3 +145,4 @@ impl fmt::Display for GlobalValueData { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index ba417c08429f..35956406fb28 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1961,3 +1961,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 80c04e48e6fb..6a95b1ce9975 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -1538,3 +1538,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 5bdad87d941f..85d6d77b1a51 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -173,3 +173,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/known_symbol.rs b/cranelift/codegen/src/ir/known_symbol.rs index c3d17501a39b..6c594b7faff3 100644 --- a/cranelift/codegen/src/ir/known_symbol.rs +++ b/cranelift/codegen/src/ir/known_symbol.rs @@ -45,3 +45,4 @@ mod tests { assert_eq!("CoffTlsIndex".parse(), Ok(KnownSymbol::CoffTlsIndex)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/layout.rs b/cranelift/codegen/src/ir/layout.rs index 1284ab65676e..2a2d139018fe 100644 --- a/cranelift/codegen/src/ir/layout.rs +++ b/cranelift/codegen/src/ir/layout.rs @@ -1193,3 +1193,4 @@ mod tests { assert_eq!(layout.pp_cmp(i3, i2), Ordering::Greater) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/libcall.rs b/cranelift/codegen/src/ir/libcall.rs index 6b60dfd07d27..3cf1ebb2d7f2 100644 --- a/cranelift/codegen/src/ir/libcall.rs +++ b/cranelift/codegen/src/ir/libcall.rs @@ -230,3 +230,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memflags.rs b/cranelift/codegen/src/ir/memflags.rs index 45f32ce85fd2..726004dcd59f 100644 --- a/cranelift/codegen/src/ir/memflags.rs +++ b/cranelift/codegen/src/ir/memflags.rs @@ -485,3 +485,4 @@ mod tests { assert!(big.set_by_name("table").is_err()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index b7b0d7e2db1e..8501c9bb73a3 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -188,3 +188,4 @@ impl MemoryTypeData { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/mod.rs b/cranelift/codegen/src/ir/mod.rs index eca17e7badda..db671b366444 100644 --- a/cranelift/codegen/src/ir/mod.rs +++ b/cranelift/codegen/src/ir/mod.rs @@ -117,3 +117,4 @@ pub enum ValueLabelAssignments { value: Value, }, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index d1bf7ea62dba..f9062a1ddad6 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -1679,3 +1679,4 @@ pub fn check_vcode_facts( } Ok(()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/progpoint.rs b/cranelift/codegen/src/ir/progpoint.rs index 84d394276f67..dafcd16d7c5d 100644 --- a/cranelift/codegen/src/ir/progpoint.rs +++ b/cranelift/codegen/src/ir/progpoint.rs @@ -73,3 +73,4 @@ mod tests { assert_eq!(pp2.to_string(), "block3"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/sourceloc.rs b/cranelift/codegen/src/ir/sourceloc.rs index 6704574d0d09..38efbe2939aa 100644 --- a/cranelift/codegen/src/ir/sourceloc.rs +++ b/cranelift/codegen/src/ir/sourceloc.rs @@ -115,3 +115,4 @@ mod tests { assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 01bf2ff1a6ab..835a0ee3bafd 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -250,3 +250,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/trapcode.rs b/cranelift/codegen/src/ir/trapcode.rs index e3fbcfbb4a50..f990f312b94f 100644 --- a/cranelift/codegen/src/ir/trapcode.rs +++ b/cranelift/codegen/src/ir/trapcode.rs @@ -145,3 +145,4 @@ mod tests { assert_eq!("users".parse::(), Err(())); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs index bc7704cf0662..48e98fd352d2 100644 --- a/cranelift/codegen/src/ir/types.rs +++ b/cranelift/codegen/src/ir/types.rs @@ -622,3 +622,4 @@ mod tests { assert_eq!(Type::int_with_byte_size(evil), None); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs index 6ad9b697cd02..92aaa198effa 100644 --- a/cranelift/codegen/src/ir/user_stack_maps.rs +++ b/cranelift/codegen/src/ir/user_stack_maps.rs @@ -197,3 +197,4 @@ impl UserStackMap { }) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 9bdb74fb591a..ea9710976388 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -1632,3 +1632,4 @@ fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv { env } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index a382a5ef725a..d912aee4dd79 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -724,3 +724,4 @@ impl TestBitAndBranchKind { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 06e0eb017708..b5bb377591df 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -3685,3 +3685,4 @@ fn emit_return_call_common_sequence( sink.put4(key.enc_auti_hint()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index baa42a265cb2..fdca784dd038 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -7970,3 +7970,4 @@ fn test_cond_invert() { assert_eq!(cond.invert().invert(), cond); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index 09aa838b8e82..d72de5f39692 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -1241,3 +1241,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index e29302008ea5..1021ddc6b90c 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -3115,3 +3115,4 @@ mod tests { assert_eq!(expected, core::mem::size_of::()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index c9468f46e932..5f1086252fbd 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -280,3 +280,4 @@ pub fn pretty_print_vreg_vector(reg: Reg, size: VectorSize) -> String { pub fn pretty_print_vreg_element(reg: Reg, idx: usize, size: ScalarSize) -> String { show_vreg_element(reg, idx as u8, size) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs index 9378c46fa53b..25a095983c42 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs @@ -175,3 +175,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs index 6d51a380433f..99c9f2f95592 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.rs +++ b/cranelift/codegen/src/isa/aarch64/lower.rs @@ -143,3 +143,4 @@ impl LowerBackend for AArch64Backend { type FactFlowState = pcc::FactFlowState; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 31800f10dafb..6898f2852403 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -860,3 +860,4 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.backend.flags.is_pic() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 2e0f7bd77dda..3867a060b7f3 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -14,3 +14,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_aarch64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index ca1939acbd58..703a0240036a 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -280,3 +280,4 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs index e5ee1919803e..3b5e31d11c0e 100644 --- a/cranelift/codegen/src/isa/aarch64/pcc.rs +++ b/cranelift/codegen/src/isa/aarch64/pcc.rs @@ -568,3 +568,4 @@ fn check_store_addr( let _output_fact = ctx.store(&fact, ty, None)?; Ok(()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/settings.rs b/cranelift/codegen/src/isa/aarch64/settings.rs index 2cda69446ff3..21031399b5eb 100644 --- a/cranelift/codegen/src/isa/aarch64/settings.rs +++ b/cranelift/codegen/src/isa/aarch64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/arm64.rs`. include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/call_conv.rs b/cranelift/codegen/src/isa/call_conv.rs index a8f6ce50203e..65e6c514c830 100644 --- a/cranelift/codegen/src/isa/call_conv.rs +++ b/cranelift/codegen/src/isa/call_conv.rs @@ -153,3 +153,4 @@ impl str::FromStr for CallConv { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2bc2033983ef..2c31830e139a 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -499,3 +499,4 @@ impl Debug for &dyn TargetIsa { ) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley32.rs b/cranelift/codegen/src/isa/pulley32.rs index b337274660d0..e3467275472e 100644 --- a/cranelift/codegen/src/isa/pulley32.rs +++ b/cranelift/codegen/src/isa/pulley32.rs @@ -11,3 +11,4 @@ impl PulleyTargetKind for Pulley32 { PointerWidth::PointerWidth32 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley64.rs b/cranelift/codegen/src/isa/pulley64.rs index 31b1d08a04b2..234840c45eb5 100644 --- a/cranelift/codegen/src/isa/pulley64.rs +++ b/cranelift/codegen/src/isa/pulley64.rs @@ -11,3 +11,4 @@ impl PulleyTargetKind for Pulley64 { PointerWidth::PointerWidth64 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index db9b47ab6523..44b8d350b971 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -985,3 +985,4 @@ fn create_reg_environment() -> MachineEnv { scratch_by_class: [None, None, None], } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index 440699490b8e..3520abec8d24 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -780,3 +780,4 @@ impl fmt::Display for AddrG32Bne { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs index 74082b4260c3..25614218b03b 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs @@ -707,3 +707,4 @@ fn patch_pc_rel_offset

( assert_eq!(*chunk, [0, 0, 0, 0]); *chunk = (end - start - 4).to_le_bytes(); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index d76705a7fb9f..497ba5e2031e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -952,3 +952,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs index 90f7d36e104b..069050e7cd55 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs @@ -162,3 +162,4 @@ define_registers! { v_reg(30) => v30, writable_v30; v_reg(31) => v31, writable_v31; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.rs b/cranelift/codegen/src/isa/pulley_shared/lower.rs index 8dd5a0cea50c..b436d1d3e46e 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower.rs @@ -34,3 +34,4 @@ where type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs index d72b6a023789..baa93a5eb1bc 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs @@ -327,3 +327,4 @@ where let mut isle_ctx = PulleyIsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs index 45dd7050dc3c..6b0853db8f25 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_pulley_shared.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 1c0b736c15f3..8bcaa2eae62a 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -313,3 +313,4 @@ impl PulleyFlags { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/settings.rs b/cranelift/codegen/src/isa/pulley_shared/settings.rs index 5d4fd19ed116..d611e3a6f2a5 100644 --- a/cranelift/codegen/src/isa/pulley_shared/settings.rs +++ b/cranelift/codegen/src/isa/pulley_shared/settings.rs @@ -14,3 +14,4 @@ use core::fmt; include!(concat!(env!("OUT_DIR"), "/settings-pulley.rs")); impl IsaFlags for Flags {} +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index 74e1916e4167..8b217e4ffd2f 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -1056,3 +1056,4 @@ impl Riscv64MachineDeps { insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index 918a4854b3a3..d710f4348e46 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -1946,3 +1946,4 @@ impl ZcbMemOp { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 5e631c3af1d3..714271546539 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -2885,3 +2885,4 @@ fn return_call_emit_impl( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 3b0cf59b633f..09880464c68e 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -2283,3 +2283,4 @@ fn riscv64_worst_case_instruction_size() { println!("calculate max size is {} , inst is {:?}", max.0, max.1); assert!(max.0 <= Inst::worst_case_size()); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/encode.rs b/cranelift/codegen/src/isa/riscv64/inst/encode.rs index 048fc2af05b5..b167f319ccfe 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs @@ -718,3 +718,4 @@ pub fn encode_fp_rrrr( funct7, ) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 92a8ceb60b83..5e9f0faeee45 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -371,3 +371,4 @@ mod test { assert!(Inst::imm_min() == i32::MIN as i64 - 2048); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 74f89c823b09..0ba4fcc684cc 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -1944,3 +1944,4 @@ mod test { assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/regs.rs b/cranelift/codegen/src/isa/riscv64/inst/regs.rs index 76493732bfe1..d1e9fa7cd00f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/regs.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/regs.rs @@ -151,3 +151,4 @@ pub const fn pf_reg(enc: usize) -> PReg { pub const fn pv_reg(enc: usize) -> PReg { PReg::new(enc, RegClass::Vector) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs index 0b2ef040b19c..0edc32ba221f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs @@ -171,3 +171,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 0c8c49f8544b..add4cc872f16 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -1149,3 +1149,4 @@ pub trait VecInstOverlapInfo { self.forbids_src_dst_overlaps() || (mask.is_enabled() && self.forbids_mask_dst_overlaps()) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower.rs b/cranelift/codegen/src/isa/riscv64/lower.rs index 117778f820b3..8de92855b2f8 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.rs +++ b/cranelift/codegen/src/isa/riscv64/lower.rs @@ -33,3 +33,4 @@ impl LowerBackend for Riscv64Backend { type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index e0ef1971bdf3..6a8aed5eb907 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -751,3 +751,4 @@ pub(crate) fn lower_branch( let mut isle_ctx = RV64IsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs index ad8466108a3b..9fb78bfb80ca 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_riscv64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 5034f6589b8a..ad9f3854a7bd 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -294,3 +294,4 @@ fn isa_constructor( let backend = Riscv64Backend::new_with_flags(triple, shared_flags, isa_flags); Ok(backend.wrapped()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/settings.rs b/cranelift/codegen/src/isa/riscv64/settings.rs index c896dd5fe911..f4ca3fb3a88a 100644 --- a/cranelift/codegen/src/isa/riscv64/settings.rs +++ b/cranelift/codegen/src/isa/riscv64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/riscv64/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-riscv64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 055371ee9c93..09d19fe54462 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -1623,3 +1623,4 @@ fn tail_create_machine_env() -> MachineEnv { scratch_by_class: [None, None, None], } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/args.rs b/cranelift/codegen/src/isa/s390x/inst/args.rs index 33e790673b61..5e114104b320 100644 --- a/cranelift/codegen/src/isa/s390x/inst/args.rs +++ b/cranelift/codegen/src/isa/s390x/inst/args.rs @@ -269,3 +269,4 @@ impl PrettyPrint for Cond { s.to_string() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index 5baef0fede8a..e218fe55454a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3559,3 +3559,4 @@ impl Inst { state.clear_post_insn(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index 569c16ac5c4d..aa4ab565eaef 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -13496,3 +13496,4 @@ fn test_s390x_binemit() { assert_eq!(expected_encoding, actual_encoding); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 9559f34ac7f8..edb66ba08196 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -200,3 +200,4 @@ impl PrettyPrint for UImm32Shifted { format!("{}", self.bits) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index b22d051aae01..1132b39b7b8a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -3553,3 +3553,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index 8b0205569b80..438069a12c24 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -185,3 +185,4 @@ pub fn pretty_print_regpair_mod_lo(rd: WritableRegPair, ri: Reg) -> String { pub fn pretty_print_fpr(reg: Reg) -> (String, Option) { (show_reg(reg), maybe_show_fpr(reg)) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind.rs b/cranelift/codegen/src/isa/s390x/inst/unwind.rs index 1e2bb904db74..cb1a9ad16eb4 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind.rs @@ -1,2 +1,3 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs index 6ae2c7e262d9..a37ca84767d9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs @@ -216,3 +216,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index 9af0b96147e5..c111eee9c915 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -28,3 +28,4 @@ impl LowerBackend for S390xBackend { type FactFlowState = (); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index b3115fd7229e..56176476ecb8 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -862,3 +862,4 @@ fn condcode_is_signed(cc: IntCC) -> bool { IntCC::UnsignedLessThan => false, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index a6daad546b62..c32fdefdc440 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -13,3 +13,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_s390x.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 83752285d8a5..c2905dcdfde2 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -238,3 +238,4 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/settings.rs b/cranelift/codegen/src/isa/s390x/settings.rs index 5bf89030f19d..16a717f9e7c7 100644 --- a/cranelift/codegen/src/isa/s390x/settings.rs +++ b/cranelift/codegen/src/isa/s390x/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/s390x/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index a2e47590f4d3..08cb2c7cbb14 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -250,3 +250,4 @@ impl<'a> Writer<'a> { self.offset += 4; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index 5989e0b2a12b..0fb19d0408c7 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -286,3 +286,4 @@ impl UnwindInfo { fde } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winarm64.rs b/cranelift/codegen/src/isa/unwind/winarm64.rs index 3d3cdd8fcf48..803867af2a85 100644 --- a/cranelift/codegen/src/isa/unwind/winarm64.rs +++ b/cranelift/codegen/src/isa/unwind/winarm64.rs @@ -315,3 +315,4 @@ pub(crate) fn create_unwind_info_from_insts( Ok(UnwindInfo { unwind_codes }) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winx64.rs b/cranelift/codegen/src/isa/unwind/winx64.rs index 38cb46b83b55..e352dc6351df 100644 --- a/cranelift/codegen/src/isa/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/unwind/winx64.rs @@ -310,3 +310,4 @@ fn ensure_unwind_offset(offset: u32) -> CodegenResult { } Ok(offset as u8) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index df8fdce35223..8e9bbf0efdc3 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -20,3 +20,4 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index a0edee844d0a..4d96e2056808 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -1345,3 +1345,4 @@ fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv { env } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 35c22ca49b3c..c5e6a117ec04 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -1061,3 +1061,4 @@ impl OperandSize { self.to_bytes() * 8 } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 363f9194bd6f..2374d6e63b58 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -2193,3 +2193,4 @@ fn emit_lea( _ => lea(*dst.as_ref(), addr, sink), } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_state.rs b/cranelift/codegen/src/isa/x64/inst/emit_state.rs index 426a17a2803b..98ffebf3f3be 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_state.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_state.rs @@ -53,3 +53,4 @@ impl EmitState { self.user_stack_map = None; } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 9e47ea081b56..7d9e7a6e7eba 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -383,3 +383,4 @@ fn test_x64_emit() { assert_eq!(expected_encoding, actual_encoding, "{expected_printing}"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index e0fceb201cc7..3a3210e2cc2b 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -564,3 +564,4 @@ mod tests { assert_eq!(pair.to_string(None), "(%v500 <- %v400)"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index f15bcca93a28..33d35ddd29ad 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -1681,3 +1681,4 @@ impl MachInstLabelUse for LabelUse { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 493058bd8c6a..fa68a12cc944 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -176,3 +176,4 @@ pub fn pretty_print_reg(reg: Reg, size: u8) -> String { name } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs index 4c9400df41bf..d32c59dd9fee 100644 --- a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs +++ b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs @@ -47,3 +47,4 @@ pub fn control_context_layout() -> ControlContextLayout { pub fn payload_register() -> Reg { regs::rdi() } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind.rs b/cranelift/codegen/src/isa/x64/inst/unwind.rs index cb86c3b7ccd5..56289f082012 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind.rs @@ -3,3 +3,4 @@ pub(crate) mod systemv; #[cfg(feature = "unwind")] pub(crate) mod winx64; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs index 3f46843ab4f4..ecbe379cd7da 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs @@ -202,3 +202,4 @@ mod tests { func } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs index f848a5baf76f..f6d80f5e531f 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs @@ -14,3 +14,4 @@ impl crate::isa::unwind::winx64::RegisterMapper for RegisterMapper { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index a000f8ece143..210f1d964a71 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -351,3 +351,4 @@ impl LowerBackend for X64Backend { type FactFlowState = pcc::FactFlowState; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 57bfa06ee7fd..3917b4203ca5 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -1249,3 +1249,4 @@ const I8X16_USHR_MASKS: [u8; 128] = [ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ]; +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index c48996ec46d6..1bc434f23b5a 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -14,3 +14,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_x64.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index b4cc5467536a..9cd8cc6085c4 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -268,3 +268,4 @@ fn isa_constructor( let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags)?; Ok(backend.wrapped()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs index 09b356d69958..b82eb7d5014e 100644 --- a/cranelift/codegen/src/isa/x64/pcc.rs +++ b/cranelift/codegen/src/isa/x64/pcc.rs @@ -324,3 +324,4 @@ fn compute_addr(ctx: &FactContext, vcode: &VCode, amode: &Amode, bits: u16 Amode::RipRelative { .. } => None, } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/settings.rs b/cranelift/codegen/src/isa/x64/settings.rs index 12420311b34c..83faa5585cb6 100644 --- a/cranelift/codegen/src/isa/x64/settings.rs +++ b/cranelift/codegen/src/isa/x64/settings.rs @@ -7,3 +7,4 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/x86/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-x86.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index a2b58b15431d..7e974bff3f56 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -941,3 +941,4 @@ macro_rules! isle_common_prelude_methods { } }; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/branch_to_trap.rs b/cranelift/codegen/src/legalizer/branch_to_trap.rs index 1cbb0e657ffb..330c47abc6e7 100644 --- a/cranelift/codegen/src/legalizer/branch_to_trap.rs +++ b/cranelift/codegen/src/legalizer/branch_to_trap.rs @@ -96,3 +96,4 @@ impl BranchToTrap { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index 45444d161934..85b7dee06108 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -176,3 +176,4 @@ fn symbol( WalkCommand::Continue } +use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs index 768afd306752..44dcd1ad4dcb 100644 --- a/cranelift/codegen/src/legalizer/mod.rs +++ b/cranelift/codegen/src/legalizer/mod.rs @@ -392,3 +392,4 @@ fn expand_stack_load( WalkCommand::Continue } +use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 2ba4a4db5a4c..f167528ad3fc 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -50,6 +50,8 @@ mod prelude; #[macro_use] mod machinst; +mod prelude; + pub mod binemit; pub mod cfg_printer; pub mod cursor; @@ -129,3 +131,4 @@ macro_rules! trace_log_enabled { } include!(concat!(env!("OUT_DIR"), "/version.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index 5d88c519af5a..adb70bc20971 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -430,3 +430,4 @@ mod tests { assert_eq!(loop_analysis.loop_level(block5).level(), 1); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 0c4b205433cb..35ce6223bd83 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -2617,3 +2617,4 @@ mod tests { assert_eq!(core::mem::size_of::(), 24); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 671426e600b2..484e867f845b 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -483,3 +483,4 @@ mod test { assert!(order.lowered_order[8].out_edge().is_none()); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index b76f4a5d7d48..dd295bf2d392 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -2916,3 +2916,4 @@ mod test { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index 9c7d2d55bd26..ee597bb9e94d 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -96,3 +96,4 @@ pub fn compile( Ok((vcode, regalloc_result)) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 01f397c8c67f..222dc072e470 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -21,3 +21,4 @@ where let alignment_mask = alignment - 1.into(); (x + alignment_mask) & !alignment_mask } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/inst_common.rs b/cranelift/codegen/src/machinst/inst_common.rs index b077dd3b6112..1a15cde4e1fa 100644 --- a/cranelift/codegen/src/machinst/inst_common.rs +++ b/cranelift/codegen/src/machinst/inst_common.rs @@ -14,3 +14,4 @@ pub struct InsnInput { pub(crate) insn: IRInst, pub(crate) input: usize, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index 8a64fab294f3..f8cc77def53d 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -849,3 +849,4 @@ where &self.lower_ctx.f.dfg } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 930f4aaa4b30..76438cc3cacd 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -1799,3 +1799,4 @@ mod tests { assert_eq!(uses[v5], ValueUseState::Unused); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 61ebb9bc0800..6bc6890f8a35 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -628,3 +628,4 @@ pub trait TextSectionBuilder { /// the bytes of the text section. fn finish(&mut self, ctrl_plane: &mut ControlPlane) -> Vec; } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/pcc.rs b/cranelift/codegen/src/machinst/pcc.rs index 046b2ca3b3e2..665790bad4b9 100644 --- a/cranelift/codegen/src/machinst/pcc.rs +++ b/cranelift/codegen/src/machinst/pcc.rs @@ -164,3 +164,4 @@ pub(crate) enum LoadOrStore<'a> { stored_fact: Option<&'a Fact>, }, } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index dd28ee05f4c8..5d364601297d 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -563,3 +563,4 @@ pub trait PrettyPrint { self.pretty_print(0) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index 8a684d868f86..f7d3a2c0c91b 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -150,3 +150,4 @@ pub(crate) fn writable_value_regs(regs: ValueRegs) -> ValueRegs>) -> ValueRegs { regs.map(|r| r.to_reg()) } +use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 09d299968c54..ae142ec487a8 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -2062,3 +2062,4 @@ mod test { // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes. } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/nan_canonicalization.rs b/cranelift/codegen/src/nan_canonicalization.rs index e6a73deaf83a..04f8ffdc0f6f 100644 --- a/cranelift/codegen/src/nan_canonicalization.rs +++ b/cranelift/codegen/src/nan_canonicalization.rs @@ -124,3 +124,4 @@ fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst, has_vector_support: bool) pos.prev_inst(); // Step backwards so the pass does not skip instructions. } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 4ec9728f1e35..50ced940f133 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -368,3 +368,4 @@ impl<'a, 'b, 'c> generated_code::Context for IsleContext<'a, 'b, 'c> { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/div_const.rs b/cranelift/codegen/src/opts/div_const.rs index a88f0c6344f5..4ef0163a2d8b 100644 --- a/cranelift/codegen/src/opts/div_const.rs +++ b/cranelift/codegen/src/opts/div_const.rs @@ -1212,3 +1212,4 @@ mod tests { } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/generated_code.rs b/cranelift/codegen/src/opts/generated_code.rs index 82208623362a..2ff9eaef16bc 100644 --- a/cranelift/codegen/src/opts/generated_code.rs +++ b/cranelift/codegen/src/opts/generated_code.rs @@ -16,3 +16,4 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_opt.rs")); +use crate::prelude::*; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index b2d13852bc08..981d7fe27e43 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,4 +1,8 @@ -use alloc::format; -use alloc::string::{String, ToString}; -use alloc::vec::Vec; -use alloc::vec; +pub use alloc::format; +pub use alloc::string::{String, ToString}; +pub use alloc::vec::Vec; +pub use alloc::vec; +pub use alloc::slice; + +pub use core::prelude::*; +pub use core::ops; \ No newline at end of file diff --git a/cranelift/codegen/src/print_errors.rs b/cranelift/codegen/src/print_errors.rs index 21a2767267e8..348497eeb96b 100644 --- a/cranelift/codegen/src/print_errors.rs +++ b/cranelift/codegen/src/print_errors.rs @@ -221,3 +221,4 @@ pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String { err.to_string() } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/ranges.rs b/cranelift/codegen/src/ranges.rs index 419dee83c08f..4ea817d64457 100644 --- a/cranelift/codegen/src/ranges.rs +++ b/cranelift/codegen/src/ranges.rs @@ -129,3 +129,4 @@ impl Ranges { self.reverse_index(); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index ab5def4f75b4..dd0fbbba4959 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -418,3 +418,4 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) n_consts ); } +use crate::prelude::*; diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index c62572cd9958..0f56d06772ed 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -109,3 +109,4 @@ impl<'a> core::fmt::Debug for CompileError<'a> { /// A convenient alias for a `Result` that uses `CompileError` as the error type. pub type CompileResult<'a, T> = Result>; +use crate::prelude::*; diff --git a/cranelift/codegen/src/scoped_hash_map.rs b/cranelift/codegen/src/scoped_hash_map.rs index b599d36dc205..0835af1c4368 100644 --- a/cranelift/codegen/src/scoped_hash_map.rs +++ b/cranelift/codegen/src/scoped_hash_map.rs @@ -332,3 +332,4 @@ mod tests { assert_eq!(map.get(&NullCtx, &3), Some(&4)); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 90b835c0965a..cd54f5b9f356 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -567,3 +567,4 @@ enable_incremental_compilation_cache_checks = false assert_eq!(f.opt_level(), super::OptLevel::Speed); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/souper_harvest.rs b/cranelift/codegen/src/souper_harvest.rs index 02958ed56a71..5ea25882bae3 100644 --- a/cranelift/codegen/src/souper_harvest.rs +++ b/cranelift/codegen/src/souper_harvest.rs @@ -587,3 +587,4 @@ fn post_order_dfs( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index 584d9239d0fa..e6232e901a39 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -89,3 +89,4 @@ where (&mut *self.container, &mut self.value) } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index a06c6001ef41..0c02dcb790c8 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -303,3 +303,4 @@ mod tests { assert_eq!(Pass::regalloc.to_string(), "Register allocation"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/traversals.rs b/cranelift/codegen/src/traversals.rs index db57036aacd6..24e8feb38b61 100644 --- a/cranelift/codegen/src/traversals.rs +++ b/cranelift/codegen/src/traversals.rs @@ -277,3 +277,4 @@ mod tests { ); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/unreachable_code.rs b/cranelift/codegen/src/unreachable_code.rs index 68d7bd33fdeb..7af5e6d7d33c 100644 --- a/cranelift/codegen/src/unreachable_code.rs +++ b/cranelift/codegen/src/unreachable_code.rs @@ -71,3 +71,4 @@ pub fn eliminate_unreachable_code( } } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/value_label.rs b/cranelift/codegen/src/value_label.rs index 65b3e7d1eac9..f822e19437c8 100644 --- a/cranelift/codegen/src/value_label.rs +++ b/cranelift/codegen/src/value_label.rs @@ -30,3 +30,4 @@ pub enum LabelValueLoc { /// Resulting map of Value labels and their ranges/locations. pub type ValueLabelsRanges = HashMap>; +use crate::prelude::*; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 822d6e27ede0..015ba58afe40 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2315,3 +2315,4 @@ mod tests { assert_err_with_msg!(errors, "block0 cannot be empty"); } } +use crate::prelude::*; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index 1961a57dfd9a..6442ccbe3632 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -750,3 +750,4 @@ mod tests { ); } } +use crate::prelude::*; From 3ccba9f662340c1c8d573b09ad651f4773762a4c Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 19:33:44 +0100 Subject: [PATCH 40/61] update isle to use alloc and core --- cranelift/isle/isle/src/codegen.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cranelift/isle/isle/src/codegen.rs b/cranelift/isle/isle/src/codegen.rs index 78a8fee729e7..e42ef1ae5a7c 100644 --- a/cranelift/isle/isle/src/codegen.rs +++ b/cranelift/isle/isle/src/codegen.rs @@ -166,7 +166,8 @@ impl<'a> Codegen<'a> { } writeln!(code, "\nuse super::*; // Pulls in all external types.").unwrap(); - writeln!(code, "use core::marker::PhantomData;").unwrap(); + writeln!(code, "use alloc::vec::Vec;").unwrap(); + writeln!(code, "use core::{{marker::PhantomData, ops}};").unwrap(); } fn generate_trait_sig(&self, code: &mut String, indent: &str, sig: &ExternalSig) { From 6e2f58de3ee6021e1fa8e8b12ea045a890f587b9 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:00:47 +0100 Subject: [PATCH 41/61] add cranelift-assembler-x64 (no_std) to CI --- .github/workflows/main.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 50e7d5bd599c..592cea2b3635 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,8 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && - cargo check -p cranelift-assembler-x64 --lib && - cargo check -p cranelift-codegen --no-default-features -F x86,arm64 && + cargo check -p cranelift-assembler-x64 --no-default-features -F core && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. From 3d88bcf9f9a1fb24b4dfc4c3b3403d26a1d35300 Mon Sep 17 00:00:00 2001 From: SSD Date: Sat, 27 Dec 2025 20:25:58 +0100 Subject: [PATCH 42/61] automatically remove prelude with cargo fix --- cranelift/codegen/src/binemit/mod.rs | 1 - cranelift/codegen/src/cfg_printer.rs | 1 - cranelift/codegen/src/constant_hash.rs | 1 - cranelift/codegen/src/context.rs | 1 - cranelift/codegen/src/ctxhash.rs | 1 - cranelift/codegen/src/cursor.rs | 1 - cranelift/codegen/src/dbg.rs | 1 - cranelift/codegen/src/dominator_tree/simple.rs | 1 - cranelift/codegen/src/egraph/cost.rs | 1 - cranelift/codegen/src/flowgraph.rs | 1 - cranelift/codegen/src/inst_predicates.rs | 1 - cranelift/codegen/src/ir/atomic_rmw_op.rs | 1 - cranelift/codegen/src/ir/builder.rs | 1 - cranelift/codegen/src/ir/condcodes.rs | 1 - cranelift/codegen/src/ir/constant.rs | 1 - cranelift/codegen/src/ir/dfg.rs | 1 - cranelift/codegen/src/ir/dynamic_type.rs | 1 - cranelift/codegen/src/ir/extfunc.rs | 1 - cranelift/codegen/src/ir/extname.rs | 1 - cranelift/codegen/src/ir/function.rs | 1 - cranelift/codegen/src/ir/globalvalue.rs | 1 - cranelift/codegen/src/ir/instructions.rs | 1 - cranelift/codegen/src/ir/jumptable.rs | 1 - cranelift/codegen/src/ir/known_symbol.rs | 1 - cranelift/codegen/src/ir/libcall.rs | 1 - cranelift/codegen/src/ir/memflags.rs | 1 - cranelift/codegen/src/ir/memtype.rs | 1 - cranelift/codegen/src/ir/mod.rs | 1 - cranelift/codegen/src/ir/pcc.rs | 1 - cranelift/codegen/src/ir/progpoint.rs | 1 - cranelift/codegen/src/ir/sourceloc.rs | 1 - cranelift/codegen/src/ir/user_stack_maps.rs | 1 - cranelift/codegen/src/isa/call_conv.rs | 1 - cranelift/codegen/src/isa/mod.rs | 2 +- cranelift/codegen/src/isa/unwind.rs | 1 - cranelift/codegen/src/isa/winch.rs | 1 - cranelift/codegen/src/isa/x64/inst/emit.rs | 1 - cranelift/codegen/src/isa/x64/inst/emit_state.rs | 1 - cranelift/codegen/src/isa/x64/inst/stack_switch.rs | 1 - cranelift/codegen/src/isa/x64/inst/unwind.rs | 1 - cranelift/codegen/src/isa/x64/lower.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 2 +- cranelift/codegen/src/isa/x64/pcc.rs | 1 - cranelift/codegen/src/isa/x64/settings.rs | 1 - cranelift/codegen/src/isle_prelude.rs | 1 - cranelift/codegen/src/legalizer/branch_to_trap.rs | 1 - cranelift/codegen/src/legalizer/globalvalue.rs | 1 - cranelift/codegen/src/legalizer/mod.rs | 1 - cranelift/codegen/src/lib.rs | 3 +-- cranelift/codegen/src/loop_analysis.rs | 1 - cranelift/codegen/src/machinst/blockorder.rs | 1 - cranelift/codegen/src/machinst/compile.rs | 1 - cranelift/codegen/src/machinst/helpers.rs | 1 - cranelift/codegen/src/machinst/isle.rs | 1 - cranelift/codegen/src/machinst/mod.rs | 1 - cranelift/codegen/src/machinst/pcc.rs | 1 - cranelift/codegen/src/machinst/valueregs.rs | 1 - cranelift/codegen/src/nan_canonicalization.rs | 1 - cranelift/codegen/src/opts.rs | 1 - cranelift/codegen/src/opts/div_const.rs | 1 - cranelift/codegen/src/prelude.rs | 6 +----- cranelift/codegen/src/print_errors.rs | 1 - cranelift/codegen/src/ranges.rs | 1 - cranelift/codegen/src/remove_constant_phis.rs | 1 - cranelift/codegen/src/result.rs | 1 - cranelift/codegen/src/scoped_hash_map.rs | 1 - cranelift/codegen/src/take_and_replace.rs | 1 - cranelift/codegen/src/timing.rs | 1 - cranelift/codegen/src/traversals.rs | 1 - cranelift/codegen/src/unreachable_code.rs | 1 - cranelift/codegen/src/value_label.rs | 1 - 71 files changed, 4 insertions(+), 76 deletions(-) diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs index 022eb7db5fca..cd34c0b3ff13 100644 --- a/cranelift/codegen/src/binemit/mod.rs +++ b/cranelift/codegen/src/binemit/mod.rs @@ -190,4 +190,3 @@ pub struct CodeInfo { /// Number of bytes in total. pub total_size: CodeOffset, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/cfg_printer.rs b/cranelift/codegen/src/cfg_printer.rs index 8c07f0ac478b..ef71b63ca712 100644 --- a/cranelift/codegen/src/cfg_printer.rs +++ b/cranelift/codegen/src/cfg_printer.rs @@ -81,4 +81,3 @@ impl<'a> Display for CFGPrinter<'a> { self.write(f) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/constant_hash.rs b/cranelift/codegen/src/constant_hash.rs index be018675b5e2..1de2a2edb43e 100644 --- a/cranelift/codegen/src/constant_hash.rs +++ b/cranelift/codegen/src/constant_hash.rs @@ -60,4 +60,3 @@ pub fn probe + ?Sized>( idx += step; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index 46267cb446d2..c37de05497bc 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -391,4 +391,3 @@ impl Context { self.verify_if(fisa) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 7e6b852907f3..7148046ae9c1 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -223,4 +223,3 @@ mod test { assert_eq!(*map.get(&k0, &ctx).unwrap(), 84); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/cursor.rs b/cranelift/codegen/src/cursor.rs index b1bec22fa159..ae7b0ea874ad 100644 --- a/cranelift/codegen/src/cursor.rs +++ b/cranelift/codegen/src/cursor.rs @@ -687,4 +687,3 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> { &mut self.func.dfg } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dbg.rs b/cranelift/codegen/src/dbg.rs index 8a0da7a24aed..4796f3967b91 100644 --- a/cranelift/codegen/src/dbg.rs +++ b/cranelift/codegen/src/dbg.rs @@ -26,4 +26,3 @@ where } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree/simple.rs b/cranelift/codegen/src/dominator_tree/simple.rs index 9abc47e4df95..853158bc80b1 100644 --- a/cranelift/codegen/src/dominator_tree/simple.rs +++ b/cranelift/codegen/src/dominator_tree/simple.rs @@ -582,4 +582,3 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/cost.rs b/cranelift/codegen/src/egraph/cost.rs index f2f2048497b9..062196964c96 100644 --- a/cranelift/codegen/src/egraph/cost.rs +++ b/cranelift/codegen/src/egraph/cost.rs @@ -236,4 +236,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/flowgraph.rs b/cranelift/codegen/src/flowgraph.rs index 9358c851b4e3..6478dfddbf90 100644 --- a/cranelift/codegen/src/flowgraph.rs +++ b/cranelift/codegen/src/flowgraph.rs @@ -347,4 +347,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/inst_predicates.rs b/cranelift/codegen/src/inst_predicates.rs index 91cb01ca7cf3..7b42e1728663 100644 --- a/cranelift/codegen/src/inst_predicates.rs +++ b/cranelift/codegen/src/inst_predicates.rs @@ -215,4 +215,3 @@ pub(crate) fn visit_block_succs( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/atomic_rmw_op.rs b/cranelift/codegen/src/ir/atomic_rmw_op.rs index ea6a16b7d969..0317fc00d2c1 100644 --- a/cranelift/codegen/src/ir/atomic_rmw_op.rs +++ b/cranelift/codegen/src/ir/atomic_rmw_op.rs @@ -102,4 +102,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/builder.rs b/cranelift/codegen/src/ir/builder.rs index c36673bd79ee..24d9beaee660 100644 --- a/cranelift/codegen/src/ir/builder.rs +++ b/cranelift/codegen/src/ir/builder.rs @@ -280,4 +280,3 @@ mod tests { .Trap(Opcode::Return, I32, TrapCode::BAD_CONVERSION_TO_INTEGER); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/condcodes.rs b/cranelift/codegen/src/ir/condcodes.rs index 454423f7a189..009f95bf391c 100644 --- a/cranelift/codegen/src/ir/condcodes.rs +++ b/cranelift/codegen/src/ir/condcodes.rs @@ -402,4 +402,3 @@ mod tests { assert_eq!("bogus".parse::(), Err(())); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/constant.rs b/cranelift/codegen/src/ir/constant.rs index 5612510c8f33..67310cd9462f 100644 --- a/cranelift/codegen/src/ir/constant.rs +++ b/cranelift/codegen/src/ir/constant.rs @@ -485,4 +485,3 @@ mod tests { assert_eq!(Ieee128::try_from(&constant).unwrap().bits(), value.bits()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dfg.rs b/cranelift/codegen/src/ir/dfg.rs index e48cdd42d990..3dd2ad4211c3 100644 --- a/cranelift/codegen/src/ir/dfg.rs +++ b/cranelift/codegen/src/ir/dfg.rs @@ -1882,4 +1882,3 @@ mod tests { assert_eq!(v1, func.dfg.inst_args(call_inst_dup)[0]); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/dynamic_type.rs b/cranelift/codegen/src/ir/dynamic_type.rs index 369bcc74eeba..53027c196945 100644 --- a/cranelift/codegen/src/ir/dynamic_type.rs +++ b/cranelift/codegen/src/ir/dynamic_type.rs @@ -52,4 +52,3 @@ pub fn dynamic_to_fixed(ty: Type) -> Type { _ => unreachable!("unhandled type: {}", ty), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extfunc.rs b/cranelift/codegen/src/ir/extfunc.rs index 61880e27fc84..ebfaf3a8ddaf 100644 --- a/cranelift/codegen/src/ir/extfunc.rs +++ b/cranelift/codegen/src/ir/extfunc.rs @@ -418,4 +418,3 @@ mod tests { assert_eq!(sig.to_string(), "(i32, i32x4) -> f32, i8 windows_fastcall"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/extname.rs b/cranelift/codegen/src/ir/extname.rs index e80fb4cf34b4..d28ebcb4e7b2 100644 --- a/cranelift/codegen/src/ir/extname.rs +++ b/cranelift/codegen/src/ir/extname.rs @@ -336,4 +336,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/function.rs b/cranelift/codegen/src/ir/function.rs index 296d0c9cf938..80926edcdf1c 100644 --- a/cranelift/codegen/src/ir/function.rs +++ b/cranelift/codegen/src/ir/function.rs @@ -517,4 +517,3 @@ impl<'a> fmt::Debug for DisplayFunctionSpec<'a> { write_function_spec(fmt, self.0) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/globalvalue.rs b/cranelift/codegen/src/ir/globalvalue.rs index 8ea7372c7349..89120c8b8364 100644 --- a/cranelift/codegen/src/ir/globalvalue.rs +++ b/cranelift/codegen/src/ir/globalvalue.rs @@ -145,4 +145,3 @@ impl fmt::Display for GlobalValueData { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/instructions.rs b/cranelift/codegen/src/ir/instructions.rs index 6a95b1ce9975..80c04e48e6fb 100644 --- a/cranelift/codegen/src/ir/instructions.rs +++ b/cranelift/codegen/src/ir/instructions.rs @@ -1538,4 +1538,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/jumptable.rs b/cranelift/codegen/src/ir/jumptable.rs index 85d6d77b1a51..5bdad87d941f 100644 --- a/cranelift/codegen/src/ir/jumptable.rs +++ b/cranelift/codegen/src/ir/jumptable.rs @@ -173,4 +173,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/known_symbol.rs b/cranelift/codegen/src/ir/known_symbol.rs index 6c594b7faff3..c3d17501a39b 100644 --- a/cranelift/codegen/src/ir/known_symbol.rs +++ b/cranelift/codegen/src/ir/known_symbol.rs @@ -45,4 +45,3 @@ mod tests { assert_eq!("CoffTlsIndex".parse(), Ok(KnownSymbol::CoffTlsIndex)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/libcall.rs b/cranelift/codegen/src/ir/libcall.rs index 3cf1ebb2d7f2..6b60dfd07d27 100644 --- a/cranelift/codegen/src/ir/libcall.rs +++ b/cranelift/codegen/src/ir/libcall.rs @@ -230,4 +230,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memflags.rs b/cranelift/codegen/src/ir/memflags.rs index 726004dcd59f..45f32ce85fd2 100644 --- a/cranelift/codegen/src/ir/memflags.rs +++ b/cranelift/codegen/src/ir/memflags.rs @@ -485,4 +485,3 @@ mod tests { assert!(big.set_by_name("table").is_err()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/memtype.rs b/cranelift/codegen/src/ir/memtype.rs index 8501c9bb73a3..b7b0d7e2db1e 100644 --- a/cranelift/codegen/src/ir/memtype.rs +++ b/cranelift/codegen/src/ir/memtype.rs @@ -188,4 +188,3 @@ impl MemoryTypeData { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/mod.rs b/cranelift/codegen/src/ir/mod.rs index db671b366444..eca17e7badda 100644 --- a/cranelift/codegen/src/ir/mod.rs +++ b/cranelift/codegen/src/ir/mod.rs @@ -117,4 +117,3 @@ pub enum ValueLabelAssignments { value: Value, }, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index f9062a1ddad6..d1bf7ea62dba 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -1679,4 +1679,3 @@ pub fn check_vcode_facts( } Ok(()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/progpoint.rs b/cranelift/codegen/src/ir/progpoint.rs index dafcd16d7c5d..84d394276f67 100644 --- a/cranelift/codegen/src/ir/progpoint.rs +++ b/cranelift/codegen/src/ir/progpoint.rs @@ -73,4 +73,3 @@ mod tests { assert_eq!(pp2.to_string(), "block3"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/sourceloc.rs b/cranelift/codegen/src/ir/sourceloc.rs index 38efbe2939aa..6704574d0d09 100644 --- a/cranelift/codegen/src/ir/sourceloc.rs +++ b/cranelift/codegen/src/ir/sourceloc.rs @@ -115,4 +115,3 @@ mod tests { assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/user_stack_maps.rs b/cranelift/codegen/src/ir/user_stack_maps.rs index 92aaa198effa..6ad9b697cd02 100644 --- a/cranelift/codegen/src/ir/user_stack_maps.rs +++ b/cranelift/codegen/src/ir/user_stack_maps.rs @@ -197,4 +197,3 @@ impl UserStackMap { }) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/call_conv.rs b/cranelift/codegen/src/isa/call_conv.rs index 65e6c514c830..a8f6ce50203e 100644 --- a/cranelift/codegen/src/isa/call_conv.rs +++ b/cranelift/codegen/src/isa/call_conv.rs @@ -153,4 +153,3 @@ impl str::FromStr for CallConv { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2c31830e139a..2c44409de892 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -50,7 +50,7 @@ use crate::CodegenResult; use crate::ir::{self, Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::{UnwindInfoKind, systemv::RegisterMappingError}; -use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder}; +use crate::machinst::{CompiledCodeStencil, TextSectionBuilder}; use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index 08cb2c7cbb14..a2e47590f4d3 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -250,4 +250,3 @@ impl<'a> Writer<'a> { self.offset += 4; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/winch.rs b/cranelift/codegen/src/isa/winch.rs index 8e9bbf0efdc3..df8fdce35223 100644 --- a/cranelift/codegen/src/isa/winch.rs +++ b/cranelift/codegen/src/isa/winch.rs @@ -20,4 +20,3 @@ pub(super) fn reverse_stack(mut args: ArgsAccumulator, next_stack: u32, uses_ext } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 2374d6e63b58..363f9194bd6f 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -2193,4 +2193,3 @@ fn emit_lea( _ => lea(*dst.as_ref(), addr, sink), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_state.rs b/cranelift/codegen/src/isa/x64/inst/emit_state.rs index 98ffebf3f3be..426a17a2803b 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_state.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_state.rs @@ -53,4 +53,3 @@ impl EmitState { self.user_stack_map = None; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs index d32c59dd9fee..4c9400df41bf 100644 --- a/cranelift/codegen/src/isa/x64/inst/stack_switch.rs +++ b/cranelift/codegen/src/isa/x64/inst/stack_switch.rs @@ -47,4 +47,3 @@ pub fn control_context_layout() -> ControlContextLayout { pub fn payload_register() -> Reg { regs::rdi() } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind.rs b/cranelift/codegen/src/isa/x64/inst/unwind.rs index 56289f082012..cb86c3b7ccd5 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind.rs @@ -3,4 +3,3 @@ pub(crate) mod systemv; #[cfg(feature = "unwind")] pub(crate) mod winx64; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 210f1d964a71..a000f8ece143 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -351,4 +351,3 @@ impl LowerBackend for X64Backend { type FactFlowState = pcc::FactFlowState; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 9cd8cc6085c4..5028c3b21bad 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -10,7 +10,7 @@ use crate::isa::unwind::systemv; use crate::isa::x64::settings as x64_settings; use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey}; use crate::machinst::{ - CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, + CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/pcc.rs b/cranelift/codegen/src/isa/x64/pcc.rs index b82eb7d5014e..09b356d69958 100644 --- a/cranelift/codegen/src/isa/x64/pcc.rs +++ b/cranelift/codegen/src/isa/x64/pcc.rs @@ -324,4 +324,3 @@ fn compute_addr(ctx: &FactContext, vcode: &VCode, amode: &Amode, bits: u16 Amode::RipRelative { .. } => None, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/settings.rs b/cranelift/codegen/src/isa/x64/settings.rs index 83faa5585cb6..12420311b34c 100644 --- a/cranelift/codegen/src/isa/x64/settings.rs +++ b/cranelift/codegen/src/isa/x64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/x86/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-x86.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs index 7e974bff3f56..a2b58b15431d 100644 --- a/cranelift/codegen/src/isle_prelude.rs +++ b/cranelift/codegen/src/isle_prelude.rs @@ -941,4 +941,3 @@ macro_rules! isle_common_prelude_methods { } }; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/branch_to_trap.rs b/cranelift/codegen/src/legalizer/branch_to_trap.rs index 330c47abc6e7..1cbb0e657ffb 100644 --- a/cranelift/codegen/src/legalizer/branch_to_trap.rs +++ b/cranelift/codegen/src/legalizer/branch_to_trap.rs @@ -96,4 +96,3 @@ impl BranchToTrap { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/globalvalue.rs b/cranelift/codegen/src/legalizer/globalvalue.rs index 85b7dee06108..45444d161934 100644 --- a/cranelift/codegen/src/legalizer/globalvalue.rs +++ b/cranelift/codegen/src/legalizer/globalvalue.rs @@ -176,4 +176,3 @@ fn symbol( WalkCommand::Continue } -use crate::prelude::*; diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs index 44dcd1ad4dcb..768afd306752 100644 --- a/cranelift/codegen/src/legalizer/mod.rs +++ b/cranelift/codegen/src/legalizer/mod.rs @@ -392,4 +392,3 @@ fn expand_stack_load( WalkCommand::Continue } -use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index f167528ad3fc..586dfd74b139 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -21,7 +21,7 @@ extern crate alloc; extern crate std; #[cfg(not(feature = "std"))] -use hashbrown::{HashMap, HashSet, hash_map}; +use hashbrown::{HashMap, hash_map}; #[cfg(feature = "std")] use std::collections::{HashMap, HashSet, hash_map}; @@ -131,4 +131,3 @@ macro_rules! trace_log_enabled { } include!(concat!(env!("OUT_DIR"), "/version.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/loop_analysis.rs b/cranelift/codegen/src/loop_analysis.rs index adb70bc20971..5d88c519af5a 100644 --- a/cranelift/codegen/src/loop_analysis.rs +++ b/cranelift/codegen/src/loop_analysis.rs @@ -430,4 +430,3 @@ mod tests { assert_eq!(loop_analysis.loop_level(block5).level(), 1); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/blockorder.rs b/cranelift/codegen/src/machinst/blockorder.rs index 484e867f845b..671426e600b2 100644 --- a/cranelift/codegen/src/machinst/blockorder.rs +++ b/cranelift/codegen/src/machinst/blockorder.rs @@ -483,4 +483,3 @@ mod test { assert!(order.lowered_order[8].out_edge().is_none()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index ee597bb9e94d..9c7d2d55bd26 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -96,4 +96,3 @@ pub fn compile( Ok((vcode, regalloc_result)) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/helpers.rs b/cranelift/codegen/src/machinst/helpers.rs index 222dc072e470..01f397c8c67f 100644 --- a/cranelift/codegen/src/machinst/helpers.rs +++ b/cranelift/codegen/src/machinst/helpers.rs @@ -21,4 +21,3 @@ where let alignment_mask = alignment - 1.into(); (x + alignment_mask) & !alignment_mask } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index f8cc77def53d..8a64fab294f3 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -849,4 +849,3 @@ where &self.lower_ctx.f.dfg } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 6bc6890f8a35..61ebb9bc0800 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -628,4 +628,3 @@ pub trait TextSectionBuilder { /// the bytes of the text section. fn finish(&mut self, ctrl_plane: &mut ControlPlane) -> Vec; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/pcc.rs b/cranelift/codegen/src/machinst/pcc.rs index 665790bad4b9..046b2ca3b3e2 100644 --- a/cranelift/codegen/src/machinst/pcc.rs +++ b/cranelift/codegen/src/machinst/pcc.rs @@ -164,4 +164,3 @@ pub(crate) enum LoadOrStore<'a> { stored_fact: Option<&'a Fact>, }, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/valueregs.rs b/cranelift/codegen/src/machinst/valueregs.rs index f7d3a2c0c91b..8a684d868f86 100644 --- a/cranelift/codegen/src/machinst/valueregs.rs +++ b/cranelift/codegen/src/machinst/valueregs.rs @@ -150,4 +150,3 @@ pub(crate) fn writable_value_regs(regs: ValueRegs) -> ValueRegs>) -> ValueRegs { regs.map(|r| r.to_reg()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/nan_canonicalization.rs b/cranelift/codegen/src/nan_canonicalization.rs index 04f8ffdc0f6f..e6a73deaf83a 100644 --- a/cranelift/codegen/src/nan_canonicalization.rs +++ b/cranelift/codegen/src/nan_canonicalization.rs @@ -124,4 +124,3 @@ fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst, has_vector_support: bool) pos.prev_inst(); // Step backwards so the pass does not skip instructions. } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 50ced940f133..4ec9728f1e35 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -368,4 +368,3 @@ impl<'a, 'b, 'c> generated_code::Context for IsleContext<'a, 'b, 'c> { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts/div_const.rs b/cranelift/codegen/src/opts/div_const.rs index 4ef0163a2d8b..a88f0c6344f5 100644 --- a/cranelift/codegen/src/opts/div_const.rs +++ b/cranelift/codegen/src/opts/div_const.rs @@ -1212,4 +1212,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs index 981d7fe27e43..5dd5950bdf86 100644 --- a/cranelift/codegen/src/prelude.rs +++ b/cranelift/codegen/src/prelude.rs @@ -1,8 +1,4 @@ pub use alloc::format; -pub use alloc::string::{String, ToString}; -pub use alloc::vec::Vec; +pub use alloc::string::ToString; pub use alloc::vec; -pub use alloc::slice; -pub use core::prelude::*; -pub use core::ops; \ No newline at end of file diff --git a/cranelift/codegen/src/print_errors.rs b/cranelift/codegen/src/print_errors.rs index 348497eeb96b..21a2767267e8 100644 --- a/cranelift/codegen/src/print_errors.rs +++ b/cranelift/codegen/src/print_errors.rs @@ -221,4 +221,3 @@ pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String { err.to_string() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ranges.rs b/cranelift/codegen/src/ranges.rs index 4ea817d64457..419dee83c08f 100644 --- a/cranelift/codegen/src/ranges.rs +++ b/cranelift/codegen/src/ranges.rs @@ -129,4 +129,3 @@ impl Ranges { self.reverse_index(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/remove_constant_phis.rs b/cranelift/codegen/src/remove_constant_phis.rs index dd0fbbba4959..ab5def4f75b4 100644 --- a/cranelift/codegen/src/remove_constant_phis.rs +++ b/cranelift/codegen/src/remove_constant_phis.rs @@ -418,4 +418,3 @@ pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) n_consts ); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/result.rs b/cranelift/codegen/src/result.rs index 0f56d06772ed..c62572cd9958 100644 --- a/cranelift/codegen/src/result.rs +++ b/cranelift/codegen/src/result.rs @@ -109,4 +109,3 @@ impl<'a> core::fmt::Debug for CompileError<'a> { /// A convenient alias for a `Result` that uses `CompileError` as the error type. pub type CompileResult<'a, T> = Result>; -use crate::prelude::*; diff --git a/cranelift/codegen/src/scoped_hash_map.rs b/cranelift/codegen/src/scoped_hash_map.rs index 0835af1c4368..b599d36dc205 100644 --- a/cranelift/codegen/src/scoped_hash_map.rs +++ b/cranelift/codegen/src/scoped_hash_map.rs @@ -332,4 +332,3 @@ mod tests { assert_eq!(map.get(&NullCtx, &3), Some(&4)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/take_and_replace.rs b/cranelift/codegen/src/take_and_replace.rs index e6232e901a39..584d9239d0fa 100644 --- a/cranelift/codegen/src/take_and_replace.rs +++ b/cranelift/codegen/src/take_and_replace.rs @@ -89,4 +89,3 @@ where (&mut *self.container, &mut self.value) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/timing.rs b/cranelift/codegen/src/timing.rs index 0c02dcb790c8..a06c6001ef41 100644 --- a/cranelift/codegen/src/timing.rs +++ b/cranelift/codegen/src/timing.rs @@ -303,4 +303,3 @@ mod tests { assert_eq!(Pass::regalloc.to_string(), "Register allocation"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/traversals.rs b/cranelift/codegen/src/traversals.rs index 24e8feb38b61..db57036aacd6 100644 --- a/cranelift/codegen/src/traversals.rs +++ b/cranelift/codegen/src/traversals.rs @@ -277,4 +277,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/unreachable_code.rs b/cranelift/codegen/src/unreachable_code.rs index 7af5e6d7d33c..68d7bd33fdeb 100644 --- a/cranelift/codegen/src/unreachable_code.rs +++ b/cranelift/codegen/src/unreachable_code.rs @@ -71,4 +71,3 @@ pub fn eliminate_unreachable_code( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/value_label.rs b/cranelift/codegen/src/value_label.rs index f822e19437c8..65b3e7d1eac9 100644 --- a/cranelift/codegen/src/value_label.rs +++ b/cranelift/codegen/src/value_label.rs @@ -30,4 +30,3 @@ pub enum LabelValueLoc { /// Resulting map of Value labels and their ranges/locations. pub type ValueLabelsRanges = HashMap>; -use crate::prelude::*; From 91639174bdbef46f4ada3ad21e0d284bacf0ce6e Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 00:16:09 +0100 Subject: [PATCH 43/61] update isle changes --- cranelift/isle/isle/src/codegen.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/cranelift/isle/isle/src/codegen.rs b/cranelift/isle/isle/src/codegen.rs index e42ef1ae5a7c..78a8fee729e7 100644 --- a/cranelift/isle/isle/src/codegen.rs +++ b/cranelift/isle/isle/src/codegen.rs @@ -166,8 +166,7 @@ impl<'a> Codegen<'a> { } writeln!(code, "\nuse super::*; // Pulls in all external types.").unwrap(); - writeln!(code, "use alloc::vec::Vec;").unwrap(); - writeln!(code, "use core::{{marker::PhantomData, ops}};").unwrap(); + writeln!(code, "use core::marker::PhantomData;").unwrap(); } fn generate_trait_sig(&self, code: &mut String, indent: &str, sig: &ExternalSig) { From d632990923e03544eec82e70cc1b580ddb388695 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 00:16:50 +0100 Subject: [PATCH 44/61] update assembler changes --- cranelift/assembler-x64/Cargo.toml | 1 - cranelift/assembler-x64/src/api.rs | 3 ++- cranelift/assembler-x64/src/custom.rs | 2 +- cranelift/assembler-x64/src/imm.rs | 4 +--- cranelift/assembler-x64/src/inst.rs | 1 - cranelift/assembler-x64/src/lib.rs | 4 +++- cranelift/assembler-x64/src/main.rs | 12 ------------ cranelift/assembler-x64/src/mem.rs | 3 --- cranelift/assembler-x64/src/xmm.rs | 2 -- 9 files changed, 7 insertions(+), 25 deletions(-) diff --git a/cranelift/assembler-x64/Cargo.toml b/cranelift/assembler-x64/Cargo.toml index 1a49192f219f..ef0822d3113a 100644 --- a/cranelift/assembler-x64/Cargo.toml +++ b/cranelift/assembler-x64/Cargo.toml @@ -23,4 +23,3 @@ workspace = true [features] fuzz = ['dep:arbitrary', 'dep:capstone'] -core = [] diff --git a/cranelift/assembler-x64/src/api.rs b/cranelift/assembler-x64/src/api.rs index f65cfc338045..f861b7726822 100644 --- a/cranelift/assembler-x64/src/api.rs +++ b/cranelift/assembler-x64/src/api.rs @@ -3,10 +3,11 @@ use crate::gpr; use crate::xmm; use crate::{Amode, DeferredTarget, GprMem, XmmMem}; +use alloc::string::String; use alloc::vec::Vec; use core::fmt; use core::num::NonZeroU8; -use alloc::string::String; + /// Describe how an instruction is emitted into a code buffer. pub trait CodeSink { /// Add 1 byte to the code section. diff --git a/cranelift/assembler-x64/src/custom.rs b/cranelift/assembler-x64/src/custom.rs index c2b70fecbc24..25c63e239cf4 100644 --- a/cranelift/assembler-x64/src/custom.rs +++ b/cranelift/assembler-x64/src/custom.rs @@ -191,8 +191,8 @@ pub mod mnemonic { pub mod display { use crate::inst; use crate::{Amode, Gpr, GprMem, Registers, Size}; - use core::fmt; use alloc::string::ToString; + use core::fmt; pub fn callq_d(f: &mut fmt::Formatter, inst: &inst::callq_d) -> fmt::Result { let inst::callq_d { imm32 } = inst; diff --git a/cranelift/assembler-x64/src/imm.rs b/cranelift/assembler-x64/src/imm.rs index 0c129cd65d45..f350952dd23f 100644 --- a/cranelift/assembler-x64/src/imm.rs +++ b/cranelift/assembler-x64/src/imm.rs @@ -1,10 +1,8 @@ //! Immediate operands to instructions. use crate::api::CodeSink; -use core::fmt; - -#[cfg(feature = "core")] use alloc::{format, string::String}; +use core::fmt; /// This helper function prints the unsigned hexadecimal representation of the /// immediate value: e.g., this prints `$0xfe` to represent both the signed `-2` diff --git a/cranelift/assembler-x64/src/inst.rs b/cranelift/assembler-x64/src/inst.rs index e4f23849cd12..c9073401b040 100644 --- a/cranelift/assembler-x64/src/inst.rs +++ b/cranelift/assembler-x64/src/inst.rs @@ -16,7 +16,6 @@ use crate::xmm::{self, Xmm}; use alloc::string::ToString; - // Include code generated by the `meta` crate. include!(concat!(env!("OUT_DIR"), "/assembler.rs")); diff --git a/cranelift/assembler-x64/src/lib.rs b/cranelift/assembler-x64/src/lib.rs index d28e102ffeb7..bf781a50de44 100644 --- a/cranelift/assembler-x64/src/lib.rs +++ b/cranelift/assembler-x64/src/lib.rs @@ -41,8 +41,10 @@ non_camel_case_types, reason = "all of the generated struct names use snake case" )] -#![cfg_attr(feature = "core", no_std)] +#![no_std] extern crate alloc; +#[cfg(any(test, feature = "fuzz"))] +extern crate std; mod api; mod custom; diff --git a/cranelift/assembler-x64/src/main.rs b/cranelift/assembler-x64/src/main.rs index 4361d85624f9..31ae7a7d55c5 100644 --- a/cranelift/assembler-x64/src/main.rs +++ b/cranelift/assembler-x64/src/main.rs @@ -1,19 +1,7 @@ //! Print the path to the generated code. -#![cfg_attr(feature = "core", no_std)] - -#[cfg(not(feature = "core"))] fn main() { let paths: Vec = include!(concat!(env!("OUT_DIR"), "/generated-files.rs")); for path in paths { println!("{}", path.display()); } } - -#[cfg(feature = "core")] -fn main() {} - -#[cfg(feature = "core")] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} \ No newline at end of file diff --git a/cranelift/assembler-x64/src/mem.rs b/cranelift/assembler-x64/src/mem.rs index 3bfc88066009..8235f9b5bfa9 100644 --- a/cranelift/assembler-x64/src/mem.rs +++ b/cranelift/assembler-x64/src/mem.rs @@ -6,9 +6,6 @@ use crate::api::{AsReg, CodeSink, Constant, KnownOffset, Label, TrapCode}; use crate::gpr::{self, NonRspGpr, Size}; use crate::rex::{Disp, RexPrefix, encode_modrm, encode_sib}; -#[cfg(feature = "core")] -use alloc::string::{String, ToString}; - /// x64 memory addressing modes. #[derive(Copy, Clone, Debug, PartialEq)] #[cfg_attr(any(test, feature = "fuzz"), derive(arbitrary::Arbitrary))] diff --git a/cranelift/assembler-x64/src/xmm.rs b/cranelift/assembler-x64/src/xmm.rs index 636c887afbc7..d016e270b8e9 100644 --- a/cranelift/assembler-x64/src/xmm.rs +++ b/cranelift/assembler-x64/src/xmm.rs @@ -2,9 +2,7 @@ use crate::{AsReg, CodeSink, rex::encode_modrm}; -#[cfg(feature = "core")] use alloc::string::String; -//use core::convert::{AsMut, AsRef, From}; /// An x64 SSE register (e.g., `%xmm0`). #[derive(Clone, Copy, Debug)] From 135931b83d2373c66ef0159e8d9bd8e552e01128 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 08:25:44 +0100 Subject: [PATCH 45/61] use latest codegen changes + fix FxHash problem --- .github/workflows/main.yml | 2 +- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/alias_analysis.rs | 2 -- cranelift/codegen/src/ctxhash.rs | 1 - cranelift/codegen/src/data_value.rs | 1 - cranelift/codegen/src/dominator_tree.rs | 1 - cranelift/codegen/src/egraph/elaborate.rs | 1 - cranelift/codegen/src/egraph/mod.rs | 1 - cranelift/codegen/src/incremental_cache.rs | 1 - cranelift/codegen/src/inline.rs | 1 - cranelift/codegen/src/ir/debug_tags.rs | 1 - cranelift/codegen/src/ir/entities.rs | 1 - cranelift/codegen/src/ir/exception_table.rs | 1 - cranelift/codegen/src/ir/immediates.rs | 2 -- cranelift/codegen/src/ir/layout.rs | 1 - cranelift/codegen/src/ir/pcc.rs | 1 - cranelift/codegen/src/ir/stackslot.rs | 1 - cranelift/codegen/src/ir/trapcode.rs | 1 - cranelift/codegen/src/ir/types.rs | 1 - cranelift/codegen/src/isa/aarch64/abi.rs | 2 -- cranelift/codegen/src/isa/aarch64/inst/args.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/emit.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs | 3 +-- cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/mod.rs | 3 --- cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/unwind.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/aarch64/lower.rs | 1 - cranelift/codegen/src/isa/aarch64/lower/isle.rs | 3 --- .../codegen/src/isa/aarch64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/aarch64/mod.rs | 2 -- cranelift/codegen/src/isa/aarch64/pcc.rs | 1 - cranelift/codegen/src/isa/aarch64/settings.rs | 1 - cranelift/codegen/src/isa/mod.rs | 3 +-- cranelift/codegen/src/isa/pulley32.rs | 1 - cranelift/codegen/src/isa/pulley64.rs | 1 - cranelift/codegen/src/isa/pulley_shared/abi.rs | 2 -- cranelift/codegen/src/isa/pulley_shared/inst/args.rs | 2 -- cranelift/codegen/src/isa/pulley_shared/inst/emit.rs | 1 - cranelift/codegen/src/isa/pulley_shared/inst/mod.rs | 1 - cranelift/codegen/src/isa/pulley_shared/inst/regs.rs | 1 - cranelift/codegen/src/isa/pulley_shared/lower.rs | 1 - cranelift/codegen/src/isa/pulley_shared/lower/isle.rs | 1 - .../src/isa/pulley_shared/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/pulley_shared/mod.rs | 2 -- cranelift/codegen/src/isa/pulley_shared/settings.rs | 1 - cranelift/codegen/src/isa/riscv64/abi.rs | 2 -- cranelift/codegen/src/isa/riscv64/inst/args.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/emit.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/encode.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/imms.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/mod.rs | 4 ---- cranelift/codegen/src/isa/riscv64/inst/regs.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/unwind.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 - cranelift/codegen/src/isa/riscv64/lower.rs | 1 - cranelift/codegen/src/isa/riscv64/lower/isle.rs | 3 --- .../codegen/src/isa/riscv64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/riscv64/mod.rs | 2 -- cranelift/codegen/src/isa/riscv64/settings.rs | 1 - cranelift/codegen/src/isa/s390x/abi.rs | 2 -- cranelift/codegen/src/isa/s390x/inst/args.rs | 1 - cranelift/codegen/src/isa/s390x/inst/emit.rs | 1 - cranelift/codegen/src/isa/s390x/inst/emit_tests.rs | 1 - cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 - cranelift/codegen/src/isa/s390x/inst/mod.rs | 3 --- cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 - cranelift/codegen/src/isa/s390x/inst/unwind.rs | 1 - cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/s390x/lower.rs | 1 - cranelift/codegen/src/isa/s390x/lower/isle.rs | 4 ---- .../codegen/src/isa/s390x/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/s390x/mod.rs | 2 -- cranelift/codegen/src/isa/s390x/settings.rs | 1 - cranelift/codegen/src/isa/unwind.rs | 1 - cranelift/codegen/src/isa/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/unwind/winarm64.rs | 1 - cranelift/codegen/src/isa/unwind/winx64.rs | 1 - cranelift/codegen/src/isa/x64/abi.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/args.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/emit_tests.rs | 3 +-- cranelift/codegen/src/isa/x64/inst/external.rs | 2 -- cranelift/codegen/src/isa/x64/inst/mod.rs | 3 --- cranelift/codegen/src/isa/x64/inst/regs.rs | 3 --- cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs | 1 - cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs | 1 - cranelift/codegen/src/isa/x64/lower/isle.rs | 1 - cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 3 +-- cranelift/codegen/src/lib.rs | 4 +--- cranelift/codegen/src/machinst/abi.rs | 2 -- cranelift/codegen/src/machinst/buffer.rs | 6 ------ cranelift/codegen/src/machinst/inst_common.rs | 1 - cranelift/codegen/src/machinst/lower.rs | 6 ++---- cranelift/codegen/src/machinst/mod.rs | 1 - cranelift/codegen/src/machinst/reg.rs | 1 - cranelift/codegen/src/machinst/vcode.rs | 2 -- cranelift/codegen/src/opts.rs | 1 - cranelift/codegen/src/opts/generated_code.rs | 1 - cranelift/codegen/src/settings.rs | 1 - cranelift/codegen/src/souper_harvest.rs | 1 - cranelift/codegen/src/verifier/mod.rs | 1 - cranelift/codegen/src/write.rs | 1 - 106 files changed, 11 insertions(+), 154 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 592cea2b3635..fe35d822d676 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -550,7 +550,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,component-model && cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && - cargo check -p cranelift-assembler-x64 --no-default-features -F core && + cargo check -p cranelift-assembler-x64 --lib && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 6220a20e9068..e84ea6ae1e30 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -72,7 +72,7 @@ std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] # deprecated (we (i) always use hashbrown, and (ii) don't support a # no_std build anymore). The feature remains for backward # compatibility as a no-op. -core = ["cranelift-assembler-x64/core"] +core = [] # Enable the `to_capstone` method on TargetIsa, for constructing a Capstone # context, and the `disassemble` method on `MachBufferFinalized`. diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index f4c3fc30adad..eecb38096d1b 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,7 +61,6 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. -use crate::prelude::*; use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, @@ -401,4 +400,3 @@ fn get_ext_opcode(op: Opcode) -> Option { _ => Some(op), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ctxhash.rs b/cranelift/codegen/src/ctxhash.rs index 7148046ae9c1..ea7de766006e 100644 --- a/cranelift/codegen/src/ctxhash.rs +++ b/cranelift/codegen/src/ctxhash.rs @@ -6,7 +6,6 @@ use core::hash::{Hash, Hasher}; use hashbrown::hash_table::HashTable; -use core::hash::{Hash, Hasher}; /// Trait that allows for equality comparison given some external /// context. diff --git a/cranelift/codegen/src/data_value.rs b/cranelift/codegen/src/data_value.rs index 26a66d53694e..a2e69a724e1b 100644 --- a/cranelift/codegen/src/data_value.rs +++ b/cranelift/codegen/src/data_value.rs @@ -420,4 +420,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index b730b9a6107e..29e65a9ae806 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -772,4 +772,3 @@ mod tests { assert!(!dt.dominates(v3_def, block0, &cur.func.layout)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index 1ae2d260284f..b717fc32df4e 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -866,4 +866,3 @@ impl<'a> Elaborator<'a> { self.stats.elaborate_func_post_insts += self.func.dfg.num_insts() as u64; } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/egraph/mod.rs b/cranelift/codegen/src/egraph/mod.rs index 0e0ec49278f9..938f632bf892 100644 --- a/cranelift/codegen/src/egraph/mod.rs +++ b/cranelift/codegen/src/egraph/mod.rs @@ -1111,4 +1111,3 @@ pub(crate) struct Stats { pub(crate) elaborate_func_post_insts: u64, pub(crate) eclass_size_limit: u64, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/incremental_cache.rs b/cranelift/codegen/src/incremental_cache.rs index 973cca13ece1..a597d18869ce 100644 --- a/cranelift/codegen/src/incremental_cache.rs +++ b/cranelift/codegen/src/incremental_cache.rs @@ -239,4 +239,3 @@ pub fn try_finish_recompile(func: &Function, bytes: &[u8]) -> Result Err(RecompileError::Deserialize(err)), } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/inline.rs b/cranelift/codegen/src/inline.rs index 6e6756871545..ac150c598980 100644 --- a/cranelift/codegen/src/inline.rs +++ b/cranelift/codegen/src/inline.rs @@ -1584,4 +1584,3 @@ fn create_constants(allocs: &mut InliningAllocs, func: &mut ir::Function, callee allocs.constants[*callee_constant] = Some(inlined_constant).into(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/debug_tags.rs b/cranelift/codegen/src/ir/debug_tags.rs index d2ca049f6c53..39d137c2973b 100644 --- a/cranelift/codegen/src/ir/debug_tags.rs +++ b/cranelift/codegen/src/ir/debug_tags.rs @@ -139,4 +139,3 @@ impl core::fmt::Display for DebugTag { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/entities.rs b/cranelift/codegen/src/ir/entities.rs index a1ab10662d7d..cbb8f3097aff 100644 --- a/cranelift/codegen/src/ir/entities.rs +++ b/cranelift/codegen/src/ir/entities.rs @@ -562,4 +562,3 @@ mod tests { assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 08f1a7cb778e..f92ad688e565 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -288,4 +288,3 @@ impl<'a> Display for DisplayExceptionTable<'a> { Ok(()) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 35956406fb28..15af5a5ec20f 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -1,4 +1,3 @@ - //! Immediate operands for Cranelift instructions //! //! This module defines the types of immediate operands that can appear on Cranelift instructions. @@ -1961,4 +1960,3 @@ mod tests { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/layout.rs b/cranelift/codegen/src/ir/layout.rs index 2a2d139018fe..1284ab65676e 100644 --- a/cranelift/codegen/src/ir/layout.rs +++ b/cranelift/codegen/src/ir/layout.rs @@ -1193,4 +1193,3 @@ mod tests { assert_eq!(layout.pp_cmp(i3, i2), Ordering::Greater) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/pcc.rs b/cranelift/codegen/src/ir/pcc.rs index d1bf7ea62dba..8b9a3cc6bb6e 100644 --- a/cranelift/codegen/src/ir/pcc.rs +++ b/cranelift/codegen/src/ir/pcc.rs @@ -79,7 +79,6 @@ use crate::machinst::{BlockIndex, LowerBackend, VCode}; use crate::trace; use core::fmt; use regalloc2::Function as _; -use core::fmt; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 835a0ee3bafd..01bf2ff1a6ab 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -250,4 +250,3 @@ mod tests { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/trapcode.rs b/cranelift/codegen/src/ir/trapcode.rs index f990f312b94f..e3fbcfbb4a50 100644 --- a/cranelift/codegen/src/ir/trapcode.rs +++ b/cranelift/codegen/src/ir/trapcode.rs @@ -145,4 +145,3 @@ mod tests { assert_eq!("users".parse::(), Err(())); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/ir/types.rs b/cranelift/codegen/src/ir/types.rs index 48e98fd352d2..bc7704cf0662 100644 --- a/cranelift/codegen/src/ir/types.rs +++ b/cranelift/codegen/src/ir/types.rs @@ -622,4 +622,3 @@ mod tests { assert_eq!(Type::int_with_byte_size(evil), None); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index ea9710976388..78470852d4f2 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -18,7 +18,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because @@ -1632,4 +1631,3 @@ fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv { env } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs index d912aee4dd79..a382a5ef725a 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/args.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/args.rs @@ -724,4 +724,3 @@ impl TestBitAndBranchKind { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index b5bb377591df..06e0eb017708 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -3685,4 +3685,3 @@ fn emit_return_call_common_sequence( sink.put4(key.enc_auti_hint()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index fdca784dd038..d8e6cd6a2083 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -27,7 +27,7 @@ fn test_aarch64_binemit() { // // #!/bin/sh // tmp=`mktemp /tmp/XXXXXXXX.o` - // aarch64-linux-gnu-as /dev/corein -o $tmp + // aarch64-linux-gnu-as /dev/stdin -o $tmp // aarch64-linux-gnu-objdump -d $tmp // rm -f $tmp // @@ -7970,4 +7970,3 @@ fn test_cond_invert() { assert_eq!(cond.invert().invert(), cond); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index d72de5f39692..09aa838b8e82 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -1241,4 +1241,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 1021ddc6b90c..ead759b93028 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -15,8 +15,6 @@ use alloc::vec::Vec; use core::fmt::Write; use core::slice; use smallvec::{SmallVec, smallvec}; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub(crate) mod regs; pub(crate) use self::regs::*; @@ -3115,4 +3113,3 @@ mod tests { assert_eq!(expected, core::mem::size_of::()); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 5f1086252fbd..c9468f46e932 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -280,4 +280,3 @@ pub fn pretty_print_vreg_vector(reg: Reg, size: VectorSize) -> String { pub fn pretty_print_vreg_element(reg: Reg, idx: usize, size: ScalarSize) -> String { show_vreg_element(reg, idx as u8, size) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs index 25a095983c42..9378c46fa53b 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs @@ -175,4 +175,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs index 99c9f2f95592..6d51a380433f 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.rs +++ b/cranelift/codegen/src/isa/aarch64/lower.rs @@ -143,4 +143,3 @@ impl LowerBackend for AArch64Backend { type FactFlowState = pcc::FactFlowState; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index 6898f2852403..3e82af2a9c8e 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -35,8 +35,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::u32; use regalloc2::PReg; -use alloc::boxed::Box; -use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxCallIndInfo = Box>; @@ -860,4 +858,3 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> { self.backend.flags.is_pic() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 3867a060b7f3..2e0f7bd77dda 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -14,4 +14,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_aarch64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 703a0240036a..dafb6364f38d 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -17,7 +17,6 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Aarch64Architecture, Architecture, OperatingSystem, Triple}; // New backend: @@ -280,4 +279,3 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/pcc.rs b/cranelift/codegen/src/isa/aarch64/pcc.rs index 3b5e31d11c0e..e5ee1919803e 100644 --- a/cranelift/codegen/src/isa/aarch64/pcc.rs +++ b/cranelift/codegen/src/isa/aarch64/pcc.rs @@ -568,4 +568,3 @@ fn check_store_addr( let _output_fact = ctx.store(&fact, ty, None)?; Ok(()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/aarch64/settings.rs b/cranelift/codegen/src/isa/aarch64/settings.rs index 21031399b5eb..2cda69446ff3 100644 --- a/cranelift/codegen/src/isa/aarch64/settings.rs +++ b/cranelift/codegen/src/isa/aarch64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/arm64.rs`. include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index 2c44409de892..2bc2033983ef 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -50,7 +50,7 @@ use crate::CodegenResult; use crate::ir::{self, Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::{UnwindInfoKind, systemv::RegisterMappingError}; -use crate::machinst::{CompiledCodeStencil, TextSectionBuilder}; +use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder}; use crate::settings; use crate::settings::Configurable; use crate::settings::SetResult; @@ -499,4 +499,3 @@ impl Debug for &dyn TargetIsa { ) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley32.rs b/cranelift/codegen/src/isa/pulley32.rs index e3467275472e..b337274660d0 100644 --- a/cranelift/codegen/src/isa/pulley32.rs +++ b/cranelift/codegen/src/isa/pulley32.rs @@ -11,4 +11,3 @@ impl PulleyTargetKind for Pulley32 { PointerWidth::PointerWidth32 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley64.rs b/cranelift/codegen/src/isa/pulley64.rs index 234840c45eb5..31b1d08a04b2 100644 --- a/cranelift/codegen/src/isa/pulley64.rs +++ b/cranelift/codegen/src/isa/pulley64.rs @@ -11,4 +11,3 @@ impl PulleyTargetKind for Pulley64 { PointerWidth::PointerWidth64 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 44b8d350b971..780adddb3dcc 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,7 +15,6 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). @@ -985,4 +984,3 @@ fn create_reg_environment() -> MachineEnv { scratch_by_class: [None, None, None], } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs index 3520abec8d24..e97e3303ef99 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/args.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/args.rs @@ -6,7 +6,6 @@ use crate::machinst::abi::StackAMode; use core::fmt; use pulley_interpreter::encode; use pulley_interpreter::regs::Reg as _; -use core::fmt; /// A macro for defining a newtype of `Reg` that enforces some invariant about /// the wrapped `Reg` (such as that it is of a particular register class). @@ -780,4 +779,3 @@ impl fmt::Display for AddrG32Bne { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs index 25614218b03b..74082b4260c3 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/emit.rs @@ -707,4 +707,3 @@ fn patch_pc_rel_offset

( assert_eq!(*chunk, [0, 0, 0, 0]); *chunk = (end - start - 4).to_le_bytes(); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs index 497ba5e2031e..d76705a7fb9f 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/mod.rs @@ -952,4 +952,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs index 069050e7cd55..90f7d36e104b 100644 --- a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs +++ b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs @@ -162,4 +162,3 @@ define_registers! { v_reg(30) => v30, writable_v30; v_reg(31) => v31, writable_v31; } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.rs b/cranelift/codegen/src/isa/pulley_shared/lower.rs index b436d1d3e46e..8dd5a0cea50c 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower.rs @@ -34,4 +34,3 @@ where type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs index baa93a5eb1bc..d72b6a023789 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs @@ -327,4 +327,3 @@ where let mut isle_ctx = PulleyIsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs index 6b0853db8f25..45dd7050dc3c 100644 --- a/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/pulley_shared/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_pulley_shared.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/mod.rs b/cranelift/codegen/src/isa/pulley_shared/mod.rs index 8bcaa2eae62a..0b781e467a08 100644 --- a/cranelift/codegen/src/isa/pulley_shared/mod.rs +++ b/cranelift/codegen/src/isa/pulley_shared/mod.rs @@ -22,7 +22,6 @@ use alloc::vec::Vec; use core::fmt::Debug; use core::marker::PhantomData; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; pub use settings::Flags as PulleyFlags; @@ -313,4 +312,3 @@ impl PulleyFlags { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/pulley_shared/settings.rs b/cranelift/codegen/src/isa/pulley_shared/settings.rs index d611e3a6f2a5..5d4fd19ed116 100644 --- a/cranelift/codegen/src/isa/pulley_shared/settings.rs +++ b/cranelift/codegen/src/isa/pulley_shared/settings.rs @@ -14,4 +14,3 @@ use core::fmt; include!(concat!(env!("OUT_DIR"), "/settings-pulley.rs")); impl IsaFlags for Flags {} -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index 8b217e4ffd2f..e406c88ab1de 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -22,7 +22,6 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). @@ -1056,4 +1055,3 @@ impl Riscv64MachineDeps { insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32)); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs index d710f4348e46..918a4854b3a3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/args.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs @@ -1946,4 +1946,3 @@ impl ZcbMemOp { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 714271546539..5e631c3af1d3 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -2885,4 +2885,3 @@ fn return_call_emit_impl( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs index 09880464c68e..3b0cf59b633f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs @@ -2283,4 +2283,3 @@ fn riscv64_worst_case_instruction_size() { println!("calculate max size is {} , inst is {:?}", max.0, max.1); assert!(max.0 <= Inst::worst_case_size()); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/encode.rs b/cranelift/codegen/src/isa/riscv64/inst/encode.rs index b167f319ccfe..048fc2af05b5 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs @@ -718,4 +718,3 @@ pub fn encode_fp_rrrr( funct7, ) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs index 5e9f0faeee45..92a8ceb60b83 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs @@ -371,4 +371,3 @@ mod test { assert!(Inst::imm_min() == i32::MIN as i64 - 2048); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 0ba4fcc684cc..2addfd65b63a 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -19,9 +19,6 @@ use alloc::vec::Vec; use core::fmt::Write; use regalloc2::RegClass; use smallvec::{SmallVec, smallvec}; -use alloc::boxed::Box; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; @@ -1944,4 +1941,3 @@ mod test { assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/regs.rs b/cranelift/codegen/src/isa/riscv64/inst/regs.rs index d1e9fa7cd00f..76493732bfe1 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/regs.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/regs.rs @@ -151,4 +151,3 @@ pub const fn pf_reg(enc: usize) -> PReg { pub const fn pv_reg(enc: usize) -> PReg { PReg::new(enc, RegClass::Vector) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs index 0edc32ba221f..0b2ef040b19c 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs @@ -171,4 +171,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index add4cc872f16..0c8c49f8544b 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -1149,4 +1149,3 @@ pub trait VecInstOverlapInfo { self.forbids_src_dst_overlaps() || (mask.is_enabled() && self.forbids_mask_dst_overlaps()) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower.rs b/cranelift/codegen/src/isa/riscv64/lower.rs index 8de92855b2f8..117778f820b3 100644 --- a/cranelift/codegen/src/isa/riscv64/lower.rs +++ b/cranelift/codegen/src/isa/riscv64/lower.rs @@ -33,4 +33,3 @@ impl LowerBackend for Riscv64Backend { type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs index 6a8aed5eb907..a2a7d0c196e6 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs @@ -24,8 +24,6 @@ use crate::{ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::PReg; -use alloc::boxed::Box; -use alloc::vec::Vec; use wasmtime_math::{f32_cvt_to_int_bounds, f64_cvt_to_int_bounds}; type BoxCallInfo = Box>; @@ -751,4 +749,3 @@ pub(crate) fn lower_branch( let mut isle_ctx = RV64IsleContext::new(lower_ctx, backend); generated_code::constructor_lower_branch(&mut isle_ctx, branch, targets) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs index 9fb78bfb80ca..ad8466108a3b 100644 --- a/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/riscv64/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_riscv64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index ad9f3854a7bd..5affb19a8a65 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -18,7 +18,6 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; mod abi; pub(crate) mod inst; @@ -294,4 +293,3 @@ fn isa_constructor( let backend = Riscv64Backend::new_with_flags(triple, shared_flags, isa_flags); Ok(backend.wrapped()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/riscv64/settings.rs b/cranelift/codegen/src/isa/riscv64/settings.rs index f4ca3fb3a88a..c896dd5fe911 100644 --- a/cranelift/codegen/src/isa/riscv64/settings.rs +++ b/cranelift/codegen/src/isa/riscv64/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/riscv64/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-riscv64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 09d19fe54462..699cbba78890 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -149,7 +149,6 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use alloc::borrow::ToOwned; use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -1623,4 +1622,3 @@ fn tail_create_machine_env() -> MachineEnv { scratch_by_class: [None, None, None], } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/args.rs b/cranelift/codegen/src/isa/s390x/inst/args.rs index 5e114104b320..33e790673b61 100644 --- a/cranelift/codegen/src/isa/s390x/inst/args.rs +++ b/cranelift/codegen/src/isa/s390x/inst/args.rs @@ -269,4 +269,3 @@ impl PrettyPrint for Cond { s.to_string() } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index e218fe55454a..5baef0fede8a 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3559,4 +3559,3 @@ impl Inst { state.clear_post_insn(); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index aa4ab565eaef..569c16ac5c4d 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -13496,4 +13496,3 @@ fn test_s390x_binemit() { assert_eq!(expected_encoding, actual_encoding); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index edb66ba08196..9559f34ac7f8 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -200,4 +200,3 @@ impl PrettyPrint for UImm32Shifted { format!("{}", self.bits) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 1132b39b7b8a..e851ef4e6ffb 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -12,8 +12,6 @@ use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::Write; use smallvec::SmallVec; -use core::fmt::Write; -use alloc::string::{String, ToString}; pub mod regs; pub use self::regs::*; pub mod imms; @@ -3553,4 +3551,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index 438069a12c24..8b0205569b80 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -185,4 +185,3 @@ pub fn pretty_print_regpair_mod_lo(rd: WritableRegPair, ri: Reg) -> String { pub fn pretty_print_fpr(reg: Reg) -> (String, Option) { (show_reg(reg), maybe_show_fpr(reg)) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind.rs b/cranelift/codegen/src/isa/s390x/inst/unwind.rs index cb1a9ad16eb4..1e2bb904db74 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind.rs @@ -1,3 +1,2 @@ #[cfg(feature = "unwind")] pub(crate) mod systemv; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs index a37ca84767d9..6ae2c7e262d9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs @@ -216,4 +216,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index c111eee9c915..9af0b96147e5 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -28,4 +28,3 @@ impl LowerBackend for S390xBackend { type FactFlowState = (); } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index 56176476ecb8..561fabd9561e 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -27,9 +27,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use core::cell::Cell; use regalloc2::PReg; -use alloc::boxed::Box; -use core::cell::Cell; -use alloc::vec::Vec; type BoxCallInfo = Box>; type BoxReturnCallInfo = Box>; @@ -862,4 +859,3 @@ fn condcode_is_signed(cc: IntCC) -> bool { IntCC::UnsignedLessThan => false, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index c32fdefdc440..a6daad546b62 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -13,4 +13,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_s390x.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index c2905dcdfde2..b3f7986b9e8b 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -17,7 +17,6 @@ use alloc::string::String; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use cranelift_control::ControlPlane; -use alloc::string::String; use target_lexicon::{Architecture, Triple}; // New backend: @@ -238,4 +237,3 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { }, } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/s390x/settings.rs b/cranelift/codegen/src/isa/s390x/settings.rs index 16a717f9e7c7..5bf89030f19d 100644 --- a/cranelift/codegen/src/isa/s390x/settings.rs +++ b/cranelift/codegen/src/isa/s390x/settings.rs @@ -7,4 +7,3 @@ use core::fmt; // public `Flags` struct with an impl for all of the settings defined in // `cranelift/codegen/meta/src/isa/s390x/settings.rs`. include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind.rs b/cranelift/codegen/src/isa/unwind.rs index a2e47590f4d3..c9ea050fb28a 100644 --- a/cranelift/codegen/src/isa/unwind.rs +++ b/cranelift/codegen/src/isa/unwind.rs @@ -16,7 +16,6 @@ pub mod winarm64; #[cfg(feature = "unwind")] /// CFA-based unwind information used on SystemV. -#[cfg(feature = "unwind")] pub type CfaUnwindInfo = systemv::UnwindInfo; /// Expected unwind info type. diff --git a/cranelift/codegen/src/isa/unwind/systemv.rs b/cranelift/codegen/src/isa/unwind/systemv.rs index 0fb19d0408c7..5989e0b2a12b 100644 --- a/cranelift/codegen/src/isa/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/unwind/systemv.rs @@ -286,4 +286,3 @@ impl UnwindInfo { fde } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winarm64.rs b/cranelift/codegen/src/isa/unwind/winarm64.rs index 803867af2a85..3d3cdd8fcf48 100644 --- a/cranelift/codegen/src/isa/unwind/winarm64.rs +++ b/cranelift/codegen/src/isa/unwind/winarm64.rs @@ -315,4 +315,3 @@ pub(crate) fn create_unwind_info_from_insts( Ok(UnwindInfo { unwind_codes }) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/unwind/winx64.rs b/cranelift/codegen/src/isa/unwind/winx64.rs index e352dc6351df..38cb46b83b55 100644 --- a/cranelift/codegen/src/isa/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/unwind/winx64.rs @@ -310,4 +310,3 @@ fn ensure_unwind_offset(offset: u32) -> CodegenResult { } Ok(offset as u8) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 4d96e2056808..7ec39e608181 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -14,10 +14,10 @@ use alloc::borrow::ToOwned; use alloc::boxed::Box; use alloc::vec::Vec; use args::*; -use std::sync::OnceLock; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -1345,4 +1345,3 @@ fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv { env } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index c5e6a117ec04..233299966a16 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,8 +7,8 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use core::fmt; use alloc::string::String; +use core::fmt; /// An extension trait for converting `Writable{Xmm,Gpr}` to `Writable`. pub trait ToWritableReg { @@ -1061,4 +1061,3 @@ impl OperandSize { self.to_bytes() * 8 } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 7d9e7a6e7eba..1bd8b0f6b28e 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -2,7 +2,7 @@ //! //! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases. //! -//! to see coreout: cargo test -- --nocapture +//! to see stdout: cargo test -- --nocapture //! //! for this specific case, as of 24 Aug 2020: //! @@ -383,4 +383,3 @@ fn test_x64_emit() { assert_eq!(expected_encoding, actual_encoding, "{expected_printing}"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 3a3210e2cc2b..783f33414cb2 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -9,7 +9,6 @@ use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; use regalloc2::{PReg, RegClass}; -use alloc::string::String; /// Define the types of registers Cranelift will use. #[derive(Clone, Debug)] @@ -564,4 +563,3 @@ mod tests { assert_eq!(pair.to_string(None), "(%v500 <- %v400)"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 33d35ddd29ad..f6e0b02cb38a 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -19,8 +19,6 @@ use core::fmt::{self, Write}; use core::slice; use cranelift_assembler_x64 as asm; use smallvec::{SmallVec, smallvec}; -use core::fmt::{self, Write}; -use alloc::string::{String, ToString}; pub mod args; mod emit; @@ -1681,4 +1679,3 @@ impl MachInstLabelUse for LabelUse { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index fa68a12cc944..b1416e88df5c 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,12 +6,10 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; -use crate::prelude::*; use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; use regalloc2::{PReg, RegClass, VReg}; -use alloc::string::String; // Constructors for Regs. @@ -176,4 +174,3 @@ pub fn pretty_print_reg(reg: Reg, size: u8) -> String { name } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs index ecbe379cd7da..3f46843ab4f4 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs @@ -202,4 +202,3 @@ mod tests { func } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs index f6d80f5e531f..f848a5baf76f 100644 --- a/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs +++ b/cranelift/codegen/src/isa/x64/inst/unwind/winx64.rs @@ -14,4 +14,3 @@ impl crate::isa::unwind::winx64::RegisterMapper for RegisterMapper { } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle.rs b/cranelift/codegen/src/isa/x64/lower/isle.rs index 3917b4203ca5..57bfa06ee7fd 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle.rs @@ -1249,4 +1249,3 @@ const I8X16_USHR_MASKS: [u8; 128] = [ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ]; -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index 1bc434f23b5a..c48996ec46d6 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -14,4 +14,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_x64.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 5028c3b21bad..b4cc5467536a 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -10,7 +10,7 @@ use crate::isa::unwind::systemv; use crate::isa::x64::settings as x64_settings; use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey}; use crate::machinst::{ - CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, + CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; use crate::prelude::*; @@ -268,4 +268,3 @@ fn isa_constructor( let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags)?; Ok(backend.wrapped()) } -use crate::prelude::*; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 586dfd74b139..2ba4a4db5a4c 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -21,7 +21,7 @@ extern crate alloc; extern crate std; #[cfg(not(feature = "std"))] -use hashbrown::{HashMap, hash_map}; +use hashbrown::{HashMap, HashSet, hash_map}; #[cfg(feature = "std")] use std::collections::{HashMap, HashSet, hash_map}; @@ -50,8 +50,6 @@ mod prelude; #[macro_use] mod machinst; -mod prelude; - pub mod binemit; pub mod cfg_printer; pub mod cursor; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 35ce6223bd83..1474eac342a2 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -111,7 +111,6 @@ use crate::{ir, isa}; use crate::{machinst::*, trace}; use alloc::boxed::Box; use core::marker::PhantomData; -use hashbrown::HashMap; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::smallvec; @@ -2617,4 +2616,3 @@ mod tests { assert_eq!(core::mem::size_of::(), 24); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index dd295bf2d392..da95e541ff6b 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -190,11 +190,6 @@ use core::ops::Range; use cranelift_control::ControlPlane; use cranelift_entity::{PrimaryMap, SecondaryMap, entity_impl}; use smallvec::SmallVec; -use core::cmp::Ordering; -use alloc::collections::BinaryHeap; -use core::mem; -use alloc::string::String; -use alloc::vec::Vec; #[cfg(feature = "enable-serde")] use serde::{Deserialize, Serialize}; @@ -2916,4 +2911,3 @@ mod test { ); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/inst_common.rs b/cranelift/codegen/src/machinst/inst_common.rs index 1a15cde4e1fa..b077dd3b6112 100644 --- a/cranelift/codegen/src/machinst/inst_common.rs +++ b/cranelift/codegen/src/machinst/inst_common.rs @@ -14,4 +14,3 @@ pub struct InsnInput { pub(crate) insn: IRInst, pub(crate) input: usize, } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 76438cc3cacd..0dcc5170a97a 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -28,7 +28,6 @@ use alloc::vec::Vec; use core::fmt::Debug; use cranelift_control::ControlPlane; use smallvec::{SmallVec, smallvec}; -use core::fmt::Debug; use super::{VCodeBuildDirection, VRegAllocator}; @@ -40,7 +39,7 @@ pub type InstOutput = SmallVec<[ValueRegs; 2]>; /// any side-effecting op (for this purpose, loads are also considered /// side-effecting, to avoid subtle questions w.r.t. the memory model), and /// furthermore, it is guaranteed that for any two instructions A and B such -/// that color(A) == color(B), either A dominates B and B pocoreominates A, or +/// that color(A) == color(B), either A dominates B and B postdominates A, or /// vice-versa. (For now, in practice, only ops in the same basic block can ever /// have the same color, trivially providing the second condition.) Intuitively, /// this means that the ops of the same color must always execute "together", as @@ -1391,7 +1390,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { /// Instruction input/output queries. impl<'func, I: VCodeInst> Lower<'func, I> { - /// Get the incoreata for a given IR instruction. + /// Get the instdata for a given IR instruction. pub fn data(&self, ir_inst: Inst) -> &InstructionData { &self.f.dfg.insts[ir_inst] } @@ -1799,4 +1798,3 @@ mod tests { assert_eq!(uses[v5], ValueUseState::Unused); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 61ebb9bc0800..c327803d5fb3 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -60,7 +60,6 @@ use cranelift_control::ControlPlane; use cranelift_entity::PrimaryMap; use regalloc2::VReg; use smallvec::{SmallVec, smallvec}; -use alloc::string::String; #[cfg(feature = "enable-serde")] use serde_derive::{Deserialize, Serialize}; diff --git a/cranelift/codegen/src/machinst/reg.rs b/cranelift/codegen/src/machinst/reg.rs index 5d364601297d..dd28ee05f4c8 100644 --- a/cranelift/codegen/src/machinst/reg.rs +++ b/cranelift/codegen/src/machinst/reg.rs @@ -563,4 +563,3 @@ pub trait PrettyPrint { self.pretty_print(0) } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index ae142ec487a8..97c467ce212f 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -34,7 +34,6 @@ use regalloc2::{ use crate::HashMap; use crate::hash_map::Entry; - use core::cmp::Ordering; use core::fmt::{self, Write}; use core::mem::take; @@ -2062,4 +2061,3 @@ mod test { // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes. } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/opts.rs b/cranelift/codegen/src/opts.rs index 4ec9728f1e35..fc360913b1d9 100644 --- a/cranelift/codegen/src/opts.rs +++ b/cranelift/codegen/src/opts.rs @@ -18,7 +18,6 @@ use crate::trace; use core::marker::PhantomData; use cranelift_entity::packed_option::ReservedValue; use smallvec::{SmallVec, smallvec}; -use core::marker::PhantomData; pub type Unit = (); pub type ValueArray2 = [Value; 2]; diff --git a/cranelift/codegen/src/opts/generated_code.rs b/cranelift/codegen/src/opts/generated_code.rs index 2ff9eaef16bc..82208623362a 100644 --- a/cranelift/codegen/src/opts/generated_code.rs +++ b/cranelift/codegen/src/opts/generated_code.rs @@ -16,4 +16,3 @@ )] include!(concat!(env!("ISLE_DIR"), "/isle_opt.rs")); -use crate::prelude::*; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index cd54f5b9f356..90b835c0965a 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -567,4 +567,3 @@ enable_incremental_compilation_cache_checks = false assert_eq!(f.opt_level(), super::OptLevel::Speed); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/souper_harvest.rs b/cranelift/codegen/src/souper_harvest.rs index 5ea25882bae3..02958ed56a71 100644 --- a/cranelift/codegen/src/souper_harvest.rs +++ b/cranelift/codegen/src/souper_harvest.rs @@ -587,4 +587,3 @@ fn post_order_dfs( } } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 015ba58afe40..822d6e27ede0 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2315,4 +2315,3 @@ mod tests { assert_err_with_msg!(errors, "block0 cannot be empty"); } } -use crate::prelude::*; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index 6442ccbe3632..1961a57dfd9a 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -750,4 +750,3 @@ mod tests { ); } } -use crate::prelude::*; From 0d5919444f953b5a43ada61ddf4a6808d83c4598 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 08:56:34 +0100 Subject: [PATCH 46/61] add imports --- cranelift/codegen/src/alias_analysis.rs | 1 + cranelift/codegen/src/isa/x64/inst/args.rs | 1 + cranelift/codegen/src/isa/x64/inst/regs.rs | 1 + 3 files changed, 3 insertions(+) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index eecb38096d1b..ba141d235001 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,6 +61,7 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. +use crate::prelude::*; use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 233299966a16..1ac58c5f8872 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,6 +7,7 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; +use crate::prelude::*; use alloc::string::String; use core::fmt; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index b1416e88df5c..62a81a6dd722 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,6 +6,7 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; +use crate::prelude::*; use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; From 823dbba65650178688bda4ace077a02eeb4dfd2b Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 09:47:49 +0100 Subject: [PATCH 47/61] fix floating issues with libm --- cranelift/codegen/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index e84ea6ae1e30..33c3c3b90c51 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -66,7 +66,7 @@ default = ["std", "unwind", "host-arch", "timing"] # The "std" feature enables use of libstd. The "core" feature enables use # of some minimal std-like replacement libraries. At least one of these two # features need to be enabled. -std = ["serde?/std", "rustc-hash/std", "cranelift-control/fuzz"] +std = ["serde?/std", "rustc-hash/std", "gimli/std", "cranelift-control/fuzz"] # The "core" feature used to enable a hashmap workaround, but is now # deprecated (we (i) always use hashbrown, and (ii) don't support a From 1d8bcd24f4fbc9b706d5ad4d8a77d3c7e4cf8e09 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 12:16:25 +0100 Subject: [PATCH 48/61] temporarily remove OnceLock --- cranelift/codegen/src/isa/aarch64/abi.rs | 1 - cranelift/codegen/src/isa/pulley_shared/abi.rs | 1 - cranelift/codegen/src/isa/riscv64/abi.rs | 1 - cranelift/codegen/src/isa/s390x/abi.rs | 1 - cranelift/codegen/src/isa/x64/abi.rs | 1 - 5 files changed, 5 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 78470852d4f2..cb75d3082fb0 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -18,7 +18,6 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because // these ABIs are very similar. diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 780adddb3dcc..07a537b94127 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,7 +15,6 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). pub(crate) type PulleyCallee

= Callee>; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index e406c88ab1de..d1d12621dd5c 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -22,7 +22,6 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). pub(crate) type Riscv64Callee = Callee; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 699cbba78890..8c566ff24756 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -149,7 +149,6 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 7ec39e608181..2563083f917e 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -17,7 +17,6 @@ use args::*; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; -use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; From 9b01fa268ff77e41ad6eb4bb3ec1c3895c926954 Mon Sep 17 00:00:00 2001 From: SSD Date: Fri, 2 Jan 2026 12:44:44 +0100 Subject: [PATCH 49/61] add no_std arm support and add it into CI --- .github/workflows/main.yml | 1 + cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 + 2 files changed, 2 insertions(+) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index fe35d822d676..50e7d5bd599c 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -551,6 +551,7 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && cargo check -p cranelift-assembler-x64 --lib && + cargo check -p cranelift-codegen --no-default-features -F x86,arm64 && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 9559f34ac7f8..e114d9b022b0 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,6 +1,7 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; +use crate::prelude::*; use alloc::string::String; /// An unsigned 12-bit immediate. From 723f889d82cac8dd91d55f486272aa326879cbad Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 22:59:27 +0100 Subject: [PATCH 50/61] revert Cargo.toml formating --- Cargo.toml | 94 ++++++++++++------------------------------------------ 1 file changed, 20 insertions(+), 74 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index cf7a21011aea..cabc855044ac 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -50,10 +50,7 @@ wasmtime-cranelift = { workspace = true, optional = true } wasmtime-environ = { workspace = true } wasmtime-explorer = { workspace = true, optional = true } wasmtime-wast = { workspace = true, optional = true } -wasi-common = { workspace = true, default-features = true, features = [ - "exit", - "tokio", -], optional = true } +wasi-common = { workspace = true, default-features = true, features = ["exit", "tokio"], optional = true } wasmtime-wasi = { workspace = true, default-features = true, optional = true } wasmtime-wasi-nn = { workspace = true, optional = true } wasmtime-wasi-config = { workspace = true, optional = true } @@ -62,10 +59,7 @@ wasmtime-wasi-keyvalue = { workspace = true, optional = true } wasmtime-wasi-threads = { workspace = true, optional = true } wasmtime-wasi-http = { workspace = true, optional = true } wasmtime-unwinder = { workspace = true } -wasmtime-wizer = { workspace = true, optional = true, features = [ - 'clap', - 'wasmtime', -] } +wasmtime-wizer = { workspace = true, optional = true, features = ['clap', 'wasmtime'] } clap = { workspace = true } clap_complete = { workspace = true, optional = true } anyhow = { workspace = true, features = ['std'] } @@ -90,7 +84,7 @@ smallvec = { workspace = true } async-trait = { workspace = true } bytes = { workspace = true } cfg-if = { workspace = true } -tokio = { workspace = true, optional = true, features = ["signal", "macros"] } +tokio = { workspace = true, optional = true, features = [ "signal", "macros" ] } hyper = { workspace = true, optional = true } http = { workspace = true, optional = true } http-body-util = { workspace = true, optional = true } @@ -101,25 +95,12 @@ rustix = { workspace = true, features = ["mm", "process"] } [dev-dependencies] # depend again on wasmtime to activate its default features for tests -wasmtime = { workspace = true, features = [ - 'default', - 'winch', - 'pulley', - 'all-arch', - 'call-hook', - 'memory-protection-keys', - 'component-model-async', -] } +wasmtime = { workspace = true, features = ['default', 'winch', 'pulley', 'all-arch', 'call-hook', 'memory-protection-keys', 'component-model-async'] } env_logger = { workspace = true } log = { workspace = true } filecheck = { workspace = true } tempfile = { workspace = true } -tokio = { workspace = true, features = [ - "rt", - "time", - "macros", - "rt-multi-thread", -] } +tokio = { workspace = true, features = ["rt", "time", "macros", "rt-multi-thread"] } wast = { workspace = true } criterion = { workspace = true } num_cpus = "1.17.0" @@ -129,10 +110,7 @@ wat = { workspace = true } rayon = "1.5.0" wasmtime-wast = { workspace = true, features = ['component-model'] } wasmtime-component-util = { workspace = true } -wasmtime-test-util = { workspace = true, features = [ - 'wasmtime-wast', - 'component', -] } +wasmtime-test-util = { workspace = true, features = ['wasmtime-wast', 'component'] } bstr = "1.6.0" libc = { workspace = true } serde = { workspace = true } @@ -142,11 +120,7 @@ test-programs-artifacts = { workspace = true } bytesize = "2.0.1" wit-component = { workspace = true } cranelift-filetests = { workspace = true } -cranelift-codegen = { workspace = true, features = [ - "disas", - "trace-log", - "timing", -] } +cranelift-codegen = { workspace = true, features = ["disas", "trace-log", "timing"] } cranelift-reader = { workspace = true } toml = { workspace = true } similar = { workspace = true } @@ -206,7 +180,9 @@ members = [ "fuzz", "winch/codegen", ] -exclude = ['docs/rust_wasi_markdown_parser'] +exclude = [ + 'docs/rust_wasi_markdown_parser', +] [workspace.package] version = "42.0.0" @@ -367,9 +343,7 @@ wit-bindgen = { version = "0.50.0", default-features = false } wit-bindgen-rust-macro = { version = "0.50.0", default-features = false } # wasm-tools family: -wasmparser = { version = "0.243.0", default-features = false, features = [ - 'simd', -] } +wasmparser = { version = "0.243.0", default-features = false, features = ['simd'] } wat = "1.243.0" wast = "243.0.0" wasmprinter = "0.243.0" @@ -388,20 +362,14 @@ arbitrary = "1.4.2" backtrace = "0.3.75" mutatis = "0.3.2" cc = "1.2.41" -object = { version = "0.37.3", default-features = false, features = [ - 'read_core', - 'elf', -] } +object = { version = "0.37.3", default-features = false, features = ['read_core', 'elf'] } gimli = { version = "0.32.3", default-features = false, features = ['read'] } addr2line = { version = "0.25.1", default-features = false } anyhow = { version = "1.0.100", default-features = false } windows-sys = "0.61.2" env_logger = "0.11.5" log = { version = "0.4.28", default-features = false } -clap = { version = "4.5.48", default-features = false, features = [ - "std", - "derive", -] } +clap = { version = "4.5.48", default-features = false, features = ["std", "derive"] } clap_complete = "4.5.58" hashbrown = { version = "0.15", default-features = false } capstone = "0.13.0" @@ -430,7 +398,7 @@ tempfile = "3.23.0" filecheck = "0.5.0" libc = { version = "0.2.177", default-features = true } file-per-thread-logger = "0.2.0" -tokio = { version = "1.48.0", features = ["rt", "time"] } +tokio = { version = "1.48.0", features = [ "rt", "time" ] } hyper = "1.7.0" http = "1.3.1" http-body = "1.0.1" @@ -441,21 +409,11 @@ indexmap = { version = "2.11.4", default-features = false } syn = "2.0.106" quote = "1.0.41" proc-macro2 = "1.0.101" -test-log = { version = "0.2.18", default-features = false, features = [ - "trace", -] } -tracing-subscriber = { version = "0.3.20", default-features = false, features = [ - 'fmt', - 'env-filter', - 'ansi', - 'tracing-log', -] } +test-log = { version = "0.2.18", default-features = false, features = ["trace"] } +tracing-subscriber = { version = "0.3.20", default-features = false, features = ['fmt', 'env-filter', 'ansi', 'tracing-log'] } url = "2.5.7" postcard = { version = "1.1.3", default-features = false, features = ['alloc'] } -criterion = { version = "0.7.0", default-features = false, features = [ - "html_reports", - "rayon", -] } +criterion = { version = "0.7.0", default-features = false, features = ["html_reports", "rayon"] } rustc-hash = { version = "2.1.1", default-features = false } libtest-mimic = "0.8.1" semver = { version = "1.0.27", default-features = false } @@ -571,19 +529,10 @@ disable-logging = ["log/max_level_off", "tracing/max_level_off"] wasi-nn = ["dep:wasmtime-wasi-nn"] wasi-tls = ["dep:wasmtime-wasi-tls"] wasi-threads = ["dep:wasmtime-wasi-threads", "threads"] -wasi-http = [ - "component-model", - "dep:wasmtime-wasi-http", - "dep:tokio", - "dep:hyper", - "wasmtime-wasi-http/default-send-request", -] +wasi-http = ["component-model", "dep:wasmtime-wasi-http", "dep:tokio", "dep:hyper", "wasmtime-wasi-http/default-send-request"] wasi-config = ["dep:wasmtime-wasi-config"] wasi-keyvalue = ["dep:wasmtime-wasi-keyvalue"] -pooling-allocator = [ - "wasmtime/pooling-allocator", - "wasmtime-cli-flags/pooling-allocator", -] +pooling-allocator = ["wasmtime/pooling-allocator", "wasmtime-cli-flags/pooling-allocator"] component-model = [ "wasmtime/component-model", "wasmtime-wast?/component-model", @@ -605,10 +554,7 @@ gc = ["wasmtime-cli-flags/gc", "wasmtime/gc"] gc-drc = ["gc", "wasmtime/gc-drc", "wasmtime-cli-flags/gc-drc"] gc-null = ["gc", "wasmtime/gc-null", "wasmtime-cli-flags/gc-null"] pulley = ["wasmtime-cli-flags/pulley"] -stack-switching = [ - "wasmtime/stack-switching", - "wasmtime-cli-flags/stack-switching", -] +stack-switching = ["wasmtime/stack-switching", "wasmtime-cli-flags/stack-switching"] debug = ["wasmtime-cli-flags/debug", "wasmtime/debug"] # CLI subcommands for the `wasmtime` executable. See `wasmtime $cmd --help` From 39c067d4450d212a2758f8fb70f3123a8a643fb7 Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:09:28 +0100 Subject: [PATCH 51/61] remove prelude and fix cargo.toml --- Cargo.toml | 2 +- cranelift/codegen/src/alias_analysis.rs | 2 +- cranelift/codegen/src/dominator_tree.rs | 2 +- cranelift/codegen/src/egraph/elaborate.rs | 2 +- cranelift/codegen/src/egraph/mod.rs | 2 +- cranelift/codegen/src/ir/exception_table.rs | 2 +- cranelift/codegen/src/ir/immediates.rs | 2 +- cranelift/codegen/src/ir/stackslot.rs | 2 +- cranelift/codegen/src/isa/aarch64/abi.rs | 2 +- cranelift/codegen/src/isa/aarch64/inst/imms.rs | 2 +- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 2 +- cranelift/codegen/src/isa/aarch64/inst/regs.rs | 2 +- cranelift/codegen/src/isa/aarch64/mod.rs | 2 +- cranelift/codegen/src/isa/riscv64/abi.rs | 2 +- cranelift/codegen/src/isa/riscv64/inst/mod.rs | 2 +- cranelift/codegen/src/isa/riscv64/inst/vector.rs | 2 +- cranelift/codegen/src/isa/riscv64/mod.rs | 2 +- cranelift/codegen/src/isa/s390x/abi.rs | 2 +- cranelift/codegen/src/isa/s390x/inst/imms.rs | 2 +- cranelift/codegen/src/isa/s390x/inst/mod.rs | 2 +- cranelift/codegen/src/isa/s390x/inst/regs.rs | 2 +- cranelift/codegen/src/isa/s390x/mod.rs | 2 +- cranelift/codegen/src/isa/x64/abi.rs | 2 +- cranelift/codegen/src/isa/x64/inst/args.rs | 2 +- cranelift/codegen/src/isa/x64/inst/external.rs | 2 +- cranelift/codegen/src/isa/x64/inst/mod.rs | 2 +- cranelift/codegen/src/isa/x64/inst/regs.rs | 2 +- cranelift/codegen/src/isa/x64/mod.rs | 2 +- cranelift/codegen/src/lib.rs | 3 +-- cranelift/codegen/src/machinst/abi.rs | 2 +- cranelift/codegen/src/machinst/buffer.rs | 2 +- cranelift/codegen/src/machinst/lower.rs | 2 +- cranelift/codegen/src/machinst/vcode.rs | 2 +- cranelift/codegen/src/prelude.rs | 4 ---- cranelift/codegen/src/settings.rs | 2 +- cranelift/codegen/src/verifier/mod.rs | 2 +- cranelift/codegen/src/write.rs | 2 +- 37 files changed, 36 insertions(+), 41 deletions(-) delete mode 100644 cranelift/codegen/src/prelude.rs diff --git a/Cargo.toml b/Cargo.toml index cabc855044ac..c07e9cc8eb58 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -304,7 +304,7 @@ cranelift-jit = { path = "cranelift/jit", version = "0.129.0" } cranelift-fuzzgen = { path = "cranelift/fuzzgen" } cranelift-bforest = { path = "cranelift/bforest", version = "0.129.0" } cranelift-bitset = { path = "cranelift/bitset", version = "0.129.0" } -cranelift-control = { path = "cranelift/control", version = "0.129.0" } +cranelift-control = { path = "cranelift/control", version = "0.129.0", default-features = false } cranelift-srcgen = { path = "cranelift/srcgen", version = "0.129.0" } cranelift = { path = "cranelift/umbrella", version = "0.129.0" } diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index ba141d235001..1e7189f7158d 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,7 +61,7 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. -use crate::prelude::*; + use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 29e65a9ae806..38019a6cd192 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -4,7 +4,7 @@ use crate::entity::SecondaryMap; use crate::flowgraph::{BlockPredecessor, ControlFlowGraph}; use crate::ir::{Block, Function, Layout, ProgramPoint}; use crate::packed_option::PackedOption; -use crate::prelude::*; + use crate::timing; use alloc::vec::Vec; use core::cmp; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index b717fc32df4e..6be8264c4674 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -9,7 +9,7 @@ use crate::hash_map::Entry as HashEntry; use crate::inst_predicates::is_pure_for_egraph; use crate::ir::{Block, Function, Inst, Value, ValueDef}; use crate::loop_analysis::{Loop, LoopAnalysis}; -use crate::prelude::*; + use crate::scoped_hash_map::ScopedHashMap; use crate::trace; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/egraph/mod.rs b/cranelift/codegen/src/egraph/mod.rs index 938f632bf892..732e81e8623a 100644 --- a/cranelift/codegen/src/egraph/mod.rs +++ b/cranelift/codegen/src/egraph/mod.rs @@ -15,7 +15,7 @@ use crate::ir::{ use crate::loop_analysis::LoopAnalysis; use crate::opts::IsleContext; use crate::opts::generated_code::SkeletonInstSimplification; -use crate::prelude::*; + use crate::scoped_hash_map::{Entry as ScopedEntry, ScopedHashMap}; use crate::settings::Flags; use crate::take_and_replace::TakeAndReplace; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index f92ad688e565..28e9cb98b29b 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -19,7 +19,7 @@ use crate::ir::entities::{ExceptionTag, SigRef}; use crate::ir::instructions::ValueListPool; use crate::ir::{BlockCall, Value}; -use crate::prelude::*; + use alloc::vec::Vec; use core::fmt::{self, Display, Formatter}; #[cfg(feature = "enable-serde")] diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 15af5a5ec20f..a34f08e0979e 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -4,7 +4,7 @@ //! Each type here should have a corresponding definition in the //! `cranelift-codegen/meta/src/shared/immediates` crate in the meta language. -use crate::prelude::*; + use alloc::vec::Vec; use core::cmp::Ordering; use core::fmt::{self, Display, Formatter}; diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 01bf2ff1a6ab..36ac94f90ce0 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -6,7 +6,7 @@ use crate::entity::PrimaryMap; use crate::ir::StackSlot; use crate::ir::entities::{DynamicStackSlot, DynamicType}; -use crate::prelude::*; + use core::fmt; use core::str::FromStr; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index cb75d3082fb0..d21b54c77920 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -11,7 +11,7 @@ use crate::isa::aarch64::{inst::*, settings as aarch64_settings}; use crate::isa::unwind::UnwindInst; use crate::isa::winch; use crate::machinst::*; -use crate::prelude::*; + use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index 09aa838b8e82..673ee52f9e67 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -3,7 +3,7 @@ use crate::ir::types::*; use crate::isa::aarch64::inst::{OperandSize, ScalarSize}; use crate::machinst::PrettyPrint; -use crate::prelude::*; + use alloc::string::String; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index ead759b93028..981963717a99 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -5,7 +5,7 @@ use crate::ir::types::{F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128}; use crate::ir::{MemFlags, Type, types}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; -use crate::prelude::*; + use crate::{CodegenError, CodegenResult, settings}; use crate::machinst::{PrettyPrint, Reg, RegClass, Writable}; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index c9468f46e932..3ea43b775037 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -5,7 +5,7 @@ use crate::isa::aarch64::inst::ScalarSize; use crate::isa::aarch64::inst::VectorSize; use crate::machinst::RealReg; use crate::machinst::{Reg, RegClass, Writable}; -use crate::prelude::*; + use regalloc2::PReg; use regalloc2::VReg; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index dafb6364f38d..d9c03cf9caa0 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -10,7 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; -use crate::prelude::*; + use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index d1d12621dd5c..b80e07bbfb61 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -14,7 +14,7 @@ use crate::ir::LibCall; use crate::ir::Signature; use crate::isa::riscv64::settings::Flags as RiscvFlags; use crate::isa::unwind::UnwindInst; -use crate::prelude::*; + use crate::settings; use alloc::boxed::Box; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 2addfd65b63a..79c2d347e6d4 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -8,7 +8,7 @@ use crate::ir::types::{self, F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128 pub use crate::ir::{ExternalName, MemFlags, Type}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; -use crate::prelude::*; + use crate::{CodegenError, CodegenResult, settings}; pub use crate::ir::condcodes::FloatCC; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 0c8c49f8544b..459b25a73b4a 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -5,7 +5,7 @@ use crate::isa::riscv64::lower::isle::generated_code::{ VecElementWidth, VecLmul, VecMaskMode, VecOpCategory, VecOpMasking, VecTailMode, }; use crate::machinst::{OperandVisitor, RegClass}; -use crate::prelude::*; + use core::fmt; use super::{Type, UImm5}; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 5affb19a8a65..37e6d9eeca15 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -10,7 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; -use crate::prelude::*; + use crate::result::CodegenResult; use crate::settings::{self as shared_settings, Flags}; use crate::{CodegenError, ir}; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 8c566ff24756..1d3a6ccf43d3 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -143,7 +143,7 @@ use crate::isa; use crate::isa::s390x::{inst::*, settings as s390x_settings}; use crate::isa::unwind::UnwindInst; use crate::machinst::*; -use crate::prelude::*; + use crate::settings; use alloc::borrow::ToOwned; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index e114d9b022b0..63614505941b 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,7 +1,7 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; -use crate::prelude::*; + use alloc::string::String; /// An unsigned 12-bit immediate. diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index e851ef4e6ffb..57e46b5d9dc7 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -5,7 +5,7 @@ use crate::ir::{ExternalName, Type, types}; use crate::isa::s390x::abi::S390xMachineDeps; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; -use crate::prelude::*; + use crate::{CodegenError, CodegenResult, settings}; use alloc::boxed::Box; use alloc::string::{String, ToString}; diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index 8b0205569b80..5901094cf262 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -5,7 +5,7 @@ use regalloc2::PReg; use crate::isa::s390x::inst::{RegPair, WritableRegPair}; use crate::machinst::*; -use crate::prelude::*; + //============================================================================= // Registers, the Universe thereof, and printing diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index b3f7986b9e8b..b233a64c7b90 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -10,7 +10,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; -use crate::prelude::*; + use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 2563083f917e..c125ee8e0118 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -8,7 +8,7 @@ use crate::isa::winch; use crate::isa::{CallConv, unwind::UnwindInst, x64::inst::*, x64::settings as x64_settings}; use crate::machinst::abi::*; use crate::machinst::*; -use crate::prelude::*; + use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index 1ac58c5f8872..cb154136244e 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,7 +7,7 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; -use crate::prelude::*; + use alloc::string::String; use core::fmt; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 783f33414cb2..85c022528c74 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -4,7 +4,7 @@ use super::{ Amode, Gpr, Inst, LabelUse, MachBuffer, MachLabel, OperandVisitor, OperandVisitorImpl, SyntheticAmode, VCodeConstant, WritableGpr, WritableXmm, Xmm, args::FromWritableReg, }; -use crate::prelude::*; + use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index f6e0b02cb38a..8df433691136 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -8,7 +8,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::isa::x64::settings as x64_settings; use crate::isa::{CallConv, FunctionAlignment}; -use crate::prelude::*; + use crate::{CodegenError, CodegenResult, settings}; use crate::{machinst::*, trace}; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 62a81a6dd722..45cfc284c3f0 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,7 +6,7 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; -use crate::prelude::*; + use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index b4cc5467536a..a944d9d8688a 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -13,7 +13,7 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; -use crate::prelude::*; + use crate::result::{CodegenError, CodegenResult}; use crate::settings::{self as shared_settings, Flags}; use crate::{Final, MachBufferFinalized}; diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 2ba4a4db5a4c..485dad3bb687 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -14,6 +14,7 @@ allow(dead_code, reason = "see comment above") )] +#[macro_use] extern crate alloc; #[cfg(feature = "std")] @@ -45,8 +46,6 @@ pub use gimli; // Pull in generated the `isle_numerics_methods` macro. include!(concat!(env!("ISLE_DIR"), "/isle_numerics.rs")); -mod prelude; - #[macro_use] mod machinst; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 1474eac342a2..61c04057ae21 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -105,7 +105,7 @@ use crate::entity::SecondaryMap; use crate::ir::{ArgumentExtension, ArgumentPurpose, ExceptionTag, Signature}; use crate::ir::{StackSlotKey, types::*}; use crate::isa::TargetIsa; -use crate::prelude::*; + use crate::settings::ProbestackStrategy; use crate::{ir, isa}; use crate::{machinst::*, trace}; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index da95e541ff6b..4852c2374039 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -177,7 +177,7 @@ use crate::isa::unwind::UnwindInst; use crate::machinst::{ BlockIndex, MachInstLabelUse, TextSectionBuilder, VCodeConstant, VCodeConstants, VCodeInst, }; -use crate::prelude::*; + use crate::trace; use crate::{MachInstEmitState, ir}; use crate::{VCodeConstantData, timing}; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 0dcc5170a97a..bd308625d811 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -20,7 +20,7 @@ use crate::machinst::{ VCodeBuilder, VCodeConstant, VCodeConstantData, VCodeConstants, VCodeInst, ValueRegs, Writable, writable_value_regs, }; -use crate::prelude::*; + use crate::settings::Flags; use crate::{CodegenError, CodegenResult, trace}; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 97c467ce212f..17f2508273f0 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -21,7 +21,7 @@ use crate::CodegenError; use crate::FxHashMap; use crate::ir::pcc::*; use crate::ir::{self, Constant, ConstantData, ValueLabel, types}; -use crate::prelude::*; + use crate::ranges::Ranges; use crate::timing; use crate::trace; diff --git a/cranelift/codegen/src/prelude.rs b/cranelift/codegen/src/prelude.rs deleted file mode 100644 index 5dd5950bdf86..000000000000 --- a/cranelift/codegen/src/prelude.rs +++ /dev/null @@ -1,4 +0,0 @@ -pub use alloc::format; -pub use alloc::string::ToString; -pub use alloc::vec; - diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 90b835c0965a..3c9e07e21c57 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -22,7 +22,7 @@ use crate::constant_hash::{probe, simple_hash}; use crate::isa::TargetIsa; -use crate::prelude::*; + use alloc::boxed::Box; use alloc::string::{String, ToString}; use core::fmt; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 822d6e27ede0..2b1c1a52b440 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -77,7 +77,7 @@ use crate::ir::{ ValueList, types, }; use crate::isa::TargetIsa; -use crate::prelude::*; + use crate::print_errors::pretty_verifier_error; use crate::settings::FlagsOrIsa; use crate::timing; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index 1961a57dfd9a..6344ddee36c0 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -9,7 +9,7 @@ use crate::ir::immediates::Ieee128; use crate::ir::pcc::Fact; use crate::ir::{Block, DataFlowGraph, Function, Inst, Opcode, SigRef, Type, Value, ValueDef}; use crate::packed_option::ReservedValue; -use crate::prelude::*; + use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::{self, Write}; From 8179d2cc3f15c2bfa0f48a92095f40696171785d Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:10:13 +0100 Subject: [PATCH 52/61] cargo fmt --- cranelift/codegen/src/alias_analysis.rs | 1 - cranelift/codegen/src/ir/immediates.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/imms.rs | 1 - cranelift/codegen/src/isa/s390x/inst/regs.rs | 1 - 4 files changed, 4 deletions(-) diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs index 1e7189f7158d..eecb38096d1b 100644 --- a/cranelift/codegen/src/alias_analysis.rs +++ b/cranelift/codegen/src/alias_analysis.rs @@ -61,7 +61,6 @@ //! must be correct likely reduce the potential benefit, we don't yet //! do this. - use crate::{FxHashMap, FxHashSet}; use crate::{ cursor::{Cursor, FuncCursor}, diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index a34f08e0979e..b4ef38a7be30 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -4,7 +4,6 @@ //! Each type here should have a corresponding definition in the //! `cranelift-codegen/meta/src/shared/immediates` crate in the meta language. - use alloc::vec::Vec; use core::cmp::Ordering; use core::fmt::{self, Display, Formatter}; diff --git a/cranelift/codegen/src/isa/aarch64/inst/imms.rs b/cranelift/codegen/src/isa/aarch64/inst/imms.rs index 673ee52f9e67..fcd67deed576 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/imms.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/imms.rs @@ -4,7 +4,6 @@ use crate::ir::types::*; use crate::isa::aarch64::inst::{OperandSize, ScalarSize}; use crate::machinst::PrettyPrint; - use alloc::string::String; /// An immediate that represents the NZCV flags. diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index 5901094cf262..d3985bb9d20b 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -6,7 +6,6 @@ use regalloc2::PReg; use crate::isa::s390x::inst::{RegPair, WritableRegPair}; use crate::machinst::*; - //============================================================================= // Registers, the Universe thereof, and printing From 48e2bd3b311e62d17e7f45fe81dbbed8a517cb1d Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:29:31 +0100 Subject: [PATCH 53/61] remove empty lines --- cranelift/codegen/src/dominator_tree.rs | 1 - cranelift/codegen/src/egraph/elaborate.rs | 1 - cranelift/codegen/src/egraph/mod.rs | 1 - cranelift/codegen/src/ir/exception_table.rs | 1 - cranelift/codegen/src/ir/stackslot.rs | 1 - cranelift/codegen/src/isa/aarch64/abi.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/mod.rs | 1 - cranelift/codegen/src/isa/aarch64/inst/regs.rs | 1 - cranelift/codegen/src/isa/aarch64/mod.rs | 1 - cranelift/codegen/src/isa/riscv64/abi.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/mod.rs | 1 - cranelift/codegen/src/isa/riscv64/inst/vector.rs | 1 - cranelift/codegen/src/isa/riscv64/mod.rs | 1 - cranelift/codegen/src/isa/s390x/abi.rs | 1 - cranelift/codegen/src/isa/s390x/inst/imms.rs | 1 - cranelift/codegen/src/isa/s390x/inst/mod.rs | 1 - cranelift/codegen/src/isa/s390x/mod.rs | 1 - cranelift/codegen/src/isa/x64/abi.rs | 1 - cranelift/codegen/src/isa/x64/inst/args.rs | 1 - cranelift/codegen/src/isa/x64/inst/external.rs | 1 - cranelift/codegen/src/isa/x64/inst/mod.rs | 1 - cranelift/codegen/src/isa/x64/inst/regs.rs | 1 - cranelift/codegen/src/isa/x64/mod.rs | 1 - cranelift/codegen/src/machinst/abi.rs | 1 - cranelift/codegen/src/machinst/buffer.rs | 1 - cranelift/codegen/src/machinst/lower.rs | 1 - cranelift/codegen/src/machinst/vcode.rs | 1 - cranelift/codegen/src/settings.rs | 1 - cranelift/codegen/src/verifier/mod.rs | 1 - cranelift/codegen/src/write.rs | 1 - 30 files changed, 30 deletions(-) diff --git a/cranelift/codegen/src/dominator_tree.rs b/cranelift/codegen/src/dominator_tree.rs index 38019a6cd192..23d099a4251a 100644 --- a/cranelift/codegen/src/dominator_tree.rs +++ b/cranelift/codegen/src/dominator_tree.rs @@ -4,7 +4,6 @@ use crate::entity::SecondaryMap; use crate::flowgraph::{BlockPredecessor, ControlFlowGraph}; use crate::ir::{Block, Function, Layout, ProgramPoint}; use crate::packed_option::PackedOption; - use crate::timing; use alloc::vec::Vec; use core::cmp; diff --git a/cranelift/codegen/src/egraph/elaborate.rs b/cranelift/codegen/src/egraph/elaborate.rs index 6be8264c4674..86443e5cb126 100644 --- a/cranelift/codegen/src/egraph/elaborate.rs +++ b/cranelift/codegen/src/egraph/elaborate.rs @@ -9,7 +9,6 @@ use crate::hash_map::Entry as HashEntry; use crate::inst_predicates::is_pure_for_egraph; use crate::ir::{Block, Function, Inst, Value, ValueDef}; use crate::loop_analysis::{Loop, LoopAnalysis}; - use crate::scoped_hash_map::ScopedHashMap; use crate::trace; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/egraph/mod.rs b/cranelift/codegen/src/egraph/mod.rs index 732e81e8623a..280109470d01 100644 --- a/cranelift/codegen/src/egraph/mod.rs +++ b/cranelift/codegen/src/egraph/mod.rs @@ -15,7 +15,6 @@ use crate::ir::{ use crate::loop_analysis::LoopAnalysis; use crate::opts::IsleContext; use crate::opts::generated_code::SkeletonInstSimplification; - use crate::scoped_hash_map::{Entry as ScopedEntry, ScopedHashMap}; use crate::settings::Flags; use crate::take_and_replace::TakeAndReplace; diff --git a/cranelift/codegen/src/ir/exception_table.rs b/cranelift/codegen/src/ir/exception_table.rs index 28e9cb98b29b..4130f23792b4 100644 --- a/cranelift/codegen/src/ir/exception_table.rs +++ b/cranelift/codegen/src/ir/exception_table.rs @@ -19,7 +19,6 @@ use crate::ir::entities::{ExceptionTag, SigRef}; use crate::ir::instructions::ValueListPool; use crate::ir::{BlockCall, Value}; - use alloc::vec::Vec; use core::fmt::{self, Display, Formatter}; #[cfg(feature = "enable-serde")] diff --git a/cranelift/codegen/src/ir/stackslot.rs b/cranelift/codegen/src/ir/stackslot.rs index 36ac94f90ce0..1ad2a5d7d871 100644 --- a/cranelift/codegen/src/ir/stackslot.rs +++ b/cranelift/codegen/src/ir/stackslot.rs @@ -6,7 +6,6 @@ use crate::entity::PrimaryMap; use crate::ir::StackSlot; use crate::ir::entities::{DynamicStackSlot, DynamicType}; - use core::fmt; use core::str::FromStr; diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index d21b54c77920..68e23a6054d9 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -11,7 +11,6 @@ use crate::isa::aarch64::{inst::*, settings as aarch64_settings}; use crate::isa::unwind::UnwindInst; use crate::isa::winch; use crate::machinst::*; - use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 981963717a99..90ba2ef0c75d 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -5,7 +5,6 @@ use crate::ir::types::{F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128}; use crate::ir::{MemFlags, Type, types}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; - use crate::{CodegenError, CodegenResult, settings}; use crate::machinst::{PrettyPrint, Reg, RegClass, Writable}; diff --git a/cranelift/codegen/src/isa/aarch64/inst/regs.rs b/cranelift/codegen/src/isa/aarch64/inst/regs.rs index 3ea43b775037..7db69df4ebe4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/regs.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/regs.rs @@ -5,7 +5,6 @@ use crate::isa::aarch64::inst::ScalarSize; use crate::isa::aarch64::inst::VectorSize; use crate::machinst::RealReg; use crate::machinst::{Reg, RegClass, Writable}; - use regalloc2::PReg; use regalloc2::VReg; diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index d9c03cf9caa0..2f80ad9fa29b 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -10,7 +10,6 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; - use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index b80e07bbfb61..d8646010d2d0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -14,7 +14,6 @@ use crate::ir::LibCall; use crate::ir::Signature; use crate::isa::riscv64::settings::Flags as RiscvFlags; use crate::isa::unwind::UnwindInst; - use crate::settings; use alloc::boxed::Box; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 79c2d347e6d4..9349d64cd08f 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -8,7 +8,6 @@ use crate::ir::types::{self, F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128 pub use crate::ir::{ExternalName, MemFlags, Type}; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; - use crate::{CodegenError, CodegenResult, settings}; pub use crate::ir::condcodes::FloatCC; diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs index 459b25a73b4a..269e6481b506 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/vector.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/vector.rs @@ -5,7 +5,6 @@ use crate::isa::riscv64::lower::isle::generated_code::{ VecElementWidth, VecLmul, VecMaskMode, VecOpCategory, VecOpMasking, VecTailMode, }; use crate::machinst::{OperandVisitor, RegClass}; - use core::fmt; use super::{Type, UImm5}; diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 37e6d9eeca15..ca0a1a13e2e9 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -10,7 +10,6 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; - use crate::result::CodegenResult; use crate::settings::{self as shared_settings, Flags}; use crate::{CodegenError, ir}; diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 1d3a6ccf43d3..2c4c281d8051 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -143,7 +143,6 @@ use crate::isa; use crate::isa::s390x::{inst::*, settings as s390x_settings}; use crate::isa::unwind::UnwindInst; use crate::machinst::*; - use crate::settings; use alloc::borrow::ToOwned; use alloc::vec::Vec; diff --git a/cranelift/codegen/src/isa/s390x/inst/imms.rs b/cranelift/codegen/src/isa/s390x/inst/imms.rs index 63614505941b..9559f34ac7f8 100644 --- a/cranelift/codegen/src/isa/s390x/inst/imms.rs +++ b/cranelift/codegen/src/isa/s390x/inst/imms.rs @@ -1,7 +1,6 @@ //! S390x ISA definitions: immediate constants. use crate::machinst::PrettyPrint; - use alloc::string::String; /// An unsigned 12-bit immediate. diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 57e46b5d9dc7..9528ba5cb376 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -5,7 +5,6 @@ use crate::ir::{ExternalName, Type, types}; use crate::isa::s390x::abi::S390xMachineDeps; use crate::isa::{CallConv, FunctionAlignment}; use crate::machinst::*; - use crate::{CodegenError, CodegenResult, settings}; use alloc::boxed::Box; use alloc::string::{String, ToString}; diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index b233a64c7b90..6bc40484153d 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -10,7 +10,6 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; - use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::string::String; diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index c125ee8e0118..562b60510410 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -8,7 +8,6 @@ use crate::isa::winch; use crate::isa::{CallConv, unwind::UnwindInst, x64::inst::*, x64::settings as x64_settings}; use crate::machinst::abi::*; use crate::machinst::*; - use crate::settings; use alloc::borrow::ToOwned; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs index cb154136244e..233299966a16 100644 --- a/cranelift/codegen/src/isa/x64/inst/args.rs +++ b/cranelift/codegen/src/isa/x64/inst/args.rs @@ -7,7 +7,6 @@ use crate::ir::types::*; use crate::isa::x64::inst::Inst; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::machinst::*; - use alloc::string::String; use core::fmt; diff --git a/cranelift/codegen/src/isa/x64/inst/external.rs b/cranelift/codegen/src/isa/x64/inst/external.rs index 85c022528c74..8d41f2e6d484 100644 --- a/cranelift/codegen/src/isa/x64/inst/external.rs +++ b/cranelift/codegen/src/isa/x64/inst/external.rs @@ -4,7 +4,6 @@ use super::{ Amode, Gpr, Inst, LabelUse, MachBuffer, MachLabel, OperandVisitor, OperandVisitorImpl, SyntheticAmode, VCodeConstant, WritableGpr, WritableXmm, Xmm, args::FromWritableReg, }; - use crate::{Reg, Writable, ir::TrapCode}; use alloc::string::String; use cranelift_assembler_x64 as asm; diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 8df433691136..8bff031e3fc4 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -8,7 +8,6 @@ use crate::isa::x64::abi::X64ABIMachineSpec; use crate::isa::x64::inst::regs::pretty_print_reg; use crate::isa::x64::settings as x64_settings; use crate::isa::{CallConv, FunctionAlignment}; - use crate::{CodegenError, CodegenResult, settings}; use crate::{machinst::*, trace}; use alloc::boxed::Box; diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs index 45cfc284c3f0..b1416e88df5c 100644 --- a/cranelift/codegen/src/isa/x64/inst/regs.rs +++ b/cranelift/codegen/src/isa/x64/inst/regs.rs @@ -6,7 +6,6 @@ //! Note also that we make use of pinned VRegs to refer to PRegs. use crate::machinst::Reg; - use alloc::string::String; use alloc::string::ToString; use cranelift_assembler_x64::{gpr, xmm}; diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index a944d9d8688a..2559a97b6863 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -13,7 +13,6 @@ use crate::machinst::{ CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode, compile, }; - use crate::result::{CodegenError, CodegenResult}; use crate::settings::{self as shared_settings, Flags}; use crate::{Final, MachBufferFinalized}; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 61c04057ae21..0ec7befe1e55 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -105,7 +105,6 @@ use crate::entity::SecondaryMap; use crate::ir::{ArgumentExtension, ArgumentPurpose, ExceptionTag, Signature}; use crate::ir::{StackSlotKey, types::*}; use crate::isa::TargetIsa; - use crate::settings::ProbestackStrategy; use crate::{ir, isa}; use crate::{machinst::*, trace}; diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index 4852c2374039..abd5396178db 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -177,7 +177,6 @@ use crate::isa::unwind::UnwindInst; use crate::machinst::{ BlockIndex, MachInstLabelUse, TextSectionBuilder, VCodeConstant, VCodeConstants, VCodeInst, }; - use crate::trace; use crate::{MachInstEmitState, ir}; use crate::{VCodeConstantData, timing}; diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index bd308625d811..c3ce9fa9c96c 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -20,7 +20,6 @@ use crate::machinst::{ VCodeBuilder, VCodeConstant, VCodeConstantData, VCodeConstants, VCodeInst, ValueRegs, Writable, writable_value_regs, }; - use crate::settings::Flags; use crate::{CodegenError, CodegenResult, trace}; use crate::{FxHashMap, FxHashSet}; diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 17f2508273f0..8c253b9aa26f 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -21,7 +21,6 @@ use crate::CodegenError; use crate::FxHashMap; use crate::ir::pcc::*; use crate::ir::{self, Constant, ConstantData, ValueLabel, types}; - use crate::ranges::Ranges; use crate::timing; use crate::trace; diff --git a/cranelift/codegen/src/settings.rs b/cranelift/codegen/src/settings.rs index 3c9e07e21c57..158ba139bd42 100644 --- a/cranelift/codegen/src/settings.rs +++ b/cranelift/codegen/src/settings.rs @@ -22,7 +22,6 @@ use crate::constant_hash::{probe, simple_hash}; use crate::isa::TargetIsa; - use alloc::boxed::Box; use alloc::string::{String, ToString}; use core::fmt; diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 2b1c1a52b440..304c3ebb202f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -77,7 +77,6 @@ use crate::ir::{ ValueList, types, }; use crate::isa::TargetIsa; - use crate::print_errors::pretty_verifier_error; use crate::settings::FlagsOrIsa; use crate::timing; diff --git a/cranelift/codegen/src/write.rs b/cranelift/codegen/src/write.rs index 6344ddee36c0..c0025aa6fca3 100644 --- a/cranelift/codegen/src/write.rs +++ b/cranelift/codegen/src/write.rs @@ -9,7 +9,6 @@ use crate::ir::immediates::Ieee128; use crate::ir::pcc::Fact; use crate::ir::{Block, DataFlowGraph, Function, Inst, Opcode, SigRef, Type, Value, ValueDef}; use crate::packed_option::ReservedValue; - use alloc::string::{String, ToString}; use alloc::vec::Vec; use core::fmt::{self, Write}; From cea863f52884109ae3d9c0a903a62fbacfcbeb5f Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:32:18 +0100 Subject: [PATCH 54/61] bad renames --- .../codegen/src/isa/s390x/inst/emit_tests.rs | 16 ++++++++-------- cranelift/codegen/src/isa/s390x/inst/mod.rs | 2 +- cranelift/codegen/src/machinst/isle.rs | 2 +- cranelift/codegen/src/verifier/mod.rs | 4 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index 569c16ac5c4d..aa6f9e6b19c9 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -12039,7 +12039,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102000", - "core %f1, 0(%r2)", + "std %f1, 0(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12054,7 +12054,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60102FFF", - "core %f1, 4095(%r2)", + "std %f1, 4095(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12069,7 +12069,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1020008067", - "corey %f1, -524288(%r2)", + "stdy %f1, -524288(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12084,7 +12084,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED102FFF7F67", - "corey %f1, 524287(%r2)", + "stdy %f1, 524287(%r2)", )); insns.push(( Inst::VecStoreLane { @@ -12129,7 +12129,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123000", - "core %f1, 0(%r2,%r3)", + "std %f1, 0(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12144,7 +12144,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "60123FFF", - "core %f1, 4095(%r2,%r3)", + "std %f1, 4095(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12159,7 +12159,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED1230008067", - "corey %f1, -524288(%r2,%r3)", + "stdy %f1, -524288(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { @@ -12174,7 +12174,7 @@ fn test_s390x_binemit() { lane_imm: 0, }, "ED123FFF7F67", - "corey %f1, 524287(%r2,%r3)", + "stdy %f1, 524287(%r2,%r3)", )); insns.push(( Inst::VecStoreLane { diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 9528ba5cb376..762f6c58d27e 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -2968,7 +2968,7 @@ impl Inst { (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None), (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None), (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")), - (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("core"), Some("corey")), + (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")), (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None), (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None), (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None), diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index 8a64fab294f3..f73ede5b257b 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -641,7 +641,7 @@ macro_rules! isle_lower_prelude_methods { et: ExceptionTable, labels: &MachLabelSlice, ) -> OptionTryCallInfo { - let mut exception_handlers = alloc::vec![]; + let mut exception_handlers = vec![]; let mut labels = labels.iter().cloned(); for item in self.lower_ctx.dfg().exception_tables[et].clone().items() { match item { diff --git a/cranelift/codegen/src/verifier/mod.rs b/cranelift/codegen/src/verifier/mod.rs index 304c3ebb202f..c57846c59c1f 100644 --- a/cranelift/codegen/src/verifier/mod.rs +++ b/cranelift/codegen/src/verifier/mod.rs @@ -2130,9 +2130,9 @@ mod tests { None => panic!("Expected an error"), Some(&VerifierError { ref message, .. }) => { if !message.contains($msg) { - #[cfg(feature = "core")] + #[cfg(feature = "std")] panic!("'{}' did not contain the substring '{}'", message, $msg); - #[cfg(not(feature = "core"))] + #[cfg(not(feature = "std"))] panic!("error message did not contain the expected substring"); } } From 4436bbf54d2fbcb3e7489b9259a50c91d30f1b72 Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:44:02 +0100 Subject: [PATCH 55/61] macro_use only on no_std --- cranelift/codegen/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cranelift/codegen/src/lib.rs b/cranelift/codegen/src/lib.rs index 485dad3bb687..1cfb95c1f204 100644 --- a/cranelift/codegen/src/lib.rs +++ b/cranelift/codegen/src/lib.rs @@ -14,7 +14,7 @@ allow(dead_code, reason = "see comment above") )] -#[macro_use] +#[cfg_attr(not(feature = "std"), macro_use)] extern crate alloc; #[cfg(feature = "std")] From 6eae76cf2cecb9cafe4c92e058e8b6234b9aa635 Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:51:27 +0100 Subject: [PATCH 56/61] revert OnceLock change --- .github/workflows/main.yml | 1 - cranelift/codegen/src/isa/aarch64/abi.rs | 9 ++++++--- cranelift/codegen/src/isa/pulley_shared/abi.rs | 6 ++++-- cranelift/codegen/src/isa/riscv64/abi.rs | 6 ++++-- cranelift/codegen/src/isa/s390x/abi.rs | 13 ++++++++++--- cranelift/codegen/src/isa/x64/abi.rs | 9 ++++++--- cranelift/codegen/src/machinst/abi.rs | 4 ++-- cranelift/codegen/src/machinst/compile.rs | 5 ++--- cranelift/codegen/src/machinst/vcode.rs | 2 +- 9 files changed, 35 insertions(+), 20 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 50e7d5bd599c..fe35d822d676 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -551,7 +551,6 @@ jobs: cargo check -p wasmtime --no-default-features --features runtime,gc,component-model,async,debug-builtins && cargo check -p cranelift-control --no-default-features && cargo check -p cranelift-assembler-x64 --lib && - cargo check -p cranelift-codegen --no-default-features -F x86,arm64 && cargo check -p pulley-interpreter --features encode,decode,disas,interp && cargo check -p wasmtime-wasi-io --no-default-features # Use `cross` for illumos to have a C compiler/linker available. diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index 68e23a6054d9..8f1afce63a87 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -17,6 +17,7 @@ use alloc::boxed::Box; use alloc::vec::Vec; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; // We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because // these ABIs are very similar. @@ -1086,11 +1087,13 @@ impl ABIMachineSpec for AArch64MachineDeps { } } - fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { + fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { if flags.enable_pinned_reg() { - create_reg_env(true) + static MACHINE_ENV: OnceLock = OnceLock::new(); + MACHINE_ENV.get_or_init(|| create_reg_env(true)) } else { - create_reg_env(false) + static MACHINE_ENV: OnceLock = OnceLock::new(); + MACHINE_ENV.get_or_init(|| create_reg_env(false)) } } diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs index 07a537b94127..de32099a14a7 100644 --- a/cranelift/codegen/src/isa/pulley_shared/abi.rs +++ b/cranelift/codegen/src/isa/pulley_shared/abi.rs @@ -15,6 +15,7 @@ use core::marker::PhantomData; use cranelift_bitset::ScalarBitSet; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; /// Support for the Pulley ABI from the callee side (within a function body). pub(crate) type PulleyCallee

= Callee>; @@ -473,8 +474,9 @@ where } } - fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { - create_reg_environment() + fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { + static MACHINE_ENV: OnceLock = OnceLock::new(); + MACHINE_ENV.get_or_init(create_reg_environment) } fn get_regs_clobbered_by_call( diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index d8646010d2d0..f53eee9a53a0 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -21,6 +21,7 @@ use regalloc2::{MachineEnv, PReg, PRegSet}; use alloc::borrow::ToOwned; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; /// Support for the Riscv64 ABI from the callee side (within a function body). pub(crate) type Riscv64Callee = Callee; @@ -611,8 +612,9 @@ impl ABIMachineSpec for Riscv64MachineDeps { } } - fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { - create_reg_environment() + fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { + static MACHINE_ENV: OnceLock = OnceLock::new(); + MACHINE_ENV.get_or_init(create_reg_environment) } fn get_regs_clobbered_by_call( diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 2c4c281d8051..738e037047d3 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -148,6 +148,7 @@ use alloc::borrow::ToOwned; use alloc::vec::Vec; use regalloc2::{MachineEnv, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; // We use a generic implementation that factors out ABI commonalities. @@ -903,10 +904,16 @@ impl ABIMachineSpec for S390xMachineDeps { } } - fn get_machine_env(_flags: &settings::Flags, call_conv: isa::CallConv) -> MachineEnv { + fn get_machine_env(_flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv { match call_conv { - isa::CallConv::Tail => tail_create_machine_env(), - _ => sysv_create_machine_env(), + isa::CallConv::Tail => { + static TAIL_MACHINE_ENV: OnceLock = OnceLock::new(); + TAIL_MACHINE_ENV.get_or_init(tail_create_machine_env) + } + _ => { + static SYSV_MACHINE_ENV: OnceLock = OnceLock::new(); + SYSV_MACHINE_ENV.get_or_init(sysv_create_machine_env) + } } } diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 562b60510410..b3a8dfed44a0 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -16,6 +16,7 @@ use args::*; use cranelift_assembler_x64 as asm; use regalloc2::{MachineEnv, PReg, PRegSet}; use smallvec::{SmallVec, smallvec}; +use std::sync::OnceLock; /// Support for the x64 ABI from the callee side (within a function body). pub(crate) type X64Callee = Callee; @@ -872,11 +873,13 @@ impl ABIMachineSpec for X64ABIMachineSpec { } } - fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> MachineEnv { + fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv { if flags.enable_pinned_reg() { - create_reg_env_systemv(true) + static MACHINE_ENV: OnceLock = OnceLock::new(); + MACHINE_ENV.get_or_init(|| create_reg_env_systemv(true)) } else { - create_reg_env_systemv(false) + static MACHINE_ENV: OnceLock = OnceLock::new(); + MACHINE_ENV.get_or_init(|| create_reg_env_systemv(false)) } } diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 0ec7befe1e55..08f275ccca76 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -574,7 +574,7 @@ pub trait ABIMachineSpec { ) -> u32; /// Get the ABI-dependent MachineEnv for managing register allocation. - fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> MachineEnv; + fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv; /// Get all caller-save registers, that is, registers that we expect /// not to be saved across a call to a callee with the given ABI. @@ -1539,7 +1539,7 @@ impl Callee { } /// Get the ABI-dependent MachineEnv for managing register allocation. - pub fn machine_env(&self) -> MachineEnv { + pub fn machine_env(&self) -> &MachineEnv { M::get_machine_env(&self.flags, self.call_conv) } diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index 9c7d2d55bd26..84c68b337498 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -69,7 +69,7 @@ pub fn compile( RegallocAlgorithm::SinglePass => Algorithm::Fastalloc, }; - regalloc2::run(&vcode, &vcode.abi.machine_env(), &options) + regalloc2::run(&vcode, vcode.abi.machine_env(), &options) .map_err(|err| { log::error!( "Register allocation error for vcode\n{vcode:?}\nError: {err:?}\nCLIF for error:\n{f:?}", @@ -82,8 +82,7 @@ pub fn compile( // Run the regalloc checker, if requested. if b.flags().regalloc_checker() { let _tt = timing::regalloc_checker(); - let machine_env = vcode.abi.machine_env(); - let mut checker = regalloc2::checker::Checker::new(&vcode, &machine_env); + let mut checker = regalloc2::checker::Checker::new(&vcode, &vcode.abi.machine_env()); checker.prepare(®alloc_result); checker .run() diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 8c253b9aa26f..97f533c42ea1 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -515,7 +515,7 @@ impl VCodeBuilder { } fn collect_operands(&mut self, vregs: &VRegAllocator) { - let allocatable = PRegSet::from(&self.vcode.abi.machine_env()); + let allocatable = PRegSet::from(self.vcode.abi.machine_env()); for (i, insn) in self.vcode.insts.iter_mut().enumerate() { // Push operands from the instruction onto the operand list. // From 9b1b89d88d85e2cb36736d6cb13ddaf4f4280b2d Mon Sep 17 00:00:00 2001 From: SSD Date: Mon, 5 Jan 2026 23:58:40 +0100 Subject: [PATCH 57/61] only use stable libm features --- cranelift/codegen/Cargo.toml | 2 +- cranelift/codegen/src/ir/immediates.rs | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 33c3c3b90c51..e8cbe564d03a 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -44,7 +44,7 @@ souper-ir = { version = "2.1.0", optional = true } sha2 = { version = "0.10.2", optional = true } rustc-hash = { workspace = true } wasmtime-math = { workspace = true } -libm = { workspace = true, features = ["unstable-public-internals"] } +libm = { workspace = true } # It is a goal of the cranelift-codegen crate to have minimal external dependencies. # Please don't add any unless they are essential to the task of creating binary # machine code. Integration tests that need external dependencies can be diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index b4ef38a7be30..101f88704a5e 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -704,7 +704,8 @@ macro_rules! ieee_float { /// Returns the nearest integer to `self`. Rounds half-way cases to the number /// with an even least significant digit. pub fn round_ties_even(self) -> Self { - Self::with_float(libm::generic::rint_round(self.$as_float(), libm::support::Round::Nearest).val) + // TODO: when libm v0.2.16 is published Libm::roundeven can be used + Self::with_float(self.$as_float().round_ties_even()) } )? } From 0f752f34bda5e3fb649d53ae181f8f6acf8bbd0c Mon Sep 17 00:00:00 2001 From: SSD Date: Wed, 7 Jan 2026 15:03:40 +0100 Subject: [PATCH 58/61] update regalloc2 --- Cargo.lock | 4 ++-- Cargo.toml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index f97890490b3a..9bb699ba1be9 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2989,9 +2989,9 @@ dependencies = [ [[package]] name = "regalloc2" -version = "0.13.3" +version = "0.13.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4e249c660440317032a71ddac302f25f1d5dff387667bcc3978d1f77aa31ac34" +checksum = "919cc500365f55230d2e2230cb813dd7c6fa5f907ad332d83ad3b862112cb69e" dependencies = [ "allocator-api2", "bumpalo", diff --git a/Cargo.toml b/Cargo.toml index c07e9cc8eb58..bfdf50d019b7 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -322,7 +322,7 @@ component-async-tests = { path = "crates/misc/component-async-tests" } # Bytecode Alliance maintained dependencies: # --------------------------- -regalloc2 = { version = "0.13.3", default-features = false } +regalloc2 = "0.13.4" wasip1 = { version = "1.0.0", default-features = false } # cap-std family: From 4355ea8dd40390eee41d10f4609b51c9f560ca9e Mon Sep 17 00:00:00 2001 From: SSD Date: Wed, 7 Jan 2026 15:06:30 +0100 Subject: [PATCH 59/61] update comment --- cranelift/codegen/src/ir/immediates.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cranelift/codegen/src/ir/immediates.rs b/cranelift/codegen/src/ir/immediates.rs index 101f88704a5e..6eb30974edc1 100644 --- a/cranelift/codegen/src/ir/immediates.rs +++ b/cranelift/codegen/src/ir/immediates.rs @@ -704,7 +704,8 @@ macro_rules! ieee_float { /// Returns the nearest integer to `self`. Rounds half-way cases to the number /// with an even least significant digit. pub fn round_ties_even(self) -> Self { - // TODO: when libm v0.2.16 is published Libm::roundeven can be used + // TODO: when libm v0.2.16 is published line below can be used instead + // Self::with_float(Libm::<$float_ty>::roundeven(self.$as_float())) Self::with_float(self.$as_float().round_ties_even()) } )? From e459e069856fbaa0975e094a9664cedd1d1756e7 Mon Sep 17 00:00:00 2001 From: SSD Date: Wed, 7 Jan 2026 15:14:30 +0100 Subject: [PATCH 60/61] use continue instead --- cranelift/codegen/src/machinst/vcode.rs | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 97f533c42ea1..5a1aa71b9761 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -1274,18 +1274,21 @@ impl VCode { let loc = if let Some(preg) = alloc.as_reg() { LabelValueLoc::Reg(Reg::from(preg)) } else { - let slot = alloc.as_stack().unwrap(); - let slot_offset = self.abi.get_spillslot_offset(slot); - let slot_base_to_caller_sp_offset = self.abi.slot_base_to_caller_sp_offset(); #[cfg(not(feature = "unwind"))] - let caller_sp_to_cfa_offset = 0; + continue; + #[cfg(feature = "unwind")] - let caller_sp_to_cfa_offset = - crate::isa::unwind::systemv::caller_sp_to_cfa_offset(); - // NOTE: this is a negative offset because it's relative to the caller's SP - let cfa_to_sp_offset = - -((slot_base_to_caller_sp_offset + caller_sp_to_cfa_offset) as i64); - LabelValueLoc::CFAOffset(cfa_to_sp_offset + slot_offset) + { + let slot = alloc.as_stack().unwrap(); + let slot_offset = self.abi.get_spillslot_offset(slot); + let slot_base_to_caller_sp_offset = self.abi.slot_base_to_caller_sp_offset(); + let caller_sp_to_cfa_offset = + crate::isa::unwind::systemv::caller_sp_to_cfa_offset(); + // NOTE: this is a negative offset because it's relative to the caller's SP + let cfa_to_sp_offset = + -((slot_base_to_caller_sp_offset + caller_sp_to_cfa_offset) as i64); + LabelValueLoc::CFAOffset(cfa_to_sp_offset + slot_offset) + } }; // Coalesce adjacent ranges that for the same location From bec5313ab1fd8bc9c6533c58b32354b55aa93c25 Mon Sep 17 00:00:00 2001 From: Alex Crichton Date: Wed, 7 Jan 2026 08:25:57 -0800 Subject: [PATCH 61/61] Update vets --- supply-chain/imports.lock | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock index 9f9ae55a03b5..e74bfb03fd73 100644 --- a/supply-chain/imports.lock +++ b/supply-chain/imports.lock @@ -1327,8 +1327,8 @@ user-login = "dtolnay" user-name = "David Tolnay" [[publisher.regalloc2]] -version = "0.13.3" -when = "2025-11-13" +version = "0.13.4" +when = "2026-01-06" user-id = 3726 user-login = "cfallin" user-name = "Chris Fallin"