M4ToVGA/M4ToVGA_top_inst.v at main · calphool/M4ToVGA · GitHub

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// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.


// Generated by Quartus Prime Version 20.1 (Build Build 711 06/05/2020)
// Created on Fri Nov 20 23:10:52 2020

M4ToVGA_top M4ToVGA_top_inst
(
	.external_clock(external_clock_sig) ,	// input  external_clock_sig
	.m4_hsync(m4_hsync_sig) ,	// input  m4_hsync_sig
	.m4_vsync(m4_vsync_sig) ,	// input  m4_vsync_sig
	.m4_video(m4_video_sig) ,	// input  m4_video_sig
	.m4_dotclk(m4_dotclk_sig) ,	// input  m4_dotclk_sig
	.vr(vr_sig) ,	// output [1:1] vr_sig
	.vr(vr_sig) ,	// output [0:0] vr_sig
	.vg(vg_sig) ,	// output [1:1] vg_sig
	.vg(vg_sig) ,	// output [0:0] vg_sig
	.vb(vb_sig) ,	// output [1:1] vb_sig
	.vb(vb_sig) ,	// output [0:0] vb_sig
	.vga_vsync(vga_vsync_sig) ,	// output  vga_vsync_sig
	.vga_hsync(vga_hsync_sig) ,	// output  vga_hsync_sig
	.LEDS0(LEDS0_sig) ,	// output  LEDS0_sig
	.LEDS1(LEDS1_sig) ,	// output  LEDS1_sig
	.LEDS2(LEDS2_sig) ,	// output  LEDS2_sig
	.LEDS3(LEDS3_sig) ,	// output  LEDS3_sig
	.PIXSTATE_PIN59(PIXSTATE_PIN59_sig) ,	// output  PIXSTATE_PIN59_sig
	.DOTCLKP2_PIN64(DOTCLKP2_PIN64_sig) ,	// output  DOTCLKP2_PIN64_sig
	.WADDR0_PIN66(WADDR0_PIN66_sig) ,	// output  WADDR0_PIN66_sig
	.WADDR1_PIN68(WADDR1_PIN68_sig) ,	// output  WADDR1_PIN68_sig
	.WADDR2_PIN70(WADDR2_PIN70_sig) ,	// output  WADDR2_PIN70_sig
	.WADDR3_PIN72(WADDR3_PIN72_sig) ,	// output  WADDR3_PIN72_sig
	.FB_DATAOUT_PIN74(FB_DATAOUT_PIN74_sig) ,	// output  FB_DATAOUT_PIN74_sig
	.VGA_CLKOUT_PIN76(VGA_CLKOUT_PIN76_sig) 	// output  VGA_CLKOUT_PIN76_sig
);