Calyx generated hardware to ASIC

[hadirkhan10]

Hi I have seen Calyx as a Dialect in CIRCT. I am not really familiar with CIRCT itself but does Calyx support memory mapping from RTL to actual sram macros for ASIC design? I guess Calyx just aims for FPGA through HLS but going through the ASIC route should also be doable?

[rachitnigam]

Yeah, I think you’d have to use something like the OpenRAM compiler to generate the SRAM and wrap it as a Verilog external to make it available in Calyx. You can look at how core.sv and core.Futil work inside the primitives folder and let us know if you need any help

[rachitnigam]

Calyx optimizations are actually pretty well suited for ASIC design since currently it tries to minimize flip flop usage pretty extensively