[yxi] handle multiple memories in AXI generator

[mercure67]

while attempting to run the linear-algebra-2mm.fuse test in cider/tests/benchmarks/polybench folder, Verilog wrapper generation fails.

this is because while some of the memories are 8 words, alpha_int and beta_int are only 1 word long.

this in turn runs into two issues with the axi generator:

• the generator only adds read/write channels for the first memory (code snippet below [1])
• the add_read_channel and add_write_channel builders will only create a component for one size of internal memory. because all components created have the same name, channels for different-sized memories create conflicts.

at some point, it's worth thinking of how to support multiple external input memories, and work around the two issues above.

[1]: in axi_generator.py

def build():
    prog = Builder(emit_sourceloc=False)
    check_mems_welformed(mems)
    add_arread_channel(prog, mems[0])
    add_awwrite_channel(prog, mems[0])
    add_read_channel(prog, mems[0])
    add_write_channel(prog, mems[0])
    add_bresp_channel(prog, mems[0])
    add_main_comp(prog, mems)
    return prog.program