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Add support for M68060 architecture in M68K disassembler and tests
Add disassembly support for CAS instruction in M68060 and update tests Add support for M68K CPU32 mode and new instructions - Introduced CS_MODE_M68K_CPU32 to support the M68K CPU32 architecture in the Python bindings and C headers. - Updated the instruction table generator to include new CPU32-specific instructions: `bgnd`, `tbls`, `tblu`, `tblsn`, and `tblun`. - Enhanced the instruction decoding logic in `cs.c` to account for CPU32 mode. - Added test cases for new instructions and ensured compatibility with existing M68K modes. - Updated YAML test files to validate the behavior of new instructions under different M68K modes. fix(M68K): fix cross-arch bugs in cpush/cinv and dc.w printing build_cpush_cinv: use op1->reg instead of op1->imm for address register operand. Writing to imm (uint64_t) when reg (m68k_reg, uint32_t) is read back causes garbage values on big-endian targets (PPC64, s390x) due to union byte order mismatch. M68K_printInst: cast imm to uint32_t before passing to PRIx32 format. Passing uint64_t to a PRIx32 format specifier is UB; on 32-bit big-endian MIPS the high word (0) is read instead of the low word containing the instruction bytes. Fixes cstest details failures on QEMU Linux PPC64, s390x, Mips32. run clang-format fix[m68k]: ori build_imm_ea fix[m68k]: btst fix[m68k]: cast immediate values to unsigned int in build_imm_ea functions
1 parent 7b1002d commit 96bfa47

11 files changed

Lines changed: 1922 additions & 146 deletions

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‎arch/M68K/M68KDisassembler.c‎

Lines changed: 559 additions & 10 deletions
Large diffs are not rendered by default.

‎arch/M68K/M68KInstPrinter.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@ static const char *const s_reg_names[] = {
2929
"dtt1", "mmusr", "urp", "srp",
3030

3131
"fpcr", "fpsr", "fpiar",
32+
33+
"tt0", "tt1", "crp",
3234
};
3335

3436
static const char *const s_instruction_names[] = {
@@ -94,7 +96,8 @@ static const char *const s_instruction_names[] = {
9496
"trapt", "trapf", "traphi", "trapls", "trapcc", "traphs",
9597
"trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs",
9698
"trappl", "trapmi", "trapge", "traplt", "trapgt", "traple",
97-
"tst", "unlk", "unpk",
99+
"tst", "unlk", "unpk", "bgnd", "tbls", "tblu",
100+
"tblsn", "tblun",
98101
};
99102
#endif
100103

@@ -380,7 +383,7 @@ void M68K_printInst(MCInst *MI, SStream *O, void *PrinterInfo)
380383
if (MI->Opcode == M68K_INS_INVALID) {
381384
if (ext->op_count)
382385
SStream_concat(O, "dc.w $%" PRIx32,
383-
ext->operands[0].imm);
386+
(uint32_t)ext->operands[0].imm);
384387
else
385388
SStream_concat(O, "dc.w $<unknown>");
386389
return;

‎arch/M68K/M68KInstructionTable.inc‎

Lines changed: 131 additions & 131 deletions
Original file line numberDiff line numberDiff line change
@@ -19144,11 +19144,11 @@ static const instruction_struct g_instruction_table[] = {
1914419144
{ d68000_tas, 0x0, 0x0 },
1914519145
{ d68000_tas, 0x0, 0x0 },
1914619146
{ d68000_tas, 0x0, 0x0 },
19147+
{ d68060_halt, 0x0, 0x0 },
1914719148
{ d68000_invalid, 0x0, 0x0 },
1914819149
{ d68000_invalid, 0x0, 0x0 },
1914919150
{ d68000_invalid, 0x0, 0x0 },
19150-
{ d68000_invalid, 0x0, 0x0 },
19151-
{ d68000_invalid, 0x0, 0x0 },
19151+
{ d68060_pulse, 0x0, 0x0 },
1915219152
{ d68000_invalid, 0x0, 0x0 },
1915319153
{ d68000_invalid, 0x0, 0x0 },
1915419154
{ d68000_invalid, 0x0, 0x0 },
@@ -19194,7 +19194,7 @@ static const instruction_struct g_instruction_table[] = {
1919419194
{ d68000_tas, 0x0, 0x0 },
1919519195
{ d68000_tas, 0x0, 0x0 },
1919619196
{ d68000_tas, 0x0, 0x0 },
19197-
{ d68000_invalid, 0x0, 0x0 },
19197+
{ d68cpu32_bgnd, 0x0, 0x0 },
1919819198
{ d68000_invalid, 0x0, 0x0 },
1919919199
{ d68000_illegal, 0x0, 0x0 },
1920019200
{ d68000_invalid, 0x0, 0x0 },
@@ -62720,38 +62720,38 @@ static const instruction_struct g_instruction_table[] = {
6272062720
{ d68040_cpush, 0x0, 0x0 },
6272162721
{ d68040_cpush, 0x0, 0x0 },
6272262722
{ d68040_cpush, 0x0, 0x0 },
62723-
{ d68000_1111, 0x0, 0x0 },
62724-
{ d68000_1111, 0x0, 0x0 },
62725-
{ d68000_1111, 0x0, 0x0 },
62726-
{ d68000_1111, 0x0, 0x0 },
62727-
{ d68000_1111, 0x0, 0x0 },
62728-
{ d68000_1111, 0x0, 0x0 },
62729-
{ d68000_1111, 0x0, 0x0 },
62730-
{ d68000_1111, 0x0, 0x0 },
62731-
{ d68000_1111, 0x0, 0x0 },
62732-
{ d68000_1111, 0x0, 0x0 },
62733-
{ d68000_1111, 0x0, 0x0 },
62734-
{ d68000_1111, 0x0, 0x0 },
62735-
{ d68000_1111, 0x0, 0x0 },
62736-
{ d68000_1111, 0x0, 0x0 },
62737-
{ d68000_1111, 0x0, 0x0 },
62738-
{ d68000_1111, 0x0, 0x0 },
62739-
{ d68020_cpsave, 0x0, 0x0 },
62740-
{ d68020_cpsave, 0x0, 0x0 },
62741-
{ d68020_cpsave, 0x0, 0x0 },
62742-
{ d68020_cpsave, 0x0, 0x0 },
62743-
{ d68020_cpsave, 0x0, 0x0 },
62744-
{ d68020_cpsave, 0x0, 0x0 },
62745-
{ d68020_cpsave, 0x0, 0x0 },
62746-
{ d68020_cpsave, 0x0, 0x0 },
62747-
{ d68000_1111, 0x0, 0x0 },
62748-
{ d68000_1111, 0x0, 0x0 },
62749-
{ d68000_1111, 0x0, 0x0 },
62750-
{ d68000_1111, 0x0, 0x0 },
62751-
{ d68000_1111, 0x0, 0x0 },
62752-
{ d68000_1111, 0x0, 0x0 },
62753-
{ d68000_1111, 0x0, 0x0 },
62754-
{ d68000_1111, 0x0, 0x0 },
62723+
{ d68040_pflush, 0x0, 0x0 },
62724+
{ d68040_pflush, 0x0, 0x0 },
62725+
{ d68040_pflush, 0x0, 0x0 },
62726+
{ d68040_pflush, 0x0, 0x0 },
62727+
{ d68040_pflush, 0x0, 0x0 },
62728+
{ d68040_pflush, 0x0, 0x0 },
62729+
{ d68040_pflush, 0x0, 0x0 },
62730+
{ d68040_pflush, 0x0, 0x0 },
62731+
{ d68040_pflush, 0x0, 0x0 },
62732+
{ d68040_pflush, 0x0, 0x0 },
62733+
{ d68040_pflush, 0x0, 0x0 },
62734+
{ d68040_pflush, 0x0, 0x0 },
62735+
{ d68040_pflush, 0x0, 0x0 },
62736+
{ d68040_pflush, 0x0, 0x0 },
62737+
{ d68040_pflush, 0x0, 0x0 },
62738+
{ d68040_pflush, 0x0, 0x0 },
62739+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62740+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62741+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62742+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62743+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62744+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62745+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62746+
{ d68040_pflush_or_cpsave, 0x0, 0x0 },
62747+
{ d68040_pflush, 0x0, 0x0 },
62748+
{ d68040_pflush, 0x0, 0x0 },
62749+
{ d68040_pflush, 0x0, 0x0 },
62750+
{ d68040_pflush, 0x0, 0x0 },
62751+
{ d68040_pflush, 0x0, 0x0 },
62752+
{ d68040_pflush, 0x0, 0x0 },
62753+
{ d68040_pflush, 0x0, 0x0 },
62754+
{ d68040_pflush, 0x0, 0x0 },
6275562755
{ d68020_cpsave, 0x0, 0x0 },
6275662756
{ d68020_cpsave, 0x0, 0x0 },
6275762757
{ d68020_cpsave, 0x0, 0x0 },
@@ -62792,14 +62792,14 @@ static const instruction_struct g_instruction_table[] = {
6279262792
{ d68000_1111, 0x0, 0x0 },
6279362793
{ d68000_1111, 0x0, 0x0 },
6279462794
{ d68000_1111, 0x0, 0x0 },
62795-
{ d68000_1111, 0x0, 0x0 },
62796-
{ d68000_1111, 0x0, 0x0 },
62797-
{ d68000_1111, 0x0, 0x0 },
62798-
{ d68000_1111, 0x0, 0x0 },
62799-
{ d68000_1111, 0x0, 0x0 },
62800-
{ d68000_1111, 0x0, 0x0 },
62801-
{ d68000_1111, 0x0, 0x0 },
62802-
{ d68000_1111, 0x0, 0x0 },
62795+
{ d68040_ptest, 0x0, 0x0 },
62796+
{ d68040_ptest, 0x0, 0x0 },
62797+
{ d68040_ptest, 0x0, 0x0 },
62798+
{ d68040_ptest, 0x0, 0x0 },
62799+
{ d68040_ptest, 0x0, 0x0 },
62800+
{ d68040_ptest, 0x0, 0x0 },
62801+
{ d68040_ptest, 0x0, 0x0 },
62802+
{ d68040_ptest, 0x0, 0x0 },
6280362803
{ d68020_cprestore, 0x0, 0x0 },
6280462804
{ d68020_cprestore, 0x0, 0x0 },
6280562805
{ d68020_cprestore, 0x0, 0x0 },
@@ -62824,6 +62824,14 @@ static const instruction_struct g_instruction_table[] = {
6282462824
{ d68000_1111, 0x0, 0x0 },
6282562825
{ d68000_1111, 0x0, 0x0 },
6282662826
{ d68000_1111, 0x0, 0x0 },
62827+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62828+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62829+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62830+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62831+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62832+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62833+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
62834+
{ d68040_ptest_or_cprestore, 0x0, 0x0 },
6282762835
{ d68020_cprestore, 0x0, 0x0 },
6282862836
{ d68020_cprestore, 0x0, 0x0 },
6282962837
{ d68020_cprestore, 0x0, 0x0 },
@@ -62837,30 +62845,6 @@ static const instruction_struct g_instruction_table[] = {
6283762845
{ d68020_cprestore, 0x0, 0x0 },
6283862846
{ d68020_cprestore, 0x0, 0x0 },
6283962847
{ d68020_cprestore, 0x0, 0x0 },
62840-
{ d68020_cprestore, 0x0, 0x0 },
62841-
{ d68020_cprestore, 0x0, 0x0 },
62842-
{ d68020_cprestore, 0x0, 0x0 },
62843-
{ d68020_cprestore, 0x0, 0x0 },
62844-
{ d68020_cprestore, 0x0, 0x0 },
62845-
{ d68020_cprestore, 0x0, 0x0 },
62846-
{ d68020_cprestore, 0x0, 0x0 },
62847-
{ d68020_cprestore, 0x0, 0x0 },
62848-
{ d68000_1111, 0x0, 0x0 },
62849-
{ d68000_1111, 0x0, 0x0 },
62850-
{ d68000_1111, 0x0, 0x0 },
62851-
{ d68000_1111, 0x0, 0x0 },
62852-
{ d68000_1111, 0x0, 0x0 },
62853-
{ d68000_1111, 0x0, 0x0 },
62854-
{ d68000_1111, 0x0, 0x0 },
62855-
{ d68000_1111, 0x0, 0x0 },
62856-
{ d68000_1111, 0x0, 0x0 },
62857-
{ d68000_1111, 0x0, 0x0 },
62858-
{ d68000_1111, 0x0, 0x0 },
62859-
{ d68000_1111, 0x0, 0x0 },
62860-
{ d68000_1111, 0x0, 0x0 },
62861-
{ d68000_1111, 0x0, 0x0 },
62862-
{ d68000_1111, 0x0, 0x0 },
62863-
{ d68000_1111, 0x0, 0x0 },
6286462848
{ d68000_1111, 0x0, 0x0 },
6286562849
{ d68000_1111, 0x0, 0x0 },
6286662850
{ d68000_1111, 0x0, 0x0 },
@@ -62872,6 +62856,14 @@ static const instruction_struct g_instruction_table[] = {
6287262856
{ d68000_1111, 0x0, 0x0 },
6287362857
{ d68000_1111, 0x0, 0x0 },
6287462858
{ d68000_1111, 0x0, 0x0 },
62859+
{ d68060_plpa, 0x0, 0x0 },
62860+
{ d68060_plpa, 0x0, 0x0 },
62861+
{ d68060_plpa, 0x0, 0x0 },
62862+
{ d68060_plpa, 0x0, 0x0 },
62863+
{ d68060_plpa, 0x0, 0x0 },
62864+
{ d68060_plpa, 0x0, 0x0 },
62865+
{ d68060_plpa, 0x0, 0x0 },
62866+
{ d68060_plpa, 0x0, 0x0 },
6287562867
{ d68000_1111, 0x0, 0x0 },
6287662868
{ d68000_1111, 0x0, 0x0 },
6287762869
{ d68000_1111, 0x0, 0x0 },
@@ -62928,6 +62920,14 @@ static const instruction_struct g_instruction_table[] = {
6292862920
{ d68000_1111, 0x0, 0x0 },
6292962921
{ d68000_1111, 0x0, 0x0 },
6293062922
{ d68000_1111, 0x0, 0x0 },
62923+
{ d68060_plpa, 0x0, 0x0 },
62924+
{ d68060_plpa, 0x0, 0x0 },
62925+
{ d68060_plpa, 0x0, 0x0 },
62926+
{ d68060_plpa, 0x0, 0x0 },
62927+
{ d68060_plpa, 0x0, 0x0 },
62928+
{ d68060_plpa, 0x0, 0x0 },
62929+
{ d68060_plpa, 0x0, 0x0 },
62930+
{ d68060_plpa, 0x0, 0x0 },
6293162931
{ d68000_1111, 0x0, 0x0 },
6293262932
{ d68000_1111, 0x0, 0x0 },
6293362933
{ d68000_1111, 0x0, 0x0 },
@@ -63488,70 +63488,70 @@ static const instruction_struct g_instruction_table[] = {
6348863488
{ d68000_1111, 0x0, 0x0 },
6348963489
{ d68000_1111, 0x0, 0x0 },
6349063490
{ d68000_1111, 0x0, 0x0 },
63491-
{ d68020_cpgen, 0x0, 0x0 },
63492-
{ d68020_cpgen, 0x0, 0x0 },
63493-
{ d68020_cpgen, 0x0, 0x0 },
63494-
{ d68020_cpgen, 0x0, 0x0 },
63495-
{ d68020_cpgen, 0x0, 0x0 },
63496-
{ d68020_cpgen, 0x0, 0x0 },
63497-
{ d68020_cpgen, 0x0, 0x0 },
63498-
{ d68020_cpgen, 0x0, 0x0 },
63499-
{ d68020_cpgen, 0x0, 0x0 },
63500-
{ d68020_cpgen, 0x0, 0x0 },
63501-
{ d68020_cpgen, 0x0, 0x0 },
63502-
{ d68020_cpgen, 0x0, 0x0 },
63503-
{ d68020_cpgen, 0x0, 0x0 },
63504-
{ d68020_cpgen, 0x0, 0x0 },
63505-
{ d68020_cpgen, 0x0, 0x0 },
63506-
{ d68020_cpgen, 0x0, 0x0 },
63507-
{ d68020_cpgen, 0x0, 0x0 },
63508-
{ d68020_cpgen, 0x0, 0x0 },
63509-
{ d68020_cpgen, 0x0, 0x0 },
63510-
{ d68020_cpgen, 0x0, 0x0 },
63511-
{ d68020_cpgen, 0x0, 0x0 },
63512-
{ d68020_cpgen, 0x0, 0x0 },
63513-
{ d68020_cpgen, 0x0, 0x0 },
63514-
{ d68020_cpgen, 0x0, 0x0 },
63515-
{ d68020_cpgen, 0x0, 0x0 },
63516-
{ d68020_cpgen, 0x0, 0x0 },
63517-
{ d68020_cpgen, 0x0, 0x0 },
63518-
{ d68020_cpgen, 0x0, 0x0 },
63519-
{ d68020_cpgen, 0x0, 0x0 },
63520-
{ d68020_cpgen, 0x0, 0x0 },
63521-
{ d68020_cpgen, 0x0, 0x0 },
63522-
{ d68020_cpgen, 0x0, 0x0 },
63523-
{ d68020_cpgen, 0x0, 0x0 },
63524-
{ d68020_cpgen, 0x0, 0x0 },
63525-
{ d68020_cpgen, 0x0, 0x0 },
63526-
{ d68020_cpgen, 0x0, 0x0 },
63527-
{ d68020_cpgen, 0x0, 0x0 },
63528-
{ d68020_cpgen, 0x0, 0x0 },
63529-
{ d68020_cpgen, 0x0, 0x0 },
63530-
{ d68020_cpgen, 0x0, 0x0 },
63531-
{ d68020_cpgen, 0x0, 0x0 },
63532-
{ d68020_cpgen, 0x0, 0x0 },
63533-
{ d68020_cpgen, 0x0, 0x0 },
63534-
{ d68020_cpgen, 0x0, 0x0 },
63535-
{ d68020_cpgen, 0x0, 0x0 },
63536-
{ d68020_cpgen, 0x0, 0x0 },
63537-
{ d68020_cpgen, 0x0, 0x0 },
63538-
{ d68020_cpgen, 0x0, 0x0 },
63539-
{ d68020_cpgen, 0x0, 0x0 },
63540-
{ d68020_cpgen, 0x0, 0x0 },
63541-
{ d68020_cpgen, 0x0, 0x0 },
63542-
{ d68020_cpgen, 0x0, 0x0 },
63543-
{ d68020_cpgen, 0x0, 0x0 },
63544-
{ d68020_cpgen, 0x0, 0x0 },
63545-
{ d68020_cpgen, 0x0, 0x0 },
63546-
{ d68020_cpgen, 0x0, 0x0 },
63547-
{ d68020_cpgen, 0x0, 0x0 },
63548-
{ d68020_cpgen, 0x0, 0x0 },
63549-
{ d68020_cpgen, 0x0, 0x0 },
63550-
{ d68020_cpgen, 0x0, 0x0 },
63551-
{ d68020_cpgen, 0x0, 0x0 },
63552-
{ d68020_cpgen, 0x0, 0x0 },
63553-
{ d68020_cpgen, 0x0, 0x0 },
63554-
{ d68020_cpgen, 0x0, 0x0 },
63491+
{ d68060_lpstop, 0x0, 0x0 },
63492+
{ d68cpu32_tbl, 0x0, 0x0 },
63493+
{ d68cpu32_tbl, 0x0, 0x0 },
63494+
{ d68cpu32_tbl, 0x0, 0x0 },
63495+
{ d68cpu32_tbl, 0x0, 0x0 },
63496+
{ d68cpu32_tbl, 0x0, 0x0 },
63497+
{ d68cpu32_tbl, 0x0, 0x0 },
63498+
{ d68cpu32_tbl, 0x0, 0x0 },
63499+
{ d68cpu32_tbl, 0x0, 0x0 },
63500+
{ d68cpu32_tbl, 0x0, 0x0 },
63501+
{ d68cpu32_tbl, 0x0, 0x0 },
63502+
{ d68cpu32_tbl, 0x0, 0x0 },
63503+
{ d68cpu32_tbl, 0x0, 0x0 },
63504+
{ d68cpu32_tbl, 0x0, 0x0 },
63505+
{ d68cpu32_tbl, 0x0, 0x0 },
63506+
{ d68cpu32_tbl, 0x0, 0x0 },
63507+
{ d68cpu32_tbl, 0x0, 0x0 },
63508+
{ d68cpu32_tbl, 0x0, 0x0 },
63509+
{ d68cpu32_tbl, 0x0, 0x0 },
63510+
{ d68cpu32_tbl, 0x0, 0x0 },
63511+
{ d68cpu32_tbl, 0x0, 0x0 },
63512+
{ d68cpu32_tbl, 0x0, 0x0 },
63513+
{ d68cpu32_tbl, 0x0, 0x0 },
63514+
{ d68cpu32_tbl, 0x0, 0x0 },
63515+
{ d68cpu32_tbl, 0x0, 0x0 },
63516+
{ d68cpu32_tbl, 0x0, 0x0 },
63517+
{ d68cpu32_tbl, 0x0, 0x0 },
63518+
{ d68cpu32_tbl, 0x0, 0x0 },
63519+
{ d68cpu32_tbl, 0x0, 0x0 },
63520+
{ d68cpu32_tbl, 0x0, 0x0 },
63521+
{ d68cpu32_tbl, 0x0, 0x0 },
63522+
{ d68cpu32_tbl, 0x0, 0x0 },
63523+
{ d68cpu32_tbl, 0x0, 0x0 },
63524+
{ d68cpu32_tbl, 0x0, 0x0 },
63525+
{ d68cpu32_tbl, 0x0, 0x0 },
63526+
{ d68cpu32_tbl, 0x0, 0x0 },
63527+
{ d68cpu32_tbl, 0x0, 0x0 },
63528+
{ d68cpu32_tbl, 0x0, 0x0 },
63529+
{ d68cpu32_tbl, 0x0, 0x0 },
63530+
{ d68cpu32_tbl, 0x0, 0x0 },
63531+
{ d68cpu32_tbl, 0x0, 0x0 },
63532+
{ d68cpu32_tbl, 0x0, 0x0 },
63533+
{ d68cpu32_tbl, 0x0, 0x0 },
63534+
{ d68cpu32_tbl, 0x0, 0x0 },
63535+
{ d68cpu32_tbl, 0x0, 0x0 },
63536+
{ d68cpu32_tbl, 0x0, 0x0 },
63537+
{ d68cpu32_tbl, 0x0, 0x0 },
63538+
{ d68cpu32_tbl, 0x0, 0x0 },
63539+
{ d68cpu32_tbl, 0x0, 0x0 },
63540+
{ d68cpu32_tbl, 0x0, 0x0 },
63541+
{ d68cpu32_tbl, 0x0, 0x0 },
63542+
{ d68cpu32_tbl, 0x0, 0x0 },
63543+
{ d68cpu32_tbl, 0x0, 0x0 },
63544+
{ d68cpu32_tbl, 0x0, 0x0 },
63545+
{ d68cpu32_tbl, 0x0, 0x0 },
63546+
{ d68cpu32_tbl, 0x0, 0x0 },
63547+
{ d68cpu32_tbl, 0x0, 0x0 },
63548+
{ d68cpu32_tbl, 0x0, 0x0 },
63549+
{ d68cpu32_tbl, 0x0, 0x0 },
63550+
{ d68cpu32_tbl, 0x0, 0x0 },
63551+
{ d68cpu32_tbl, 0x0, 0x0 },
63552+
{ d68cpu32_tbl, 0x0, 0x0 },
63553+
{ d68cpu32_tbl, 0x0, 0x0 },
63554+
{ d68cpu32_tbl, 0x0, 0x0 },
6355563555
{ d68020_cpscc, 0x0, 0x0 },
6355663556
{ d68020_cpscc, 0x0, 0x0 },
6355763557
{ d68020_cpscc, 0x0, 0x0 },

‎bindings/python/capstone/__init__.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,7 @@
9292
'CS_MODE_M68K_030',
9393
'CS_MODE_M68K_040',
9494
'CS_MODE_M68K_060',
95+
'CS_MODE_M68K_CPU32',
9596
'CS_MODE_M680X_6301',
9697
'CS_MODE_M680X_6309',
9798
'CS_MODE_M680X_6800',
@@ -364,6 +365,7 @@
364365
CS_MODE_M68K_030 = (1 << 4) # M68K 68030 mode
365366
CS_MODE_M68K_040 = (1 << 5) # M68K 68040 mode
366367
CS_MODE_M68K_060 = (1 << 6) # M68K 68060 mode
368+
CS_MODE_M68K_CPU32 = (1 << 7)
367369
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
368370
CS_MODE_MIPS16 = CS_MODE_16 # Generic mips16
369371
CS_MODE_MIPS32 = CS_MODE_32 # Generic mips32

‎contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -255,6 +255,9 @@ static opcode_struct g_opcode_info[] = {
255255
{ "d68020_pack_rr", 0xf1f8, 0x8140, 0x000 },
256256
{ "d68020_pack_mm", 0xf1f8, 0x8148, 0x000 },
257257
{ "d68000_pea", 0xffc0, 0x4840, 0x27b },
258+
{ "d68060_halt", 0xffff, 0x4ac8, 0x000 },
259+
{ "d68060_pulse", 0xffff, 0x4acc, 0x000 },
260+
{ "d68cpu32_bgnd", 0xffff, 0x4afa, 0x000 },
258261
{ "d68000_reset", 0xffff, 0x4e70, 0x000 },
259262
{ "d68000_ror_s_8", 0xf1f8, 0xe018, 0x000 },
260263
{ "d68000_ror_s_16", 0xf1f8, 0xe058, 0x000 },
@@ -293,6 +296,14 @@ static opcode_struct g_opcode_info[] = {
293296
{ "d68000_sbcd_mm", 0xf1f8, 0x8108, 0x000 },
294297
{ "d68000_scc", 0xf0c0, 0x50c0, 0xbf8 },
295298
{ "d68000_stop", 0xffff, 0x4e72, 0x000 },
299+
{ "d68060_lpstop", 0xffff, 0xf800, 0x000 },
300+
{ "d68cpu32_tbl", 0xffc0, 0xf800, 0x000 },
301+
{ "d68040_pflush", 0xffe0, 0xf500, 0x000 },
302+
{ "d68040_pflush_or_cpsave", 0xfff8, 0xf510, 0x000 },
303+
{ "d68040_ptest", 0xfff8, 0xf548, 0x000 },
304+
{ "d68040_ptest_or_cprestore", 0xfff8, 0xf568, 0x000 },
305+
{ "d68060_plpa", 0xfff8, 0xf588, 0x000 },
306+
{ "d68060_plpa", 0xfff8, 0xf5c8, 0x000 },
296307
{ "d68000_sub_er_8", 0xf1c0, 0x9000, 0xbff },
297308
{ "d68000_sub_er_16", 0xf1c0, 0x9040, 0xfff },
298309
{ "d68000_sub_er_32", 0xf1c0, 0x9080, 0xfff },

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