AArch64: SYSL writes its Rt operand, it does not read it

SYSL was generated with CS_AC_READ on Rt, but Rt is the destination.
"SYSL <Xt>, #<op1>, <Cn>, <Cm>{, #<op2>}" is the system instruction
WITH RESULT, and the Arm ARM names Xt "the 64-bit name of the
general-purpose destination register", encoded in the Rt field.

Before:

  sysl x0, #0, c0, c0, #0
    operands[0].type: REG = x0
    operands[0].access: READ
  Registers read: x0

After:

  sysl x0, #0, c0, c0, #0
    operands[0].type: REG = x0
    operands[0].access: WRITE
  Registers modified: x0

A consumer tracking register liveness saw a use where there is a
definition, which is the unsafe direction: a value written into Xt
looked like it was still needed.

SYS (without the L) is the opposite direction -- its Xt is a source,
and it takes it as the last operand -- and is already CS_AC_READ; it is
untouched.

Adds the correction to suite/auto-sync/inc_patches so it survives
regeneration, plus a regression case. That case asserts regs_write
rather than the operand list because two of SYSL's five operands are
AARCH64_OP_CIMM, which cstest's operand comparison does not handle
(it would take the default branch and report "op type not handled").
regs_write is a field of the `details` mapping, alongside `aarch64`
rather than inside it, and cstest compares it through cs_regs_access()
-- the exact view this change corrects.

Author: gaul

arch/AArch64/AArch64GenCSMappingInsnOp.inc

@@ -46762,7 +46762,7 @@
 }},
 { /* AARCH64_SYSLxt (7060) - AARCH64_INS_SYSL - sysl	$Rt, $op1, $Cn, $Cm, $op2 */
 {
-  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* Rt */
   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* op1 */
   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Cn */
   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Cm */

suite/auto-sync/inc_patches/AArch64/02_sysl_rt_access.patch

@@ -0,0 +1,26 @@
+# AArch64 SYSL was generated with CS_AC_READ on its Rt operand, but Rt
+# is the destination: "SYSL <Xt>, #<op1>, <Cn>, <Cm>{, #<op2>}" is the
+# system instruction WITH RESULT, and Xt receives that result. The Arm
+# ARM encodes it in the Rt field and names it "the 64-bit name of the
+# general-purpose destination register".
+#
+# Before this patch `sysl x0, #0, c0, c0, #0` reported operands[0] as
+# CS_AC_READ and listed x0 under "Registers read" rather than
+# "Registers modified", so a consumer tracking register liveness saw a
+# use where there is a definition.
+#
+# SYS (without the L) is the opposite direction -- its Xt is a source --
+# and is correctly CS_AC_READ already; it is untouched here.
+diff --git a/arch/AArch64/AArch64GenCSMappingInsnOp.inc b/arch/AArch64/AArch64GenCSMappingInsnOp.inc
+index 4954eb31..9a9a5b1e 100644
+--- a/arch/AArch64/AArch64GenCSMappingInsnOp.inc
++++ b/arch/AArch64/AArch64GenCSMappingInsnOp.inc
+@@ -46762,7 +46762,7 @@
+ }},
+ { /* AARCH64_SYSLxt (7060) - AARCH64_INS_SYSL - sysl	$Rt, $op1, $Cn, $Cm, $op2 */
+ {
+-  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* Rt */
++  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* Rt */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* op1 */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Cn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Cm */

tests/details/aarch64.yaml

@@ -1685,3 +1685,15 @@ test_cases:
         details:
           # Exact-match register lists: x0/x1 only, no NZCV write.
           regs_read: [ x0, x1 ]
+  -
+    input:
+      bytes: [0x00,0x00,0x28,0xd5]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sysl	x0, #0, c0, c0, #0"
+        details:
+          regs_write: [ x0 ]