RISC-V: compressed ISA support?

[KireinaHoro]

I am testing with the RISC-V frontend on next branch, and seems like compressed instructions are not supported yet:

#define RISCV_CODE64                                                           \
  "\x03\xbe\x03\x00\x23\xb0\xc2\x01\xa1\x02\xa1\x03\xe3\xca\x62\xfe\x82\x8e"

****************
Platform: riscv64
Code:0x03 0xbe 0x03 0x00 0x23 0xb0 0xc2 0x01 0xa1 0x02 0xa1 0x03 0xe3 0xca 0x62 0xfe 0x82 0x8e
Disasm:
0x1000: ld      t3, 0(t2)
        op_count: 2
                operands[0].type: REG = t3
                operands[1].type: MEM
                        operands[1].mem.base: REG = t2
        This instruction belongs to groups: isrv64

0x1004: sd      t3, 0(t0)
        op_count: 2
                operands[0].type: REG = t3
                operands[1].type: MEM
                        operands[1].mem.base: REG = t0
        This instruction belongs to groups: isrv64

0x1008:

Meanwhile, with objdump,

$ echo -ne "\x03\xbe\x03\x00\x23\xb0\xc2\x01\xa1\x02\xa1\x03\xe3\xca\x62\xfe\x82\x8e" > test.bin
$ riscv64-linux-gnu-objdump -b binary -D -m riscv:rv64 test.bin

test.bin:     file format binary


Disassembly of section .data:

0000000000000000 <.data>:
   0:   0003be03                ld      t3,0(t2)
   4:   01c2b023                sd      t3,0(t0)
   8:   02a1                    addi    t0,t0,8
   a:   03a1                    addi    t2,t2,8
   c:   fe62cae3                blt     t0,t1,0x0
  10:   8e82                    jr      t4
$

Is the Compressed ISA not supported yet? Are there any roadmaps?

[garrettgu10]

There is a PR available #1594 so please take a look at that. :-)

[Rot127]

Fixed by #2756