Work environment
| Questions |
Answers |
| OS/arch/bits |
RHEL9, x86 |
| Architecture |
x86 |
| Source of Capstone |
git clone, pip, release binaries, RHEL 9 RPM |
| Version/git commit |
v4.0.2, v6.0.0 (git e46838e) |
Instruction bytes giving faulty results
0x62,0x41,0x04,0xcf,0x59,0xc5
Expected results
It should be:
./cstool -d x64 624104cf59c5
0 62 41 04 cf 59 c5 vmulps zmm24 {k7} {z}, zmm15, zmm13
ID: 1060 (vmulps)
Prefix:0x00 0x00 0x00 0x00
Opcode:0x62 0x41 0x04 0xcf
rex: 0x45
addr_size: 8
modrm: 0xc5
disp: 0x0
sib: 0x0
op_count: 4
operands[0].type: REG = zmm24
operands[0].size: 64
operands[0].access: WRITE
operands[1].type: REG = k7
operands[1].avx_zero_opmask: TRUE
operands[1].size: 2
operands[1].access: READ
operands[2].type: REG = zmm15
operands[2].size: 64
operands[2].access: READ
operands[3].type: REG = zmm13
operands[3].size: 64
***** operands[3].access: READ ***** MISSING LINE *****
Registers read: k7 zmm15 zmm13
Registers modified: zmm24
Groups: avx512
Steps to get the wrong result
With cstool:
./cstool -d x64 624104cf59c5
0 62 41 04 cf 59 c5 vmulps zmm24 {k7} {z}, zmm15, zmm13
ID: 1060 (vmulps)
Prefix:0x00 0x00 0x00 0x00
Opcode:0x62 0x41 0x04 0xcf
rex: 0x45
addr_size: 8
modrm: 0xc5
disp: 0x0
sib: 0x0
op_count: 4
operands[0].type: REG = zmm24
operands[0].size: 64
operands[0].access: WRITE
operands[1].type: REG = k7
operands[1].avx_zero_opmask: TRUE
operands[1].size: 2
operands[1].access: READ
operands[2].type: REG = zmm15
operands[2].size: 64
operands[2].access: READ
operands[3].type: REG = zmm13
operands[3].size: 64
Registers read: k7 zmm15
Registers modified: zmm24
Groups: avx512
Additional Logs, screenshots, source code, configuration dump, ...
Appears that X86MappingInsnOp.inc does not increase the number of registers listed when a Mask Register is used, and so only the first 3 registers are given ACCESS rights.
Work environment
git clone, pip, release binaries, RHEL 9 RPMInstruction bytes giving faulty results
Expected results
It should be:
Steps to get the wrong result
With
cstool:./cstool -d x64 624104cf59c5 0 62 41 04 cf 59 c5 vmulps zmm24 {k7} {z}, zmm15, zmm13 ID: 1060 (vmulps) Prefix:0x00 0x00 0x00 0x00 Opcode:0x62 0x41 0x04 0xcf rex: 0x45 addr_size: 8 modrm: 0xc5 disp: 0x0 sib: 0x0 op_count: 4 operands[0].type: REG = zmm24 operands[0].size: 64 operands[0].access: WRITE operands[1].type: REG = k7 operands[1].avx_zero_opmask: TRUE operands[1].size: 2 operands[1].access: READ operands[2].type: REG = zmm15 operands[2].size: 64 operands[2].access: READ operands[3].type: REG = zmm13 operands[3].size: 64 Registers read: k7 zmm15 Registers modified: zmm24 Groups: avx512Additional Logs, screenshots, source code, configuration dump, ...
Appears that
X86MappingInsnOp.incdoes not increase the number of registers listed when a Mask Register is used, and so only the first 3 registers are given ACCESS rights.