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Add tricore tc1.8 instructions:
add.df sub.df madd.df msub.df mul.df div.df cmp.df max.df min.df min.f max.f dftoi dftoiz dftoin ftoin dftou dftouz dftol dftoul dftoulz abs.f abs.df dftolz neg.df neg.f qseed.df itodf utodf ltodf ultodf dftof ftodf
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-39
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‎.gitignore‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,3 +70,4 @@ pythonenv*
7070
/clang/utils/analyzer/projects/*/RefScanBuildResults
7171
# automodapi puts generated documentation files here.
7272
/lldb/docs/python_api/
73+
output_tmp/

‎gen_cs_tables.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
# Compare the generated tables of our refactored TableGen to the original ones.
44

55
# We skip Alpha because it is no longer supported by upstream LLVM
6-
archs="AArch64 ARM PPC LoongArch Alpha"
6+
archs="AArch64 ARM PPC LoongArch Alpha TriCore"
77
file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
88
release="18"
99
repo_root=$(git rev-parse --show-toplevel)

‎llvm/lib/Target/TriCore/TriCore.td‎

Lines changed: 24 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
//===----------------------------------------------------------------------===//
1717

1818
include "llvm/Target/Target.td"
19+
include "llvm/TableGen/SearchableTable.td"
1920

2021
//===----------------------------------------------------------------------===//
2122
// Descriptions
@@ -44,6 +45,9 @@ def HasV161Ops : SubtargetFeature<"v1.6.1", "HasV161Ops", "true",
4445
def HasV162Ops : SubtargetFeature<"v1.6.2", "HasV162Ops", "true",
4546
"Support TriCore v1.6.2 instructions",
4647
[]>;
48+
def HasV180Ops : SubtargetFeature<"v1.8.0", "HasV180Ops", "true",
49+
"Support TriCore v1.8.0 instructions",
50+
[]>;
4751

4852
def HasV110 : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV110Ops), "v1.1">;
4953
def HasV120 : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV120Ops), "v1.2">;
@@ -52,19 +56,22 @@ def HasV131 : Predicate<"HasV131Ops()">, AssemblerPredicate<(all_of HasV131O
5256
def HasV160 : Predicate<"HasV160Ops()">, AssemblerPredicate<(all_of HasV160Ops), "v1.6">;
5357
def HasV161 : Predicate<"HasV161Ops()">, AssemblerPredicate<(all_of HasV161Ops), "v1.6.1">;
5458
def HasV162 : Predicate<"HasV162Ops()">, AssemblerPredicate<(all_of HasV162Ops), "v1.6.2">;
55-
56-
def HasV120_UP : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
57-
, AssemblerPredicate<(any_of HasV120Ops, HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v120up">;
58-
def HasV130_UP : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
59-
, AssemblerPredicate<(any_of HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v130up">;
60-
def HasV131_UP : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
61-
, AssemblerPredicate<(any_of HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v131up">;
62-
def HasV160_UP : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops()">
63-
, AssemblerPredicate<(any_of HasV160Ops, HasV161Ops, HasV162Ops), "v160up">;
64-
def HasV161_UP : Predicate<"HasV161Ops() || HasV162Ops()">
65-
, AssemblerPredicate<(any_of HasV161Ops, HasV162Ops), "v161up">;
66-
def HasV162_UP : Predicate<"HasV162Ops()">
67-
, AssemblerPredicate<(any_of HasV162Ops), "v162up">;
59+
def HasV180 : Predicate<"HasV180Ops()">, AssemblerPredicate<(all_of HasV180Ops), "v1.8.0">;
60+
61+
def HasV120_UP : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops() || HasV180Ops()">
62+
, AssemblerPredicate<(any_of HasV120Ops, HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops, HasV180Ops), "v120up">;
63+
def HasV130_UP : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops() || HasV180Ops()">
64+
, AssemblerPredicate<(any_of HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops, HasV180Ops), "v130up">;
65+
def HasV131_UP : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops() || HasV180Ops()">
66+
, AssemblerPredicate<(any_of HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops, HasV180Ops), "v131up">;
67+
def HasV160_UP : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops() || HasV180Ops()">
68+
, AssemblerPredicate<(any_of HasV160Ops, HasV161Ops, HasV162Ops, HasV180Ops), "v160up">;
69+
def HasV161_UP : Predicate<"HasV161Ops() || HasV162Ops() || HasV180Ops()">
70+
, AssemblerPredicate<(any_of HasV161Ops, HasV162Ops, HasV180Ops), "v161up">;
71+
def HasV162_UP : Predicate<"HasV162Ops() || HasV180Ops()">
72+
, AssemblerPredicate<(any_of HasV162Ops, HasV180Ops), "v162up">;
73+
def HasV180_UP : Predicate<"HasV162Ops()">
74+
, AssemblerPredicate<(any_of HasV180Ops), "v180up">;
6875

6976
def HasV120_DN : Predicate<"HasV120Ops() || HasV110Ops()">,
7077
AssemblerPredicate<(any_of HasV120Ops, HasV110Ops), "v120dn">;
@@ -78,6 +85,8 @@ def HasV161_DN : Predicate<"HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV
7885
AssemblerPredicate<(any_of HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v161dn">;
7986
def HasV162_DN : Predicate<"HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
8087
AssemblerPredicate<(any_of HasV162Ops, HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v162dn">;
88+
def HasV180_DN : Predicate<"HasV180Ops() || HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
89+
AssemblerPredicate<(any_of HasV180Ops, HasV162Ops, HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v162dn">;
8190

8291

8392
class Architecture<string fname, string aname, list<SubtargetFeature> features = []>
@@ -95,6 +104,7 @@ def TRICORE_V1_3_1 : Architecture<"tricore-V1.3.1", "TRICOREv131", [HasV131Ops
95104
def TRICORE_V1_6 : Architecture<"tricore-V1.6", "TRICOREv160", [HasV160Ops]>;
96105
def TRICORE_V1_6_1 : Architecture<"tricore-V1.6.1", "TRICOREv161", [HasV161Ops]>;
97106
def TRICORE_V1_6_2 : Architecture<"tricore-V1.6.2", "TRICOREv162", [HasV162Ops]>;
107+
def TRICORE_V1_8_0 : Architecture<"tricore-V1.8.0", "TRICOREv162", [HasV180Ops]>;
98108
def TRICORE_PCP : Architecture<"tricore-PCP", "TRICOREpcp">;
99109
def TRICORE_PCP2 : Architecture<"tricore-PCP2", "TRICOREpcp2">;
100110

@@ -114,6 +124,7 @@ def : ProcNoItin<"tc1797", [TRICORE_V1_3_1]>;
114124
def : ProcNoItin<"tc27x", [TRICORE_V1_6_1]>;
115125
def : ProcNoItin<"tc161", [TRICORE_V1_6_1]>;
116126
def : ProcNoItin<"tc162", [TRICORE_V1_6_2]>;
127+
def : ProcNoItin<"tc180", [TRICORE_V1_8_0]>;
117128
def : ProcNoItin<"tc16", [TRICORE_V1_6]>;
118129
def : ProcNoItin<"tc131", [TRICORE_V1_3_1]>;
119130
def : ProcNoItin<"tc13", [TRICORE_V1_3]>;

‎llvm/lib/Target/TriCore/TriCoreInstrFormats.td‎

Lines changed: 32 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
3030
//
3131
//===----------------------------------------------------------------------===//
3232

33-
class InstTriCore<dag outs, dag ins, string asmstr, list<dag> pattern>
33+
class I<dag outs, dag ins, string asmstr, list<dag> pattern>
3434
: Instruction {
3535

3636
let Namespace = "TriCore";
@@ -43,15 +43,15 @@ class InstTriCore<dag outs, dag ins, string asmstr, list<dag> pattern>
4343

4444
// TriCore pseudo instructions format
4545
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
46-
: InstTriCore<outs, ins, asmstr, pattern> {
46+
: I<outs, ins, asmstr, pattern> {
4747
let isPseudo = 1;
4848
}
4949

5050
//===----------------------------------------------------------------------===//
5151
// Generic 16-bit Instruction Format
5252
//===----------------------------------------------------------------------===//
5353
class T16<dag outs, dag ins, string asmstr, list<dag> pattern>
54-
: InstTriCore<outs, ins, asmstr, pattern> {
54+
: I<outs, ins, asmstr, pattern> {
5555
field bits<16> Inst;
5656
let Size = 2;
5757
field bits<16> SoftFail = 0;
@@ -61,7 +61,7 @@ class T16<dag outs, dag ins, string asmstr, list<dag> pattern>
6161
// Generic 32-bit Instruction Format
6262
//===----------------------------------------------------------------------===//
6363
class T32<dag outs, dag ins, string asmstr, list<dag> pattern>
64-
: InstTriCore<outs, ins, asmstr, pattern> {
64+
: I<outs, ins, asmstr, pattern> {
6565
field bits<32> Inst;
6666
let Size = 4;
6767
field bits<32> SoftFail = 0;
@@ -569,24 +569,34 @@ class RLC<bits<8> op1, dag outs, dag ins, string asmstr,
569569
//===----------------------------------------------------------------------===//
570570
// 32-bit RR Instruction Format: <d|op2|-|n|s2|s1|op1>
571571
//===----------------------------------------------------------------------===//
572-
class RR<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
572+
class RRBase<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
573573
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
574574

575575
bits<4> d;
576-
bits<2> n;
577576
bits<4> s2;
578577
bits<4> s1;
579578

580579
let Inst{31-28} = d;
581580
let Inst{27-20} = op2;
582581
let Inst{19-18} = 0;
583-
let Inst{17-16} = n;
584582
let Inst{15-12} = s2;
585583
let Inst{11-8} = s1;
586584
let Inst{7-0} = op1;
587585
let DecoderMethod = "DecodeRRInstruction";
588586
}
589587

588+
class RR<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
589+
list<dag> pattern>: RRBase<op1, op2, outs, ins, asmstr, pattern> {
590+
bits<2> n;
591+
let Inst{17-16} = n;
592+
}
593+
594+
class RR_n<bits<8> op1, bits<8> op2, bits<2> n, dag outs, dag ins, string asmstr,
595+
list<dag> pattern>: RRBase<op1, op2, outs, ins, asmstr, pattern> {
596+
let Inst{17-16} = n;
597+
}
598+
599+
590600
//===----------------------------------------------------------------------===//
591601
// 32-bit RR1 Instruction Format: <d|op2|n|s2|s1|op1>
592602
//===----------------------------------------------------------------------===//
@@ -651,26 +661,38 @@ class RRPW<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
651661
//===----------------------------------------------------------------------===//
652662
// 32-bit RRR Instruction Format: <d|s3|op2|-|n|s2|s1|op1>
653663
//===----------------------------------------------------------------------===//
654-
class RRR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
664+
class RRRBase<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
655665
list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
656666

657667
bits<4> d;
658668
bits<4> s3;
659-
bits<2> n;
660669
bits<4> s2;
661670
bits<4> s1;
662671

663672
let Inst{31-28} = d;
664673
let Inst{27-24} = s3;
665674
let Inst{23-20} = op2;
666675
let Inst{19-18} = 0;
667-
let Inst{17-16} = n;
668676
let Inst{15-12} = s2;
669677
let Inst{11-8} = s1;
670678
let Inst{7-0} = op1;
671679
let DecoderMethod = "DecodeRRRInstruction";
672680
}
673681

682+
class RRR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
683+
list<dag> pattern> : RRRBase<op1, op2, outs, ins, asmstr, pattern> {
684+
685+
bits<2> n;
686+
687+
let Inst{17-16} = n;
688+
}
689+
690+
class RRR_n<bits<8> op1, bits<4> op2, bits<2> n, dag outs, dag ins, string asmstr,
691+
list<dag> pattern> : RRRBase<op1, op2, outs, ins, asmstr, pattern> {
692+
693+
let Inst{17-16} = n;
694+
}
695+
674696
//===----------------------------------------------------------------------===//
675697
// 32-bit RRR1 Instruction Format: <d|s3|op2|n|s2|s1|op1>
676698
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/TriCore/TriCoreInstrInfo.td‎

Lines changed: 68 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -288,6 +288,10 @@ class IRR_a<bits<8> op1, bits<8> op2, string asmstr, RegisterClass cd=RD, Regist
288288
: RR<op1, op2, (outs cd:$d), (ins c1:$s1),
289289
asmstr # " $d, $s1", []>;
290290

291+
class IRR_a_n<bits<8> op1, bits<8> op2, bits<2> n, string asmstr, RegisterClass cd=RD, RegisterClass c1=RD>
292+
: RR_n<op1, op2, n, (outs cd:$d), (ins c1:$s1),
293+
asmstr # " $d, $s1", []>;
294+
291295
/// op R[c], R[b]
292296
class IRR_b<bits<8> op1, bits<8> op2, string asmstr, RegisterClass cd=RD, RegisterClass c2=RD>
293297
: RR<op1, op2, (outs cd:$d), (ins c2:$s1, c2:$s2),
@@ -298,10 +302,18 @@ class IRR_2<bits<8> op1, bits<8> op2, string asmstr
298302
, RegisterClass cd=RD, RegisterClass c1=RD, RegisterClass c2=RD>
299303
: RR<op1, op2, (outs cd:$d), (ins c1:$s1, c2:$s2), asmstr, []>;
300304

305+
class IRR_2_n<bits<8> op1, bits<8> op2, bits<2> n, string asmstr
306+
, RegisterClass cd=RD, RegisterClass c1=RD, RegisterClass c2=RD>
307+
: RR_n<op1, op2, n, (outs cd:$d), (ins c1:$s1, c2:$s2), asmstr, []>;
308+
301309
class IRR_dab<bits<8> op1, bits<8> op2, string asmstr,
302310
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD>
303311
: IRR_2<op1, op2, asmstr # " $d, $s1, $s2", RCd, RC1, RC2>;
304312

313+
class IRR_dab_n<bits<8> op1, bits<8> op2, bits<2> n, string asmstr,
314+
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD>
315+
: IRR_2_n<op1, op2, n, asmstr # " $d, $s1, $s2", RCd, RC1, RC2>;
316+
305317
class IRR_dba<bits<8> op1, bits<8> op2, string asmstr,
306318
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD>
307319
: IRR_2<op1, op2, asmstr # " $d, $s2, $s1", RCd, RC1, RC2>;
@@ -593,10 +605,19 @@ class IRRR<bits<8>op1, bits<4> op2, string asmstr,
593605
: RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3),
594606
asmstr # " $d, $s3, $s1, $s2", []>;
595607

608+
class IRRR_n<bits<8>op1, bits<4> op2, bits<2> n, string asmstr,
609+
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
610+
: RRR_n<op1, op2, n, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3),
611+
asmstr # " $d, $s3, $s1, $s2", []>;
612+
596613
class IRRR_d31<bits<8>op1, bits<4> op2, string asmstr,
597614
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
598615
: RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3), asmstr # " $d, $s3, $s1", []>;
599616

617+
class IRRR_d31_n<bits<8>op1, bits<4> op2, bits<2> n, string asmstr,
618+
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
619+
: RRR_n<op1, op2, n, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3), asmstr # " $d, $s3, $s1", []>;
620+
600621
class IRRR_d32<bits<8>op1, bits<4> op2, string asmstr,
601622
RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
602623
: RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3),
@@ -1846,30 +1867,62 @@ defm XOR_LT_U : mIRR_RC<0x0B, 0x32, 0x8B, 0x32, "xor.lt.u">;
18461867

18471868
/// FPU Instructions
18481869

1849-
def MADD_F_rrr : IRRR<0x6B, 0x06, "madd.f">, Requires<[HasV130_UP]>;
1850-
def MSUB_F_rrr : IRRR<0x6B, 0x07, "msub.f">, Requires<[HasV130_UP]>;
1851-
def ADD_F_rrr : IRRR_d31<0x6B, 0x02, "add.f">, Requires<[HasV130_UP]>;
1852-
def SUB_F_rrr : IRRR_d31<0x6B, 0x03, "sub.f">, Requires<[HasV130_UP]>;
1853-
def MUL_F_rrr : IRR_dab<0x4B, 0x04, "mul.f">, Requires<[HasV130_UP]>;
1854-
def DIV_F_rr : IRR_dab<0x4B, 0x05, "div.f">, Requires<[HasV130_UP]>;
1855-
def CMP_F_rr : IRR_dab<0x4B, 0x00, "cmp.f">, Requires<[HasV130_UP]>;
1856-
1857-
def FTOI_rr : IRR_a<0x4B, 0x10, "ftoi">, Requires<[HasV130_UP]>;
1858-
def FTOIZ_rr : IRR_a<0x4B, 0x13, "ftoiz">, Requires<[HasV131_UP]>;
1870+
def MADD_F_rrr : IRRR_n<0x6B, 0x06, 0x1, "madd.f">, Requires<[HasV130_UP]>;
1871+
def MSUB_F_rrr : IRRR_n<0x6B, 0x07, 0x1, "msub.f">, Requires<[HasV130_UP]>;
1872+
def MADD_DF_rrr : IRRR_n<0x6B, 0x06, 0x2, "madd.df", RE, RE, RE, RE>, Requires<[HasV180_UP]>;
1873+
def MSUB_DF_rrr : IRRR_n<0x6B, 0x07, 0x2, "msub.df", RE, RE, RE, RE>, Requires<[HasV180_UP]>;
1874+
def ADD_F_rrr : IRRR_d31_n<0x6B, 0x02, 0x1, "add.f">, Requires<[HasV130_UP]>;
1875+
def ADD_DF_rrr : IRRR_d31_n<0x6B, 0x02, 0x2, "add.df", RE, RE, RE, RE>, Requires<[HasV180_UP]>;
1876+
def SUB_F_rrr : IRRR_d31_n<0x6B, 0x03, 0x1, "sub.f">, Requires<[HasV130_UP]>;
1877+
def SUB_DF_rrr : IRRR_d31_n<0x6B, 0x03, 0x2, "sub.df", RE, RE, RE, RE>, Requires<[HasV180_UP]>;
1878+
def MUL_F_rrr : IRR_dab_n<0x4B, 0x04, 0x01, "mul.f">, Requires<[HasV130_UP]>;
1879+
def MUL_DF_rrr : IRR_dab_n<0x4B, 0x04, 0x02, "mul.df", RE, RE, RE>, Requires<[HasV180_UP]>;
1880+
def DIV_F_rr : IRR_dab_n<0x4B, 0x05, 0x01, "div.f">, Requires<[HasV130_UP]>;
1881+
def DIV_DF_rr : IRR_dab_n<0x4B, 0x05, 0x02, "div.df", RE, RE, RE>, Requires<[HasV180_UP]>;
1882+
def CMP_F_rr : IRR_dab_n<0x4B, 0x00, 0x01, "cmp.f">, Requires<[HasV130_UP]>;
1883+
def CMP_DF_rr : IRR_dab_n<0x4B, 0x00, 0x02, "cmp.df", RD, RE, RE>, Requires<[HasV180_UP]>;
1884+
def MIN_F_rr : IRR_dab_n<0x4B, 0x33, 0x01, "min.f">, Requires<[HasV180_UP]>;
1885+
def MIN_DF_rr : IRR_dab_n<0x4B, 0x33, 0x02, "min.df", RE, RE, RE>, Requires<[HasV180_UP]>;
1886+
def MAX_F_rr : IRR_dab_n<0x4B, 0x32, 0x01, "max.f">, Requires<[HasV180_UP]>;
1887+
def MAX_DF_rr : IRR_dab_n<0x4B, 0x32, 0x02, "max.df", RE, RE, RE>, Requires<[HasV180_UP]>;
1888+
1889+
def FTOI_rr : IRR_a_n<0x4B, 0x10, 0x01, "ftoi">, Requires<[HasV130_UP]>;
1890+
def DFTOI_rr : IRR_a_n<0x4B, 0x10, 0x02, "dftoi", RD, RE>, Requires<[HasV180_UP]>;
1891+
def FTOIZ_rr : IRR_a_n<0x4B, 0x13, 0x01, "ftoiz">, Requires<[HasV131_UP]>;
1892+
def DFTOIZ_rr : IRR_a_n<0x4B, 0x13, 0x02, "dftoiz", RD, RE>, Requires<[HasV180_UP]>;
1893+
def FTOIN_rr : IRR_a_n<0x4B, 0x37, 0x01, "ftoin">, Requires<[HasV180_UP]>;
1894+
def DFTOIN_rr : IRR_a_n<0x4B, 0x37, 0x02, "dftoin", RD, RE>, Requires<[HasV180_UP]>;
1895+
def DFTOL_rr : IRR_a_n<0x4B, 0x1A, 0x02, "dftol", RE, RE>, Requires<[HasV180_UP]>;
1896+
def DFTOLZ_rr : IRR_a_n<0x4B, 0x1B, 0x02, "dftolz", RE, RE>, Requires<[HasV180_UP]>;
1897+
def DFTOUL_rr : IRR_a_n<0x4B, 0x1E, 0x02, "dftoul", RE, RE>, Requires<[HasV180_UP]>;
1898+
def DFTOULZ_rr : IRR_a_n<0x4B, 0x1F, 0x02, "dftoulz", RE, RE>, Requires<[HasV180_UP]>;
1899+
def ABS_F_rr : IRR_a_n<0x4B, 0x30, 0x01, "abs.f">, Requires<[HasV180_UP]>;
1900+
def ABS_DF_rr : IRR_a_n<0x4B, 0x30, 0x02, "abs.df", RE, RE>, Requires<[HasV180_UP]>;
1901+
def NEG_F_rr : IRR_a_n<0x4B, 0x31, 0x01, "neg.f">, Requires<[HasV180_UP]>;
1902+
def NEG_DF_rr : IRR_a_n<0x4B, 0x31, 0x02, "neg.df", RE, RE>, Requires<[HasV180_UP]>;
18591903

18601904
def FTOQ31_rr : IRR_dab<0x4B, 0x11, "ftoq31">, Requires<[HasV130_UP]>;
18611905
def FTOQ31Z_rr: IRR_dab<0x4B, 0x18, "ftoq31z">, Requires<[HasV131_UP]>;
18621906

1863-
def FTOU_rr : IRR_a<0x4B, 0x12, "ftou">, Requires<[HasV130_UP]>;
1864-
def FTOUZ_rr : IRR_a<0x4B, 0x17, "ftouz">, Requires<[HasV131_UP]>;
1907+
def FTOU_rr : IRR_a_n<0x4B, 0x12, 0x01, "ftou">, Requires<[HasV130_UP]>;
1908+
def DFTOU_rr : IRR_a_n<0x4B, 0x12, 0x02, "dftou", RD, RE>, Requires<[HasV180_UP]>;
1909+
def FTOUZ_rr : IRR_a_n<0x4B, 0x17, 0x01, "ftouz">, Requires<[HasV131_UP]>;
1910+
def DFTOUZ_rr : IRR_a_n<0x4B, 0x17, 0x02, "dftouz", RD, RE>, Requires<[HasV180_UP]>;
18651911

18661912
def FTOHP_rr : IRR_a<0x4B, 0x25, "ftohp">, Requires<[HasV162_UP]>;
18671913

18681914
def HPTOF_rr : IRR_a<0x4B, 0x24, "hptof">, Requires<[HasV162_UP]>;
1869-
def ITOF_rr : IRR_a<0x4B, 0x14, "itof">, Requires<[HasV130_UP]>;
1915+
def ITOF_rr : IRR_a_n<0x4B, 0x14, 0x01, "itof">, Requires<[HasV130_UP]>;
1916+
def ITODF_rr : IRR_a_n<0x4B, 0x14, 0x02, "itodf", RE, RD>, Requires<[HasV180_UP]>;
18701917

18711918
def Q31TOF_rr : IRR_dab<0x4B, 0x15, "q31tof">, Requires<[HasV130_UP]>;
1872-
def QSEED_F_rr : IRR_a<0x4B, 0x19, "qseed.f">, Requires<[HasV130_UP]>;
1919+
def QSEED_F_rr : IRR_a_n<0x4B, 0x19, 0x01, "qseed.f">, Requires<[HasV130_UP]>;
1920+
def QSEED_DF_rr : IRR_a_n<0x4B, 0x19, 0x02, "qseed.df", RE, RE>, Requires<[HasV180_UP]>;
18731921

18741922
def UPDFL_rr : IRR_R1<0x4B, 0x0C, "updfl">, Requires<[HasV130_UP]>;
1875-
def UTOF_rr : IRR_a<0x4B, 0x16, "utof">, Requires<[HasV130_UP]>;
1923+
def UTOF_rr : IRR_a_n<0x4B, 0x16, 0x01, "utof">, Requires<[HasV130_UP]>;
1924+
def UTODF_rr : IRR_a_n<0x4B, 0x16, 0x02, "utodf", RE, RD>, Requires<[HasV180_UP]>;
1925+
def LTODF_rr : IRR_a_n<0x4B, 0x26, 0x02, "ltodf", RE, RE>, Requires<[HasV180_UP]>;
1926+
def ULTODF_rr : IRR_a_n<0x4B, 0x27, 0x02, "ultodf", RE, RE>, Requires<[HasV180_UP]>;
1927+
def DFTOF_rr : IRR_a_n<0x4B, 0x28, 0x02, "dftof", RD, RE>, Requires<[HasV180_UP]>;
1928+
def FTODF_rr : IRR_a_n<0x4B, 0x29, 0x02, "ftodf", RE, RD>, Requires<[HasV180_UP]>;

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