diff --git a/AddExtensions.md b/AddExtensions.md new file mode 100644 index 000000000000..1c263a9fc76b --- /dev/null +++ b/AddExtensions.md @@ -0,0 +1,70 @@ +# Adding new extensions + +Some architectures have processor extensions not defined in upstream LLVM. +If we want to have them in Capstone, we can write the `.td` files for them here. + +The process is rather straight forward. + +1. Write all definitions into a new `llvm/lib/Target//NewExtension.td` file. +2. Define a feature and property for the new extension: + ```python + def FeatureExtensionName : SubtargetFeature<"extenion_name", "HasExtensionName", "true", + "Enable the new extension bla bla bla.">; + + def HasExtensionName : Predicate<"Subtarget->hasExtensionName()">, + AssemblerPredicate<(all_of FeatureExtensionName), "extenion_name">; + ``` +3. Ensure the newly defined instructions have `let Predicates = [HasExtensionName];` set. +4. Add or exclude the extension from existing processor models: + - Search for `list UnsupportedFeatures` in the target directory. + Add `HasExtensionName` to all processor models which don't support it. + - The processor models which do support it, need the instructions in the scheduler. + Check how it is done in the processor's scheduler file. +5. Include the `NewExtension.td` at the bottom of `InstrInfo.td` with `include "NewExtension.td"`. + +**Note:** As an example you can refer to `AArch64AppleProprietary.td`. +Also search for `HasAMX` and `FeatureAMX` to see how those flags are used in the files. + +# Deprecated Features + +Capstone needs to support features which were removed by LLVM in the past. +Here we explain how to reintroduce them. + +## Reintroduction + +To get the old features back we copy them from the old `.td` files and include them in the new ones. + +To include removed features from previous LLVM versions do the following: + +1. Checkout the last LLVM version the feature was present. +2. Copy all feature related definitions into a `Deprecated.td` file. +3. Checkout the newest LLVM version again. +4. Wrap the different definition types in include guards. For example the `InstrInfo` definitions could be included in: + + ``` + #ifndef INCLUDED_CAPSTONE_DEPR_INSTR + #ifdef CAPSTONE_DEPR_INSTR + #define INCLUDED_CAPSTONE_DEPR_INSTR // Ensures it is only included once + + [Instruction definitions of removed feature] + + #endif // INCLUDED_CAPSTONE_DEPR_INSTR + #endif // CAPSTONE_DEPR_INSTR + ``` + + _Note that the order of `#ifndef` and `#ifdef` matters (otherwise you'll get an error from `tblgen`)._ + + **This step is somewhat optional. It might be enough to write all definitions in a single file and `#include` them once into `ARCHInstrInfo.td` at the bottom.** + +5. Include the definitions in the current definition files with: + + ``` + #define CAPSTONE_DEPR_INSTR + include "Deprecated.td" + ``` + +## Notes +- It is possible that you have to change some definitions slightly. +Because certain classes no longer exist or were replaced (e.g.: `GCCBuiltin` -> `ClangBuiltin`). +- Some processors might need the feature flag (`Has`) added +in their `UnsupportedFeatures` list. diff --git a/DeprecatedFeatures.md b/DeprecatedFeatures.md deleted file mode 100644 index b7975dc41afd..000000000000 --- a/DeprecatedFeatures.md +++ /dev/null @@ -1,41 +0,0 @@ -# Deprecated Features - -Capstone needs to support features which were removed by LLVM in the past. -Here we explain how to reintroduce them. - -## Reintroduction - -To get the old features back we copy them from the old `.td` files and include them in the new ones. - -To include removed features from previous LLVM versions do the following: - -1. Checkout the last LLVM version the feature was present. -2. Copy all feature related definitions into a `Deprecated.td` file. -3. Checkout the newest LLVM version again. -4. Wrap the different definition types in include guards. For example the `InstrInfo` definitions could be included in: - - ``` - #ifndef INCLUDED_CAPSTONE_DEPR_INSTR - #ifdef CAPSTONE_DEPR_INSTR - #define INCLUDED_CAPSTONE_DEPR_INSTR // Ensures it is only included once - - [Instruction definitions of removed feature] - - #endif // INCLUDED_CAPSTONE_DEPR_INSTR - #endif // CAPSTONE_DEPR_INSTR - ``` - - _Note that the order of `#ifndef` and `#ifdef` matters (otherwise you'll get an error from `tblgen`)._ - -5. Include the definitions in the current definition files with: - - ``` - #define CAPSTONE_DEPR_INSTR - include "Deprecated.md" - ``` - -## Notes -- It is possible that you have to change some definitions slightly. -Because certain classes no longer exist or were replaced (e.g.: `GCCBuiltin` -> `ClangBuiltin`). -- Some new processors might need to have the feature flag (`Has`) added -to their `UnsupportedFeatures` list. diff --git a/README.md b/README.md index ae5188efa9b5..1fe08d767e64 100644 --- a/README.md +++ b/README.md @@ -123,4 +123,4 @@ You need to search for the instruction or operands with missing or incorrect val ``` - If certain target features (e.g. architecture extensions) were removed from LLVM or you want to add your own, -checkout [DeprecatedFeatures.md](DeprecatedFeatures.md). +checkout [AddExtensions.md](AddExtensions.md). diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index feabd137c0cf..43e9b012b2d9 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -1395,6 +1395,7 @@ def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B", FeatureLdpAlignedOnly, FeatureStpAlignedOnly]>; + def ProcessorFeatures { list A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; @@ -1467,35 +1468,56 @@ def ProcessorFeatures { FeatureSVE, FeatureComplxNum]; list Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, FeatureFullFP16]; + + // Capstone addition: + // Proprietary system instructions are added to all Apple processors. + // Even if we don't know if they are actually supported. + list AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, - FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; + FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg, + FeatureAppleSys]; list AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureCRC, - FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; + FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH, + FeatureAppleSys]; + + // Capstone addition: + // Note about the Mul53 extension. According to https://gist.github.com/TrungNguyen1909/5b323edda9a21550a1621af506e8ce5f + // The mul53 instructions are use in Apple's H10 processor (part of AirPots according to apple.fandom.com). + // This processor doesn't exist in LLVM. But the reference claims H10 is equivalent to A11. list AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, - FeatureNEON, FeaturePerfMon, FeatureFullFP16]; + FeatureNEON, FeaturePerfMon, FeatureFullFP16, + FeatureMUL53, FeatureAppleSys]; list AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16]; list AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, - FeatureFP16FML, FeatureSHA3]; + FeatureFP16FML, FeatureSHA3, FeatureAppleSys]; + + // Capstone addition AMX: The A14 onwards are variants (same generation) + // of the Apple M series processors. + // To my knowledge it is not documented if those processors actually support AMX, + // but we add it here as feature anyways. Simply because it is too much work + // adding a model for the Apple M series processors. Capstone currently + // doesn't care about the LLVM processor definitions. list AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFRInt3264, FeatureSpecRestrict, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, FeatureFullFP16, FeatureFP16FML, FeatureSHA3, - FeatureAltFPCmp]; + FeatureAltFPCmp, FeatureAMX, FeatureAppleSys]; list AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, - FeatureFullFP16, FeatureFP16FML]; + FeatureFullFP16, FeatureFP16FML, FeatureAMX, + FeatureAppleSys]; list AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, - FeatureHCX]; + FeatureHCX, FeatureAMX, FeatureAppleSys]; list AppleA17 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, - FeatureHCX]; + FeatureHCX, FeatureAMX, FeatureAppleSys]; list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, FeaturePerfMon]; list ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, diff --git a/llvm/lib/Target/AArch64/AArch64AppleProprietary.td b/llvm/lib/Target/AArch64/AArch64AppleProprietary.td new file mode 100644 index 000000000000..037918b56462 --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64AppleProprietary.td @@ -0,0 +1,219 @@ +// SPDX-FileCopyrightText: 2025 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only +// +// Definitions of Apple's proprietary instructions. + + +def FeatureAMX : SubtargetFeature<"amx", "HasAMX", "true", + "Enable proprietary Apple AArch64 extension AMX.">; + +def HasAMX : Predicate<"Subtarget->hasAMX()">, + AssemblerPredicate<(all_of FeatureAMX), "amx">; + +class ReservedI pattern = [], string constraints = ""> + : I { + let Inst{31-29} = 0b000; + let Inst{28-25} = 0b0000; + let Inst{24-21} = 0b0001; + let Constraints = constraints; +} + +// +// ====== AMX ====== +// +// Reference: https://github.com/corsix/amx + +// For now not all sub registers are defined here. +// Because they cannot be addressed explicit or implicitly +// by the AMX instructions. +// The registers it uses are encoded in the GPR value +// and hence only known during runtime. +def X_LANE : AArch64Reg<0, "X">; +def Y_LANE : AArch64Reg<0, "Y">; +def Z_MATRIX : AArch64Reg<0, "Z">; + +class AppleAMX amx_opcode, dag oops, dag iops, string asm, string operands, + list pattern = []> + : ReservedI { + bits<5> src; + let Inst{20-16} = 0b00000; + let Inst{15-12} = 0b0001; + let Inst{11-10} = 0b00; + let Inst{9-5} = amx_opcode; + let Inst{4-0} = src; + + let Predicates = [HasAMX]; +} + +let mayLoad = 1 in { + let Defs = [X_LANE] in + def LDX : AppleAMX<0, (outs), (ins GPR64:$src), "ldx", "\t$src">; + + let Defs = [Y_LANE] in + def LDY : AppleAMX<1, (outs), (ins GPR64:$src), "ldy", "\t$src">; + + let Defs = [Z_MATRIX] in { + def LDZ : AppleAMX<4, (outs), (ins GPR64:$src), "ldz", "\t$src">; + def LDZI : AppleAMX<6, (outs), (ins GPR64:$src), "ldzi", "\t$src">; + } +} + +let mayStore = 1 in { + let Uses = [X_LANE] in + def STX : AppleAMX<2, (outs), (ins GPR64:$src), "stx", "\t$src">; + + let Uses = [Y_LANE] in + def STY : AppleAMX<3, (outs), (ins GPR64:$src), "sty", "\t$src">; + + let Uses = [Z_MATRIX] in { + def STZ : AppleAMX<5, (outs), (ins GPR64:$src), "stz", "\t$src">; + def STZI : AppleAMX<7, (outs), (ins GPR64:$src), "stzi", "\t$src">; + } +} + +// The "set" and "clr" instruction techincally are defined by having an +// immediate value operand. +// I assume there is some kind of "amx state change" instruction. +// The immediate value then determines what specific instruction it is. +// Similar like the hint instructions which have alias depending on some +// bits. +// Since the underlying "state change instruction" is not documented +// I make it an instruction with hard-coded bits[4:0] and no +// immediate operand. +let Defs = [X_LANE, Y_LANE, Z_MATRIX] in +def SET : AppleAMX<17, (outs), (ins), "set", ""> { + let Inst{4-0} = 0b00000; +} + +def CLR : AppleAMX<17, (outs), (ins), "clr", ""> { + let Inst{4-0} = 0b00001; +} + +// These two instructions decode differently depending on the operand value. +// They also use and define different registers. +// All of it is onlye known during runtime, so implicit Defs and Uses +// are omitted here. +def EXTRX : AppleAMX<8, (outs), (ins GPR64:$src), "extrx", "\t$src">; +def EXTRY : AppleAMX<9, (outs), (ins GPR64:$src), "extry", "\t$src">; + +let Uses = [X_LANE, Y_LANE, Z_MATRIX], Defs = [Z_MATRIX] in { + def FMA64 : AppleAMX<10, (outs), (ins GPR64:$src), "fma64", "\t$src">; + def FMS64 : AppleAMX<11, (outs), (ins GPR64:$src), "fms64", "\t$src">; + def FMA32 : AppleAMX<12, (outs), (ins GPR64:$src), "fma32", "\t$src">; + def FMS32 : AppleAMX<13, (outs), (ins GPR64:$src), "fms32", "\t$src">; + def FMA16 : AppleAMX<15, (outs), (ins GPR64:$src), "fma16", "\t$src">; + def FMS16 : AppleAMX<16, (outs), (ins GPR64:$src), "fms16", "\t$src">; + def VECFP : AppleAMX<19, (outs), (ins GPR64:$src), "vecfp", "\t$src">; + def MAC16 : AppleAMX<14, (outs), (ins GPR64:$src), "mac16", "\t$src">; + def MATFP : AppleAMX<21, (outs), (ins GPR64:$src), "matfp", "\t$src">; +} + +// These instructions might read Z as well (depends on bit 47 in the operand value). +// But the indeirect read is only known during runtime when the operand value is known. +// So here we don't add Z to the implicit read list. +let Uses = [X_LANE, Y_LANE], Defs = [Z_MATRIX] in { + def VECINT : AppleAMX<18, (outs), (ins GPR64:$src), "vecint", "\t$src">; + def MATINT : AppleAMX<20, (outs), (ins GPR64:$src), "matint", "\t$src">; +} + +def GENLUT : AppleAMX<22, (outs), (ins GPR64:$src), "genlut", "\t$src">; + +// +// ====== MUL53 ====== +// +// Reference: https://gist.github.com/TrungNguyen1909/5b323edda9a21550a1621af506e8ce5f + +def FeatureMUL53 : SubtargetFeature<"mul53", "HasMUL53", "true", + "Enable proprietary Apple AArch64 extension Mul53.">; + +def HasMUL53 : Predicate<"Subtarget->hasMUL53()">, + AssemblerPredicate<(all_of FeatureMUL53), "mul53">; + +// It is an assumption that the mul53 opcode field is 5 bits. It might as well +// is more norrow or wider. +class AppleMUL53 mul53_opcode, dag oops, dag iops, string asm, string operands, + list pattern = [], string constraints = ""> + : ReservedI { + bits<5> Vn; + bits<5> Vm; + let Inst{20-15} = 0b000000; + let Inst{14-10} = mul53_opcode; + let Inst{9-5} = Vm; + let Inst{4-0} = Vn; + + let Predicates = [HasMUL53]; +} + +def MUL53LO : AppleMUL53<0, (outs V128:$Vn_wb), (ins V128:$Vn, V128:$Vm), "mul53lo.2d", "\t$Vn, $Vm", [], "$Vn = $Vn_wb">; +def MUL53HI : AppleMUL53<1, (outs V128:$Vn_wb), (ins V128:$Vn, V128:$Vm), "mul53hi.2d", "\t$Vn, $Vm", [], "$Vn = $Vn_wb">; + +// +// ====== System instructions ====== +// +// Reference: https://github.com/AsahiLinux/docs/blob/main/docs/hw/cpu/apple-instructions.md + + +def FeatureAppleSys : SubtargetFeature<"apple-sys", "HasAppleSys", "true", + "Enable proprietary Apple system instructions.">; + +def HasAppleSys : Predicate<"Subtarget->hasAppleSys()">, + AssemblerPredicate<(all_of FeatureAppleSys), "apple-sys">; + + +// +// GL instructions +// +// See: https://github.com/AsahiLinux/docs/blob/main/docs/hw/cpu/sprr-gxf.md +// + +def GEXIT : ReservedI<(outs), (ins), "gexit", "">, Sched<[WriteSys]> { + let Inst{20-0} = 0b000000001010000000000; + let Predicates = [HasAppleSys]; +} + +def GENTER : ReservedI<(outs), (ins simm5_32b:$perm), "genter", "\t$perm">, Sched<[WriteSys]> { + bits<5> perm; + let Inst{20-5} = 0b0000000010100001; + // The permission of the pages. See document + let Inst{4-0} = perm; + let Predicates = [HasAppleSys]; +} + +let mayLoad = 1, mayStore = 1 in { +def WKDMC : ReservedI<(outs GPR64:$src_wb), (ins GPR64:$dst, GPR64:$src), "wkdmc", "\t$dst, $src", [], "$src = $src_wb">, Sched<[WriteSys]> { + bits<5> src; + bits<5> dst; + let Inst{20-10} = 0b00000000010; + let Inst{9-5} = dst; + let Inst{4-0} = src; + let Predicates = [HasAppleSys]; +} + +def WKDMD : ReservedI<(outs GPR64:$src_wb), (ins GPR64:$dst, GPR64:$src), "wkdmd", "\t$dst, $src", [], "$src = $src_wb">, Sched<[WriteSys]> { + bits<5> src; + bits<5> dst; + let Inst{20-10} = 0b00000000011; + let Inst{9-5} = dst; + let Inst{4-0} = src; + let Predicates = [HasAppleSys]; +} +} + +def AT_AS1ELX : ReservedI<(outs GPR64:$Ra_wb), (ins GPR64:$Ra), "at_as1elx", "\t$Ra", [], "$Ra = $Ra_wb">, Sched<[WriteSys]> { + bits<5> Ra; + let Inst{20-5} = 0b0000000010100010; + let Inst{4-0} = Ra; + let Predicates = [HasAppleSys]; +} + +def apple_sys_barrier_op : Operand { + let PrintMethod = "printAppleSysBarrierOption"; +} + +def SDSB : ReservedI<(outs), (ins apple_sys_barrier_op:$CRm), "sdsb", "\t$CRm">, Sched<[WriteBarrier]> { + bits<4> CRm; + let Inst{20-4} = 0b00000000101000110; + let Inst{3-0} = CRm; +} + diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 59020f3af614..c8448375ae8f 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -4294,6 +4294,7 @@ class BaseLoadStoreUnscale sz, bit V, bits<2> opc, dag oops, dag iops, // Armv8.4 LDAPR & STLR with Immediate Offset instruction multiclass BaseLoadUnscaleV84 sz, bits<2> opc, DAGOperand regtype > { + let mayLoad = 1 in def i : BaseLoadStoreUnscale, Sched<[WriteST]> { @@ -4306,6 +4307,7 @@ multiclass BaseLoadUnscaleV84 sz, bits<2> opc, multiclass BaseStoreUnscaleV84 sz, bits<2> opc, DAGOperand regtype > { + let mayStore = 1 in def i : BaseLoadStoreUnscale, @@ -4319,7 +4321,7 @@ multiclass BaseStoreUnscaleV84 sz, bits<2> opc, multiclass LoadUnscaled sz, bit V, bits<2> opc, DAGOperand regtype, string asm, list pattern> { - let AddedComplexity = 1 in // try this before LoadUI + let AddedComplexity = 1, mayLoad = 1 in // try this before LoadUI def i : BaseLoadStoreUnscale, Sched<[WriteLD]>; @@ -4330,7 +4332,7 @@ multiclass LoadUnscaled sz, bit V, bits<2> opc, DAGOperand regtype, multiclass StoreUnscaled sz, bit V, bits<2> opc, DAGOperand regtype, string asm, list pattern> { - let AddedComplexity = 1 in // try this before StoreUI + let AddedComplexity = 1, mayStore = 1 in // try this before StoreUI def i : BaseLoadStoreUnscale, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index fb83038f211b..55622c15c9fd 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -9595,3 +9595,4 @@ include "AArch64InstrAtomics.td" include "AArch64SVEInstrInfo.td" include "AArch64SMEInstrInfo.td" include "AArch64InstrGISel.td" +include "AArch64AppleProprietary.td" diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td index c714bad92b7f..ce63bd69badc 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA53.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td @@ -29,7 +29,7 @@ def CortexA53Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } diff --git a/llvm/lib/Target/AArch64/AArch64SchedA55.td b/llvm/lib/Target/AArch64/AArch64SchedA55.td index cb77be350d12..409c6befa715 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA55.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA55.td @@ -29,7 +29,7 @@ def CortexA55Model : SchedMachineModel { let PostRAScheduler = 1; // Enable PostRA scheduler pass. let CompleteModel = 0; // Covers instructions applicable to Cortex-A55. - list UnsupportedFeatures = [HasSVE, HasMTE]; + list UnsupportedFeatures = [HasSVE, HasMTE, HasAMX, HasMUL53, HasAppleSys]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td index ebbc3b72b506..9342a396bbe2 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA57.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td @@ -34,7 +34,7 @@ def CortexA57Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td index d6fe84a2c9c9..19ebf0557ae0 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td @@ -23,7 +23,7 @@ def A64FXModel : SchedMachineModel { list UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F, [HasMTE, HasMatMulInt8, HasBF16, HasPAuth, HasPAuthLR, HasCPA, - HasCSSC]); + HasCSSC, HasAMX, HasMUL53, HasAppleSys]); let FullInstRWOverlapCheck = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td index cf9f50c2784b..92bcbe87e716 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td @@ -27,7 +27,7 @@ def Ampere1Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, SMEUnsupported.F, PAUnsupported.F, - [HasMTE]); + [HasMTE, HasAMX, HasMUL53, HasAppleSys]); } let SchedModel = Ampere1Model in { diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td index 9c4f000cf351..d61dd05c860e 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td +++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td @@ -26,7 +26,8 @@ def Ampere1BModel : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, SMEUnsupported.F, - PAUnsupported.F); + PAUnsupported.F, + [HasAMX, HasMUL53, HasAppleSys]); } let SchedModel = Ampere1BModel in { diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td index 48324654949c..339bd3b891bb 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td +++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td @@ -872,4 +872,26 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +// Proprietary Apple instructions + +// +// AMX extension +// + +def : InstRW<[WriteVLD], + (instregex "LD[XYZ]I?$")>; +def : InstRW<[WriteVST], + (instregex "ST[XYZ]I?$")>; +def : InstRW<[WriteVST], + (instrs SET, CLR)>; +def : InstRW<[WriteVLD, WriteVST], + (instrs FMA64, FMS64, FMA32, FMS32, FMA16, FMS16, VECFP, MAC16, MATFP, VECINT, MATINT, GENLUT, EXTRX, EXTRY)>; + +// +// MUL53 extension +// + +def : InstRW<[WriteVq], + (instrs MUL53LO, MUL53HI)>; + } // SchedModel = CycloneModel diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td index 6fc4ec3ae41b..b9408f68afe7 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td +++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td @@ -27,7 +27,7 @@ def ExynosM3Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td index 5163de280f2e..864e54817b8c 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td +++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td @@ -27,7 +27,7 @@ def ExynosM4Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td index 2ccbe1614dcd..a2b090c559ad 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td +++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td @@ -27,7 +27,7 @@ def ExynosM5Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td index e9172e82b099..fa8db8e1db87 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td @@ -26,7 +26,7 @@ def FalkorModel : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td index 258b34c38898..4d784faf8976 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td +++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td @@ -30,7 +30,7 @@ def KryoModel : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td index 524fa33f498b..98ba2c86f472 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td @@ -25,7 +25,7 @@ def NeoverseN1Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(PAUnsupported.F, SMEUnsupported.F, SVEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td index 8ec124954362..8da4046d1451 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td @@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel { let CompleteModel = 1; list UnsupportedFeatures = !listconcat(SMEUnsupported.F, - [HasSVE2p1, HasPAuthLR, HasCPA, HasCSSC]); + [HasSVE2p1, HasPAuthLR, HasCPA, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td index 613db353cb0a..6d4e5cc596c4 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td @@ -29,7 +29,7 @@ def NeoverseV1Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVE2Unsupported.F, SMEUnsupported.F, [HasMTE, HasCPA, - HasCSSC]); + HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td index e7de40fdf1de..15541d6afd3a 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td @@ -23,7 +23,7 @@ def NeoverseV2Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SMEUnsupported.F, [HasSVE2p1, HasCPA, - HasCSSC]); + HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td index 0ae9a69fd482..0280af492ca5 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td +++ b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td @@ -27,7 +27,7 @@ def TSV110Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); } // Define each kind of processor resource and number available on the TSV110, diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td index 8df3f56e4573..ed194c11ba97 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td +++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td @@ -28,7 +28,7 @@ def ThunderXT8XModel : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td index ef4baa3dedff..e5070c6a8d51 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td +++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td @@ -28,7 +28,7 @@ def ThunderX2T99Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td index 796bd4b8b5c9..fcd1923fad11 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td +++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td @@ -27,7 +27,7 @@ def ThunderX3T110Model : SchedMachineModel { list UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F, SMEUnsupported.F, - [HasMTE, HasCSSC]); + [HasMTE, HasCSSC, HasAMX, HasMUL53, HasAppleSys]); // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } diff --git a/llvm/utils/TableGen/PrinterCapstone.cpp b/llvm/utils/TableGen/PrinterCapstone.cpp index d37174a719e8..57fdd5151121 100644 --- a/llvm/utils/TableGen/PrinterCapstone.cpp +++ b/llvm/utils/TableGen/PrinterCapstone.cpp @@ -2690,8 +2690,13 @@ normalizedMnemonic(StringRef const &Mn, const bool Upper = true, static inline std::string getNormalMnemonic(StringRef TargetName, StringRef Mnemonic, const bool Upper = true, const bool ReplaceDot = true) { - StringRef RemovePattern = TargetName.equals_insensitive("ARM") ? "[{}]" : ""; - RemovePattern = TargetName.equals_insensitive("ARC") ? "[.]$" : ""; + + StringRef RemovePattern = ""; + if (TargetName.equals_insensitive("ARM") || TargetName.equals_insensitive("AArch64")) { + RemovePattern = "[{}]"; + } else if (TargetName.equals_insensitive("ARC")) { + RemovePattern = "[.]$"; + } return normalizedMnemonic(Mnemonic, Upper, ReplaceDot, RemovePattern); }